JP2666726B2 - Analog image signal conversion method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for temporarily converting a frame analog image signal into a digital signal, writing the digital signal into an image memory, reading the frame at a read cycle different from the write cycle, and converting it again to an analog image signal. An analog image signal (RGB signal) output from a personal computer (hereinafter, referred to as PC) is driven, for example, at a horizontal scanning frequency of 15.734 KHz by NTSC (National T.K.).
The present invention relates to a method and an apparatus for converting an image into an analog image signal (RGB signal) to be displayed on a television receiver (hereinafter, referred to as a TV receiver) of an elevision system committer (hereinafter, referred to as a TV receiver).

[0002]

2. Description of the Related Art Conventionally, for example, a horizontal scanning frequency of 24.82 is used.
When displaying an image of a PC driven at 62 KHz on a TV receiver, the PC has one frame per field of the TV receiver. Therefore, if the required image memory capacity is 8 bits for each of RGB, two PC frames are required. 1 which is the capacity
It becomes 2 Mbit. However, looking at the relationship between the writing and reading operations of the image memory at this time, in order to write data for one vertical scanning period (one frame for a PC) to the image memory, a P with a horizontal scanning frequency of 24.8262 kHz is required.
Since the vertical frequency of C is 56.4231 Hz, 1
It takes 7.72 ms. On the other hand, 1
To read out data (one field of the TV receiver) in the vertical scanning period, the vertical frequency of the TV receiver is 59.94H.
Since it is z, it takes 16.68 ms. Therefore, the time (1) for writing image data for one vertical scanning period
7.72 ms), the reading time (16.68 ms)
s) is shorter. Therefore, if the image memory uses only 6 Mbits having a capacity of one frame of the PC, writing of data to be displayed on the TV receiver cannot be performed in time, and the image cannot be displayed properly.

For this reason, conventionally, as the image memory capacity, a capacity twice (12 Mbits) of the capacity for one frame of the PC (6 Mbits) is used. Its behavior is
Prepare two image memories with a memory capacity of 6 Mbit, PC
Are alternately written to two image memories for each frame. In the same manner as the writing, the reading is alternately performed for each field of the TV receiver. When the reading has overtaken the writing, the same image data is read twice from the same image memory to cope with the above-mentioned problem.

[0004]

However, such a system requires an expensive image memory twice as much as one frame of a PC, thus increasing the cost as a whole. Also, the circuit scale has been increased in accordance with the number of image memories.

A first object of the present invention is to reduce the cost and the circuit scale by reducing the capacity of the image memory to half the conventional memory capacity, that is, the memory capacity for one frame of the PC. The second object is to make it possible to realize this without deteriorating the image quality.

[0006]

Therefore, in the present invention,
The analog image signal of the frame is converted into digital image data by the A / D conversion means, written into the image memory at a fixed writing cycle, read from the image memory at a predetermined reading cycle different from the writing cycle, and read by the D / A conversion means. To convert the digital image data into an analog image signal again, digital image data is written to the image memory in the following steps. The digital image data Dg1 of the current line converted by the A / D conversion means and the digital image data Dg2 of the previous line delayed by one line are converted into two A / D conversion clocks.
Multiplexing is performed so that Dg1 and Dg2 alternate with a double clock. An overtaking point at which the read cycle overtakes the write cycle is determined in advance. In the frame corresponding to the overtaking point, both Dg1 and Dg2 of the multiplexed digital image data Dg3 are written in the image memory, and in the other frames, Dg1 and Dg2 are selected and written.

For frames other than the overtaking time,
In the case of an odd frame, it is better to write the odd line of Dg1 and Dg2, and in the case of the even frame, it is better to write the even line.

[0008]

According to the present invention, the digital image data Dg1 of the current line converted by the A / D conversion means and the digital image data Dg2 of the previous line delayed by one line are converted into a clock twice the A / D conversion clock. Multiplex alternately with. FIG. 4 (1) shows the double clock. Also,
(2) of the figure shows a select signal of the multiplexer according to this clock, and its H level and L level are inverted, so that Dg1 shown in (3) and Dg2 shown in (4) in FIG. Multiplexing is performed alternately as shown in (5). Therefore, this multiplexed digital image data Dg3 of one line (for one cycle of the horizontal scanning period)
Is such that data of odd lines and data of even lines are alternately cut and connected.

In the case of an overtaking frame in which the read cycle overtakes the write cycle, if the multi-pressed digital image data Dg3 is written as it is, that is, if both odd and even lines are written into the image memory for one frame of PC, Since image data that satisfies both the odd and even fields of the TV receiver can be written in the image memory in advance, even if the read cycle exceeds the write cycle, the image from the PC can be clearly displayed on the TV receiver. Can be projected.

On the other hand, for frames other than the overtaking frame, when it is necessary to read the odd fields of the TV set, only the odd lines of the odd frames of the PC are written in the image memory in advance, and the even fields of the TV set are read out. When reading is necessary, only the even lines of the even frame of the PC are written in the image memory in advance, so by repeating reading from the same one image memory, the image from the PC is similarly converted to the TV. It can be clearly projected on the receiver. Therefore, according to the present invention, the image memory only needs to have a memory capacity for one frame of the PC.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a system configuration of an embodiment of the present invention. This apparatus includes an A / D converter 1 for converting an analog image signal from a PC (personal computer) into digital image data, a vertical filter 2 for reducing flicker, and digital image data having passed through the vertical filter 2. For one line (horizontal scanning frequency 24.8262 kHz)
A one-line delay circuit 3 for delaying by one horizontal scanning period), and a multiplexer 4 for multiplexing digital image data Dg1 of the current line which is not delayed and digital image data Dg2 of the previous line which is delayed by one line.
A single image memory 6 having a memory capacity for one frame of a PC, a memory control unit 5 for performing writing control and reading control for writing the multi-pressed digital image data Dg3 to the image memory 6, and an image memory A digital-to-analog (D / A) converter 7 for converting the digital image data read out from the digital image signal 6 into an analog image signal again, and a timing generator 8 for generating various clocks for the operation timing of these circuits. I have.

Next, the operation of the apparatus shown in FIG. 1 will be described. The A / D conversion clock (A / DCLK) output from the timing generator 8 is input to the A / D converter 1 and
An analog image signal (RGB signal) output from C is converted into digital image data. The band of the digital image data output from the A / D converter 1 is limited by the vertical filter 2. Here, by limiting the band, T
It is possible to reduce flicker when the image is projected on the V receiver.

The digital image data that has passed through the vertical filter 2 is delayed by one line by a one-line delay circuit 3. The multiplexer 4 includes digital image data Dg1 of the current line which is not delayed by the one-line delay circuit 3,
The digital image data Dg2 of the previous line delayed by the one-line delay circuit 3 is input at the same time. The write clock (WCLK) having a time interval twice as long as the A / D conversion clock (A / DCLK) is input from the timing generator 8 to the multiplexer 4. FIG. 4A shows this write clock (WCLK). The multiplexer 4 converts the digital image data Dg1 and the digital image data Dg2 into an A / D conversion clock (A / DCLK) by the select signal (SEL) of FIG. 2B inverted according to the write clock (WCLK). Select alternately with twice the clock. In the example shown, when this select signal is at the H level, the digital image data Dg of the current line is displayed.
1 is selected and the digital image data Dg2 of the previous line is selected when it is at the L level. Therefore, the digital image data Dg3 after the multi-press is in a state where Dg1 and Dg2 are alternately arranged as shown in (5) of FIG. This is also a state where the data of the odd lines and the data of the even lines are alternately arranged partly.

The memory control unit 5 is divided into a memory write system control unit 51 and a memory read system control unit 52. The digital image data Dg3 after the multi-press is stored in an image memory by a write control signal from the memory write system control unit 51. 6 is written as described below. The written digital image data is read out by a read control signal from the memory read system control unit 52 as described later, and
Input to the A converter 7. The D / A converter 7 converts the digital image data Dg read from the image memory 6
4 is converted into an analog image signal in accordance with the D / A conversion clock (D / ACLK) from the timing generation unit 8. This D / A conversion clock is based on the horizontal scanning frequency of 15.734 KHz of the TV receiver.
It is converted to a 5.734 KHz analog image signal.

FIG. 2 shows a configuration example of the memory write system control unit 51 of the memory control unit 5. The memory write system control unit 51 includes an effective screen area determination unit 10, a line determination unit 11, an AND circuit 12, an overtaking determination unit 13, an overtaking inversion signal generation unit 14, a frame inversion unit 15, and an address determination unit 1.
6, the EX-OR circuit 17, the frame discriminator 18, and the EX-
An OR circuit 19 and an OR circuit 20 are provided.

The effective screen area discriminating section 10 does not show the specific structure, but decodes the values of a horizontal write counter and a vertical write counter (a counter for two frames of PC) at the beginning and end of the effective screen area. Using a flip-flop and an AND circuit, an effective screen area signal is output at H level in the effective screen area and at L level otherwise, as shown in (3) of FIG.

The line determining unit 11 determines whether the line is an odd line or an even line by decoding the maximum value of the horizontal line counter.
A line discrimination signal is output as shown in FIG. 6 (2), which becomes H level, and in the case of an even line, becomes L level as shown in FIG. 6 (2). An AND circuit 12 ANDs the line discrimination signal and the effective screen area signal to generate a write enable signal (WE) for enabling / disabling the write address pointer. Since the write enable signal (WE) becomes H level only in the effective screen area at the time of the odd number line as shown in (4) in FIGS. 5 to 16, the write address pointer is incremented only during that period, Stops at L level.

As described above, since the writing and reading timings of the image memory 6 are different from each other, a phenomenon occurs in which reading overtakes writing. Therefore, the overtaking determination unit 1
3 decodes an intermediate value (a value between a PC odd frame and a PC even frame) of a vertical write counter (a counter for two PC frames), and decodes a vertical read counter (TV) by a pulse signal generated at that time. The value of the counter for two fields of the receiver is latched. Then, by inputting the value to a window comparator for determining the overtaking period, it is determined in advance whether or not the overtaking period will occur, and if it is determined that the overtaking period will occur, the odd frame of the PC immediately after that is determined. An H level is output as shown in (9) of FIGS. 9 and 10 for the overtaking frame (hereinafter, referred to as an overtaking frame), and when the overtaking frame is over, the write counter is reset by a reset pulse output from the timing generation unit 8. I do. Using the reset pulse at this time, the overtaking inversion signal generating unit 14 outputs a signal that inverts from (6) in FIG. 10 to (6) in FIG. 11 each time the overtaking frame ends.

The frame inverting section 15 outputs a signal which is inverted each time a PC frame changes between an odd number and an even number. This signal goes low when the frame is odd as shown in FIG. 5 and FIG. 6 (5), and goes high when the frame is even as shown in FIG. 7 and FIG. The exclusive OR of the frame inversion signal and the overtaking inversion signal from the overtaking inversion signal generation unit 14 is performed by the EX-OR circuit 17, so that the frame discrimination unit 18 performs the processing shown in FIGS. The L level as shown in (7), the H level as shown in (7) of FIGS. 7 and 8 in the even frame of the PC, and FIGS. 9 and 1 in the overtaking frame.
A frame discrimination signal which becomes L level as shown in (7) of 0 is generated.

The address discriminating section 16 separates the odd address and the even address of the image memory 6 from each other as shown in FIGS.
As shown in (8) in any of (6) and (6), a signal whose output level at the H level and L level is opposite (opposite phase) between the case of an odd address and the case of an even address is determined by setting the least significant bit of the horizontal line counter to And output. This address discrimination signal and the frame discrimination signal from the frame discrimination unit 18 are EX
An OR circuit 19 for performing an exclusive OR operation, and further performing an OR operation on the signal after the operation and the overtaking inverted signal from the overtaking inverted signal generation unit 14 to enable / disable the write operation. Of the input enable signal (IE). This signal is shown at (10) in FIGS. The input enable signal (IE) is enabled when it is at H level, and is disabled when it is at L level.

The digital image data Dg3 from the multiplexer 4 is used only when the write enable signal (WE) enables the write address pointer and the input enable signal (IE) sets the image memory 6 to the write enable state. Image memory 6
Is written to. That is, the write enable signal (W
While E) is enabled (H level)
When the input enable signal (IE) becomes enabled (H level), that is, (1) in FIGS.
When the write control signal shown in 1) becomes H level, the digital image data Dg3 from the multiplexer 4 is input to the image memory 6 and written. (12) of FIG. 5 to FIG. 16 show the digital image data Dg3 from the multiplexer 4. Further, (13) in FIG. 5 and (1) in FIG.
3), (13) in FIG. 9, (13) in FIG. 11, (13) in FIG. 13, and (13) in FIG. 15 show image data input to the image memory 6.

As described above, the digital image data Dg3 from the multiplexer 4 is in a state where the data of the odd-numbered lines and the data of the even-numbered lines are partly arranged alternately. When the PC is an odd frame, when the PC is an even frame,
The data is written into the image memory 6 differently from the case of the overtaking frame, and is divided into the data of the odd-numbered lines and the data of the even-numbered lines. Different modes of the write control are shown in FIGS. 5 to 16.

FIG. 5 shows an operation in an odd line in one odd frame other than the overtaking frame (this is referred to as an odd frame). In this case, the overtaking determination signal in (9) is at the L level and the address determination signal in (8) is a timing for specifying an odd address.
The input enable signal (IE) of (10) inverts the H level and the L level in synchronization with the timing,
Since the write enable signal (WE) of (4) becomes H level and the write control signal of (11) inverts H level and L level in synchronization with the input enable signal (IE) only during the H level, Only the data of the odd lines in the digital image data Dg3 of (12) is (1)
The data is selected and written to the odd addresses of the image memory 6 as shown in 3).

FIG. 6 shows the operation of an odd-numbered frame in an even-numbered line. In this case, since the write enable signal (WE) is at the L level, writing to the image memory 6 is not performed.

FIG. 7 shows the operation of an odd-numbered line of one even-numbered frame other than the overtaking frame. In this case, the overtaking determination signal is at the L level, and the address determination signal is a timing for specifying an even address.
The input enable signal (IE) inverts the H level and the L level in synchronization with the timing, the write enable signal (WE) changes to the H level, and only during the H level does the write control signal change the input enable signal (I
In order to invert H level and L level in synchronization with E),
Only the data of the even-numbered lines in the digital image data Dg3 are selected and written to the even-numbered addresses of the image memory 6 as shown in (13).

FIG. 8 shows the operation of an even-numbered frame in an even-numbered line. In this case, since the write enable signal (WE) is at the L level, writing to the image memory 6 is not performed.

FIG. 9 shows the operation of the overtaking frame in the odd-numbered line. In this case, the overtaking determination signal is at the H level, the input enable signal (IE) is maintained at the H level, and the write control signal is also maintained at the H level while the write enable signal (WE) is at the H level. , Both the odd line data and the even line data of the digital image data Dg3 are stored in the image memory 6.
Are written to the respective odd and even addresses.

FIG. 10 shows the operation at the even-numbered line of the overtaking frame. In this case, the write enable signal (W
Since E) is at the L level, writing to the image memory 6 is not performed.

FIG. 11 shows the operation of the odd-numbered frame after the overtaking frame in the odd-numbered line. Since the overtaking inversion signal of (6) is inverted each time the overtaking frame ends as described above, after the overtaking frame, the odd-numbered frames are written to the image memory 6. The write operation is the same as in FIG.

FIG. 12 shows the operation of the odd-numbered frame on the even-numbered line, FIG. 13 shows the operation of the even-numbered frame after the overtaking frame on the odd-numbered line, and FIG. 14 shows the operation of the even-numbered frame on the even-numbered line. FIG. 15 shows the operation of the next overtaking frame on an odd-numbered line, and FIG. 16 shows the operation of the same overtaking frame on an even-numbered line.

Therefore, in the odd frame of the PC, only the image data of the odd line, in the even frame of the PC, only the image data of the even line, and in the overtaking frame, the image data of both the odd line and the even line (the image data of one PC frame). ) Is written into the odd and even addresses of the image memory 6. The order of odd frames is “odd”, even frames are “even”, overtaking frames are “over”, odd frames are “odd”, even frames are “even”, and overtaking frames are “over”. Even, odd, even,
······ Odd, even, additional, odd, even, odd, even, ..., odd, even, additional, odd, even, odd, even, ...

FIG. 3 shows an example of the configuration of the memory read system controller 52 of the memory controller 6. The memory read system control unit 52 includes an effective screen area determination unit 21, a field determination unit 22, an address determination unit 23, and an EX-OR circuit 24. The memory read system control unit 52 includes:
The read clock (RCLK) is input from the timing generator 8. As described above, since the write clock (WCLK) for writing to the image memory 6 is twice as large as the A / D conversion clock, the read clock (RCLK) is also A / D converted to match this. The clock is twice the clock. 17 and 18 show the operation of the memory read system controller 52. FIG. 17 shows the case of the odd field of the TV receiver, and FIG. 18 shows the case of the even field.

The effective screen area discriminating section 21 decodes the values of a horizontal write counter and a vertical write counter (a counter for two fields of a TV receiver) at the beginning and end of the effective screen area, and uses a flip-flop and an AND circuit. Then, as shown in FIG. 17 and FIG. 18 (2), an effective screen area signal is output which is H level in the effective screen area and L level in other cases. This effective screen area signal is used as a read enable signal (RE) for enabling / disabling the read address pointer. When the signal is at the H level, the read address pointer is incremented.
Stops at L level.

The field inversion section 22 outputs a field inversion signal that is inverted by an H pulse output for each field. The field inversion signal goes low in the odd field as shown in FIG. 17 (3) and goes high in the even field as shown in FIG. 18 (3).

The address discriminating section 23 uses the least significant bit of the horizontal read counter to obtain (4) in FIG. 17 and FIG.
As shown in (1), an address discrimination signal is output at H level for odd addresses and at L level for even addresses. The address discrimination signal and the field inversion signal are EX-ORed.
The exclusive OR is performed by the circuit 24 so that the image memory 6
An output enable signal (OE) for enabling / disabling the data output terminal is generated. This output enable signal (OE) is shown in FIG. 17 and FIG. 18 (5). When this signal is at H level, the data output terminal of the image memory 6 is enabled, and when it is at L level, it is disabled. This data output terminal is enabled and the read enable signal (R
When E) enables the read address pointer, the image data is read from the image memory 6. (6) of FIG. 17 and FIG. 18 show the read control signal.

The read control signal remains at the L level when the effective screen area signal is at the L level, and the H level and the L level are inverted only while the effective screen area signal is at the H level.
Moreover, the phases of the odd number field and the even field of the TV receiver are opposite in phase. Therefore, in the odd field of the TV receiver, the image data of the odd frame of the PC is read out as shown in (8) of FIG. 17, and in the even field of the TV receiver, the data of the PC is read as shown in (8) of FIG. The image data of the even frame is read.

[0038]

As described above, according to the present invention, the odd-numbered line image data and the even-numbered line image data are alternately multiplexed with a clock that is twice the A / D conversion clock.
Only the image data of the odd line in the odd frame, only the image data of the even line in the even frame, and the image data of both the odd line and the even line in the overtaking frame are written in the image memory. As a result, cost reduction and circuit scale reduction can be achieved. Further, even if the memory capacity is reduced to half, the image quality is not reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a system configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a memory write system control unit of the memory control unit in FIG. 1;

FIG. 3 is a block diagram showing a configuration example of a memory read system control unit.

FIG. 4 is a timing chart showing an operation of multiplexing digital image data obtained by A / D conversion of an analog image from a personal computer in the system of FIG. 1;

FIG. 5 is a timing chart showing an operation in an odd line of an odd frame before reading from an image memory overtakes writing in the system.

FIG. 6 is a timing chart showing the operation of the above even line.

FIG. 7 is a timing chart showing an operation of an even-numbered frame in an odd-numbered line before passing.

FIG. 8 is a timing chart showing the operation of the above even line.

FIG. 9 is a timing chart showing an operation of an overtaking frame in an odd line.

FIG. 10 is a timing chart showing the operation of the above even line.

FIG. 11 is a timing chart showing an operation of an odd-numbered frame in an odd-numbered line after passing.

FIG. 12 is a timing chart showing an operation of the above even line.

FIG. 13 is a timing chart showing an operation of an even-numbered frame in an odd-numbered line after passing.

FIG. 14 is a timing chart showing the operation of the above even line.

FIG. 15 is a timing chart showing an operation of the next overtaking frame at an odd-numbered line.

FIG. 16 is a timing chart showing the operation of the above even line.

FIG. 17 is a diagram showing an example in which image data written in an image memory is displayed on a TV
9 is a timing chart showing an operation of reading out an image in an odd field of the receiver.

FIG. 18 is a timing chart showing an operation of reading data in an even-numbered field.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 2 Vertical filter 3 1 line delay circuit 4 Multiplexer 5 Memory control unit 6 Image memory 7 D / A converter 8 Timing generation unit 10 Effective screen area discrimination unit 11 Line discrimination unit 12 AND circuit 13 Overtaking discrimination unit 14 Overtaking inverted signal generating unit 15 Frame inverting unit 16 Address determining unit 17 EX-OR circuit 18 Frame determining unit 19 EX-OR circuit 20 EX-OR circuit 21 Effective screen area determining unit 22 Field determining unit 23 Address determining unit 24 EX- OR circuit 51 Memory write system controller 52 Memory read system controller

Claims (4)

(57) [Claims] 1. An analog image signal of a frame is converted into digital image data by A / D conversion means, written into an image memory at a fixed writing cycle, and read out from the image memory at a predetermined reading cycle different from the writing cycle. /
In an analog image signal conversion method for converting again to an analog image signal by A conversion means, the digital image data Dg1 of the current line converted by the A / D conversion means and the digital image data Dg2 of the previous line delayed by one line Is the A / D conversion clock 2
Multiplexing so that Dg1 and Dg2 alternate with a double clock; determining beforehand the overtaking time when the read cycle overtakes the write cycle; and in the frame corresponding to the overtaking time, An analog image signal conversion method comprising writing both Dg1 and Dg2 of the multiplexed digital image data Dg3 to the image memory, and selecting and writing Dg1 and Dg2 in other frames. 2. An analog image signal of a frame is converted into digital image data by A / D conversion means, written into an image memory at a fixed writing cycle, and read out from the image memory at a predetermined reading cycle different from the writing cycle to obtain a digital image signal. /
In an analog image signal conversion method for converting again to an analog image signal by A conversion means, the digital image data Dg1 of the current line converted by the A / D conversion means and the digital image data Dg2 of the previous line delayed by one line are converted. Multiplexing so that Dg1 and Dg2 alternate with a clock that is twice the clock of the A / D conversion; determining beforehand the overtaking time at which the read cycle overtakes the write cycle; In the frame corresponding to the time point, both the Dg1 and Dg2 are written to the image memory for the multiplexed digital image data Dg3, and for the other odd-numbered frames, the odd-numbered lines of Dg1 and Dg2 are written and the even-numbered frames are written. The frame includes a step of writing even lines. Analog image signal conversion method. 3. An analog image signal of a frame is converted into digital image data by A / D conversion means, written into an image memory at a fixed write cycle, and read out from the image memory at a predetermined read cycle different from the write cycle. /
An analog image signal conversion device that converts the digital image data converted by the A / D conversion unit by one line in an analog image signal conversion device that converts the analog image signal into an analog image signal again by the A conversion unit; The digital image data Dg1 of the current line and the digital image data Dg2 of the previous line delayed by one line are multiplexed so that Dg1 and Dg2 alternate with a clock twice the A / D conversion clock. A multiplexer; an overtaking judging unit for judging whether or not the read cycle is an overtaking frame that will overtake the writing cycle; and Write to the image memory, and in other frames, An analog image signal conversion device, comprising: a writing control means for selecting and writing 1 and Dg2. 4. An analog image signal of a frame is converted into digital image data by A / D conversion means, written into an image memory at a fixed writing cycle, and read out from the image memory at a predetermined reading cycle different from the writing cycle to obtain a D signal. /
An analog image signal conversion device that converts the digital image data converted by the A / D conversion unit by one line in an analog image signal conversion device that converts the analog image signal into an analog image signal again by the A conversion unit; The digital image data Dg1 of the current line and the digital image data Dg2 of the previous line delayed by one line are multiplexed so that Dg1 and Dg2 alternate with a clock twice the A / D conversion clock. A multiplexer; an overtaking judging unit for judging an overtaking frame in which the read cycle overtakes the writing cycle; a frame judging unit for judging whether the current frame is an odd-numbered frame or an even-numbered frame; , For the multiplexed digital image data Dg3, g1 and Dg2
And a writing control means for writing the odd lines of Dg1 and Dg2 for the odd frames and writing the even lines for the even frames in the other odd frames. Signal converter.