JPH07276697A - Video clock forming circuit and horizontal synchronizing signal forming circuit of electrophotographic printer using laser beam - Google Patents

Abstract

PURPOSE:To form an image of high quality by forming a video clock performing the processing control of respective pixel data in synchrous relation to the scanning of laser beam. CONSTITUTION:A frequency clock CLKin equal to a video clock is formed by a reference frequency generation circuit 1 and differentiated by a differentiation circuit to obtain a differential pulse. Saw-tooth waves N1, N2 synchronous to the positive and negative pulses of the differential pulse are formed by a saw-tooth wave generation circuit 3. These saw-tooth waves N1, N2 are held at the rising of a beam detection signal BD by condensers 53a, 53b and the voltage corresponding to the phase difference between BD and CLKin is obtained in the outputs of operational amplifiers 54a, 54b. This voltage is compared with the saw-tooth wave N1 as the reference levels of comparators 61a, 61b and the comparison output and BD are subjected to AND operation by an AND gate 62 to obtain the video clock synchronous to BD.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video clock generation circuit and a horizontal synchronization signal generation circuit for an electrophotographic printer using a laser beam, and more particularly to a data processing operation for each pixel in synchronization with scanning of the laser beam. The present invention relates to a video clock generation circuit that generates a video clock to control. The present invention also relates to a horizontal synchronization signal generation circuit that generates a horizontal synchronization signal that synchronizes the scanning of a laser beam and the processing of image data.

[0002]

2. Description of the Related Art In an electrophotographic printer using a laser beam, it is necessary that the scanning of the photosensitive member by the laser beam and the modulation of the laser beam based on image data are synchronized. Therefore, for example, a laser beam for scanning the photoconductor is detected at a predetermined position, a beam detection signal corresponding to the scanning timing of the photoconductor by the laser beam is generated, and a horizontal synchronization signal is generated in synchronization with this beam detection signal. It

Since the horizontal synchronizing signal is synchronized with the scanning of the laser beam, the laser beam is subjected to modulation corresponding to the image data according to the video clock inside the apparatus based on the horizontal synchronizing signal. The desired image can be obtained.

This video clock is a clock that defines the processing operation corresponding to the image data of each pixel. For example, as shown in Japanese Patent Laid-Open No. 4-282954, there is a synchronization deviation between the beam detection signal and the video clock. To minimize it, it is generated by a circuit using the delay circuit shown in FIG.

In FIG. 5, a crystal oscillator (not shown) generates a basic clock CLKin having a frequency equal to that of the video clock VCLK. This basic clock CLKin has a plurality of stages of delay elements D connected in series.
It is input to the first stage delay element D1 of 1 to D8.

Each of the delay elements D1 to D8 is a circuit for shifting each phase of the input clock by 45 degrees, and has a basic clock CL.
Kin and the outputs of the delay elements D1 to D8 are the internal clock C.
LK0 to CLK8 are input to the clock selector S1 which is a clock selection means.

The clock selector S1 selectively derives, as the video clock VCLK, one of the internal clocks CLK0 to CLK8 whose phase difference with respect to the beam detection signal BD is closest to the predetermined phase difference. By doing so, it is possible to make the phase shift of the beam detection signal BD and the video clock VCLK less than 45 degrees.

[0008]

In the conventional circuit configuration shown in FIG. 5, a beam detection signal BD and a video clock VCL are used.
Since the maximum phase shift from K is 45 degrees, it is necessary to increase the number of stages of delay elements and reduce the synchronization shift in order to obtain a better recorded image. Therefore, the circuit scale increases, which causes a cost increase.

Further, since the video clock generally differs depending on the device specifications, it is necessary to design the delay element individually for each device specification in the circuit configuration of FIG. 5, and thus the versatility is lacking.

Further, it is necessary to generate a horizontal synchronizing signal in synchronization with the beam detection signal, but in addition to that, a horizontal synchronizing signal delayed by a desired time from the beam detection signal is required depending on the apparatus specifications. However, even in this case, there is a drawback that it is necessary to design the delay element according to each specification.

It is an object of the present invention to provide a versatile video clock generation circuit capable of generating a video clock that is phase-locked to a beam detection signal with high accuracy without increasing the circuit scale.

Another object of the present invention is to provide a horizontal synchronizing signal generating circuit which can easily generate a horizontal synchronizing signal having a desired delay time with respect to a beam detection signal.

[0013]

According to the present invention, there is provided a video clock generation circuit for generating a video clock for controlling processing of each pixel data in an electrophotographic printer using a laser beam, the clock having a reference frequency. A means for generating a signal, a sawtooth wave signal generating means for generating a sawtooth wave signal synchronized with the clock signal of the reference frequency,
Means for generating a beam detection signal corresponding to the scanning of the laser beam, and phase difference detection for detecting a phase difference between the laser beam detection signal and the clock signal of the reference frequency and generating a voltage corresponding to the phase difference Means for comparing the level of the voltage with the sawtooth wave signal and comparing means for generating the video clock based on a signal having a pulse width according to the comparison result. Is obtained.

According to the present invention, the video clock generated by the above video clock generation circuit is counted in synchronization with the beam detection signal, and when the respective count values are reached, the start and end of the horizontal synchronizing signal are started. A horizontal synchronizing signal generation circuit having a counting means for determining each timing is obtained.

[0015]

A sawtooth wave signal synchronized with the reference frequency clock is generated, a voltage is generated according to the phase difference between the reference frequency clock and the beam detection signal, and the level of this voltage and the sawtooth wave signal is compared. By generating the video clock based on the signal having the pulse width corresponding to the comparison result, it is possible to generate the video clock that is highly accurately phase-synchronized with the beam detection signal.

Further, a horizontal synchronizing signal having a desired delay time can be obtained from the beam detection signal by counting the video clock, which is highly accurately phase-locked with the beam detection signal, by the counting circuit until it reaches a predetermined count value. It will be possible.

[0017]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The reference frequency generation circuit 1 is composed of a crystal oscillation circuit and a waveform shaping circuit, and generates a reference clock CLKin having the same frequency as a target video clock.

This clock CLKin is input to the differentiating circuit 2 to generate a positive impulse signal corresponding to the rising timing of this clock and a negative impulse signal corresponding to the falling timing thereof. The impulse signal which is the differential pulse is input to the sawtooth wave generation circuit 3.

The sawtooth wave generation circuit 3 is composed of a bootstrap circuit mirror integration circuit, and two types of sawtooth wave (sawtooth wave) signals N1 and N2 are triggered by positive and negative impulses from the differentiating circuit 2, respectively. Is generated. The two types of sawtooth wave signals N1 and N2 are input to the phase difference detection circuit 5.

The phase difference detection circuit 5 has two systems. Two types of sawtooth wave signals N1 and N2 are applied to the analog log switch 51.
It is input to the sample hold circuit including resistors 52a and 52b, capacitors 53a and 53b, and voltage followers (op amps) 54a and 54b via a and 51b, respectively.

The analog switches 51a and 51b are turned on for the effective period (effective at a low level) of the beam detection signal BD generated from the beam detection circuit 4, and the beam detection signal BD is an inverter including a transistor 55 and a resistor 56. The analog switches 51a and 51b are controlled to be turned on and off via the.

FIG. 2 shows the operation waveforms of each part of the embodiment of FIG. 1. The analog switches 51a and 51b are turned on during the effective period (low level period) of the beam detection signal, and the sawtooth wave signals N1 and N2 are turned on. Is supplied to the sample hold circuit, so that at the end timing (transition timing from low to high) of the effective period of the beam detection signal BD,
Electric charges corresponding to the voltage levels of the sawtooth wave signals N1 and N2 at that timing are accumulated and held in the capacitors 53a and 53b.

Therefore, these hold voltages have a level corresponding to the phase difference between the beam detection signal BD and the clock CLKin, and these phase difference voltages (the operational amplifier 5
The outputs 4a and 54b are reference voltages of the comparators 61a and 61b of the comparison circuit 6 at the next stage.

One of the two sawtooth wave signals N1 from the sawtooth wave generating circuit 3 is supplied to the comparison inputs of these comparators 61a and 61b. An AND circuit 62 performs a logical product operation between the outputs of the comparators 61a and 61b and the beam detection signal BD, and a video clock VCLK synchronized with the rising timing of the beam detection signal BD is generated at the logical product output. Will be done.

The phase difference detection circuit 5 and the comparison circuit 6 are 2
Although a system is provided, this is provided to determine the target pulse width (duty) of the video clock VCLK, and the beam detection signal BD is used as one input of the AND operation to detect the beam. Video clock VCL synchronized with the rising timing of signal BD after this
Because K is necessary.

Further, although N1 of the two types of sawtooth wave signals N1 and N2 is used as the comparison input in the comparison circuit 6, N2 may be used.

Although it is necessary to generate the horizontal synchronizing signal HSYNC using the video clock VCLK obtained by the circuit of FIG. 1, FIG. 3 is a circuit diagram showing an embodiment of the HSYNC generating circuit, and FIG. FIG. 4 is an operation waveform diagram of each part of the circuit of FIG.

As shown in FIG. 3, the video clock VCLK synchronized with the beam detection signal BD is input to the two preset counters 71 and 72. These counters 7
Reference numerals 1 and 72 are counters whose preset initial values can be preset from the outside. These initial values are set to the video clock VCL.
It is assumed that the counter is a counter that generates a low level at the Q output (a high level at the inverted Q output) when it counts down for each K input and becomes "0".

The outputs of these counters are derived through the OR gate 73 so that the low-level effective horizontal synchronizing signal HSYNC can be generated.

It is assumed that the counter 71 is set to "2" as a preset value and the counter 72 is set to "4" as a preset value. The counter reset is released in synchronization with the rising timing of the beam detection signal BD, and the counters 71 and 72 start counting down each time the video clock VCLK is input. Since the Q output is derived from the counter 71 and the inverted Q output is derived from the counter 72, as shown in FIG.
Output HSYNC is a signal delayed from the rising timing of the beam detection signal BD by a period corresponding to a predetermined number of the video clock VCLK.

By selecting a preset value for each of the counters 71 and 72, the beam detection signal BD of the horizontal synchronizing signal HSYN is selected.
The delay time with respect to can be set arbitrarily.

[0033]

As described above, according to the present invention, the phase difference between the beam detection signal and the reference frequency signal is detected, and the reference frequency signal is delayed by the phase difference to generate the video clock. Therefore, the deviation of the synchronization between the beam detection signal and the video clock is at most about the delay of the circuit components and does not vary, and the circuit components do not depend on the frequency of the video clock, so the dependence on the device specifications is low. Since it can be integrated and mass-produced, it can be realized at a low price, and the integration can shorten the delay time of the circuit constituent elements, resulting in higher accuracy. In this way, a video clock synchronized with laser beam scanning with high accuracy can be obtained by a versatile low-cost circuit.

The video clock eliminates variations in the temporal relationship between the beam detection signal and the video clock among a plurality of scanning lines formed by the laser beam, and eliminates image shift between the plurality of scanning lines. As a result, it is possible to form a high quality image.

Further, since the horizontal synchronizing signal is generated by counting the video clock accurately synchronized with the beam detecting signal at the timing based on the beam detecting signal, the horizontal synchronizing signal synchronized with the beam detecting signal with high precision. There is also an effect that is obtained. With this horizontal sync signal. Since there is no variation in the temporal relationship between the beam detection signal and the horizontal synchronization signal among the plurality of scanning lines formed by the laser beam, there is no image shift between the plurality of scanning lines, and high quality image formation is possible. .

Further, since the horizontal synchronizing signal is generated by counting the video clocks, a desired delay time can be obtained by selecting this count value, so that the beam detection signal has a desired delay time. The horizontal synchronizing signal can be easily obtained, and the versatility is enhanced.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a video clock generation circuit of the present invention.

FIG. 2 is a signal waveform diagram of each part showing the operation of the embodiment of FIG.

FIG. 3 is a diagram showing an embodiment of a horizontal synchronization signal generation circuit of the present invention.

FIG. 4 is a signal waveform diagram of each part showing the operation of the circuit of FIG.

FIG. 5 is a block diagram showing an example of a conventional video clock generation circuit.

[Explanation of symbols]

 1 Reference Frequency Generation Circuit 2 Differentiation Circuit 3 Sawtooth Wave Generation Circuit 4 Beam Detection Circuit 5 Phase Difference Detection Circuit 6 Comparison Circuit 71,72 Comparator 73 OR Gate

Claims (4)

[Claims] 1. A video clock generation circuit for generating a video clock for controlling processing of each pixel data in an electrophotographic printer using a laser beam, the means for generating a clock signal of a reference frequency, and the reference frequency. Sawtooth wave signal generating means for generating a sawtooth wave signal synchronized with the clock signal, means for generating a beam detection signal corresponding to the scanning of the laser beam, the laser beam detection signal and the clock signal of the reference frequency Phase difference detecting means for detecting a phase difference between the voltage and the phase difference and generating a voltage corresponding to the phase difference and a signal having a pulse width corresponding to the comparison result by comparing the level of this voltage and the sawtooth wave signal. And a comparison means for generating the video clock. 2. The phase difference detecting means includes sample and hold means for sampling and holding the voltage level of the sawtooth wave signal at the end timing of the effective period of the beam detection signal, and the comparing means has the sample and hold means. 2. The video clock generation circuit according to claim 1, further comprising level comparison means for comparing an output level with a level of the sawtooth wave signal. 3. The sawtooth wave signal generating means, means for generating first and second sawtooth wave signals which are respectively synchronized with the rising and falling edges of the clock signal of the reference frequency, and the phase difference detecting means. Has first and second sample and hold means for sampling and holding the voltage levels of the first and second sawtooth wave signals, respectively, and the comparing means is provided for the first and second sample and hold means. Logic of first and second comparators comparing each output level with the level of the first sawtooth wave signal, comparison results of the first and second comparators, and further the beam detection signal. 3. A video clock generation circuit according to claim 2, further comprising a calculation means for performing a calculation and deriving a result of the calculation as the video clock. 4. A video clock generated by the video clock generation circuit according to claim 1,
An electrophotographic method using a laser beam, which has counting means for respectively counting in synchronization with the beam detection signal and determining the start and end timings of the horizontal synchronizing signal when the respective count values are reached. Horizontal sync signal generation circuit for printer.