JP2775813B2 - Video analog / digital converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital (hereinafter abbreviated as AD) converter used in various television transmission devices, and particularly to a video signal, that is, a so-called analog composite video signal. The present invention relates to a video A / D converter having a position adjustment function of converting a received digital video signal into a digital video signal, controlling the writing and reading of the digital video signal to and from a memory circuit, and outputting the digital video signal as a phase-adjusted digital video signal.

[Conventional technology]

Conventionally, there is an AD converter of this type shown in FIG. In FIG. 2, reference numeral 1 denotes a clamp circuit to which an analog composite video signal a is supplied via an input terminal 11. The clamp circuit 1 clamps the video signal a to a constant voltage and then converts an output signal to an AD conversion circuit. Feed to 2. Similarly, the composite video signal a
, Which separates only the synchronization portion from the video signal a and supplies the synchronization signal f to the detection circuit 10. Also, the reference synchronizing signal b from the input terminal 12 is a detection circuit.
Supplied to 10. As a result, the detection circuit 10 outputs the synchronization signal f from the synchronization separation circuit 4 as it is when it is normal, but switches to the reference synchronization signal b supplied from the input terminal 12 and outputs it when there is no signal. The output signal is supplied to a burst control oscillation (hereinafter, abbreviated as BCO) circuit 6 to which a reference subcarrier signal c is supplied from an input terminal 13. Further, an output signal from the clamp circuit 1 is also supplied to the BCO circuit 6. Therefore, the BCO circuit 6
Then, if the output signal from the clamp circuit 1 is normal, a clock signal g synchronized with this signal is generated. If the output signal from the clamp circuit 1 is a monochrome signal, the clock signal g is converted from the reference subcarrier signal c. generate. When the clock signal g is supplied to the AD converter 2 and the write address generator 7, the AD converter 2
Converts the analog composite video signal clamped by the clamp circuit 1 with the clock signal g into a digital video signal, and supplies the output signal to the memory circuit 3.
The write address circuit 8 generates a write address signal corresponding to the phase of the input signal, and supplies the signal to the memory circuit 3 as a write signal. On the other hand, input terminal 14
Clock signal e from read address generating circuit 8
The read address generation circuit 8 generates a read address signal corresponding to the phase of the output signal, and supplies the signal to the memory circuit 3 as a read signal. As a result, the memory circuit 3 delays the input video signal a by the write and read address control signals, and supplies the digital video signal d to the output terminal 15 as an output signal.

[Problems to be solved by the invention]

In such a conventional AD converter, the input analog composite video signal a is output as a digital composite video signal d whose phase has been adjusted. However, the input signal changes in phase and is out of the range in which the memory circuit 3 can adjust the phase. In this case, since the output signal is output at a fixed phase, there is a problem that the output signal becomes an abnormal synchronization output signal.

[Means for solving the problem]

In order to solve such a problem, the present invention provides a digital video signal whose phase has been adjusted by receiving an analog video signal, converting the digital video signal into a digital video signal, and writing and reading the digital video signal to and from a memory circuit. In the video A / D conversion device that outputs as, the input analog video signal is clamped and separated in synchronization, the synchronization signal and the reference synchronization signal are switched and selected, and both signals are compared to determine whether the signal is within the phase adjustment range of the memory circuit. A comparison detection circuit that determines whether or not the signal is out of the range, and outputs the information as asynchronous information; and a synchronization signal or reference synchronization signal selected by the comparison detection circuit, a clamped input analog video signal, and a reference subcarrier signal. A BCO circuit for generating a clock signal to be sampled, and an input based on a clock signal generated from the BCO circuit. An AD conversion circuit for outputting to the memory circuit the analog video signal to digital conversion, the received asynchronous data output from the comparison detection circuit which selects a reference clock signal for synchronous, in the case of asynchronous said
A clock switch for selecting a clock signal from the BCO circuit, a write address generation circuit for generating a write address signal based on the clock signal generated from the BCO circuit, and controlling the writing of the memory circuit by the write address signal; A read address generating circuit is provided for generating a read address signal in accordance with a reference clock signal or a clock signal selected by a clock switch, and controlling reading of the memory circuit in accordance with the read address signal.

[Action]

Therefore, in the present invention, the phase of the digital video signal is automatically adjusted according to the phase condition of the input video signal by controlling the switching of the clock switch based on the asynchronous information output from the comparison detection circuit. It becomes possible.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a video A / D converter according to the present invention. This embodiment differs from the prior art shown in FIG. 2 in that the synchronization signal f of the synchronization separation circuit 4 and the reference synchronization signal b are switched and selected.
By comparing f and b, it is determined whether the phase is within the range of the phase adjustment by the memory circuit 3, and if it is out of the range, the comparison detection circuit 5 outputs as asynchronous information h, and the asynchronous information output from the comparison detection circuit 5 a clock switch 9 for switching between the clock signal g from the BCO circuit 6 and the reference clock signal e based on the reference clock signal h. The reference clock signal e is used in the case of synchronization, and the clock signal g is used in the case of asynchronous information. That is, the selected address is supplied to the read address generating circuit 8. The same reference numerals in the drawings indicate the same or corresponding parts.

Next, the operation of the configuration of the above embodiment will be described. Here, when the analog composite video signal a is supplied to the clamp circuit 1 and the synchronization separation circuit 2, the clamp circuit 1 clamps the video signal a to a constant voltage and then outputs the output signal.
It is supplied to the AD conversion circuit 2. In the synchronization separation circuit 4,
Only the synchronizing portion is separated from the input composite video signal a, and the synchronizing signal f is supplied to the comparison detection circuit 5. On the other hand, the reference synchronization signal “b” supplied from the input terminal 12 is supplied to the comparison detection circuit 5. Thereby, the comparison detection circuit 5 outputs the synchronization signal f from the synchronization separation circuit 4 as it is, if it exists, but switches to the reference synchronization signal b supplied from the input terminal 12 when there is no signal, and outputs it. , BCO circuit 6. Further, in the comparison detection circuit 5, when there is the synchronization signal f from the synchronization separation circuit 4, it is compared with the reference synchronization signal b to judge whether or not the phase is within the range of the phase adjustment by the memory circuit 3. It is output as information h and supplied to the clock switch 9.

On the other hand, the reference subcarrier signal c supplied from the input terminal 13 is supplied to the BCO circuit 6, and the output signal from the clamp circuit 1 is also supplied to the BCO circuit 6. Therefore, the BCO circuit 6 generates a clock signal g in synchronization with the output signal from the clamp circuit 1 when the output signal from the clamp circuit 1 is normal. However, when the output signal from the clamp circuit 1 is a monochrome signal, the reference subcarrier signal is output. A clock signal g is generated from c. The clock signal g is supplied to the AD conversion circuit 2, the write address generation circuit 7, and the clock switch 9. Thus, the output signal digitally converted by the AD conversion circuit 2 is supplied to the memory circuit 3. The write address circuit 7 generates a write address signal corresponding to the phase of the input video signal a and supplies the signal to the memory circuit 2 as a write signal. Also, input terminal 14
Is supplied to the clock switch 9, and based on the asynchronous information h from the comparison detection circuit 5,
Reference clock signal e for synchronous, BC for asynchronous
The clock signal g from the O circuit 6 is switched and output. When this output signal is supplied to the read address generation circuit 8, the read address generation circuit 8
A read address signal corresponding to the phase of the output signal d is generated, and the signal is supplied to the memory circuit 3 as a read signal. As a result, the memory circuit 3 processes the input signal with delay or through by the write and read address control signals, and supplies the digital video signal d to the output terminal 15 as an output signal.

As described above, according to the present embodiment, when the input video signal a is out of the range of the phase adjustment by the memory circuit 3, the write address and the read address of the memory circuit 3 are made the same so that the output is performed without the phase adjustment. This has the advantage of eliminating synchronization errors.

In the above-described embodiment, the phase adjustment method is configured by the memory circuit, but may be configured by equivalent hardware other than the memory.

〔The invention's effect〕

As described above, according to the present invention, the reference clock signal supplied to the read address generation circuit and the BCO based on the asynchronous information output from the comparison detection circuit in the video A / D converter.
By switching and controlling the clock signal from the circuit, when the input video signal is out of the range of the phase adjustment by the memory circuit, the write address and the read address of the memory circuit can be made the same. As a result, since a digital video signal can be output without phase adjustment, it is possible to eliminate the synchronization abnormality as in the related art, and the practical effect is extremely large.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional video AD converter. 1 ... clamp circuit, 2 ... AD conversion circuit, 3 ... memory circuit, 4 ... sync separation circuit, 5 ... comparison detection circuit, 6 ...
... a burst control oscillation (BCO) circuit, 7 ... a write address generation circuit, 8 ... a read address generation circuit, 9 ... a clock switch.

Claims (1)

(57) [Claims] 1. A video analog-to-digital converter for receiving an analog video signal, converting the digital video signal into a digital video signal, and writing and reading the digital video signal to and from a memory circuit to output a phase-adjusted digital video signal. In the above, the input analog video signal is clamped and synchronously separated, the synchronous signal and the reference synchronous signal are switched and selected, and both signals are compared to determine whether or not the phase is within the phase adjustment range by the memory circuit. Is outside the range, a comparison detection circuit that outputs as asynchronous information, and a clock signal to be sampled based on the synchronization signal or reference synchronization signal selected by the comparison detection circuit, the clamped input analog video signal, and the reference subcarrier signal. The burst control oscillation circuit generated, and the clock generated from the burst control oscillation circuit. AD of the input analog video signal to digital conversion by click signal output to the memory circuit
A conversion circuit, and a clock switch which receives the asynchronous information output from the comparison detection circuit, selects a reference clock signal when the information is synchronous, and selects a clock signal from the burst control oscillation circuit when the information is asynchronous. A write address generation circuit for generating a write address signal in response to a clock signal generated from the burst control oscillation circuit and controlling the writing of the memory circuit in accordance with the write address signal;
A read address generating circuit for generating a read address signal based on a reference clock signal or a clock signal selected by the clock switch and reading and controlling the memory circuit in accordance with the read address signal, according to a phase condition of an input video signal; A video analog-to-digital converter, wherein the phase of a digital video signal is automatically adjusted.