JPH05101531A - Automatic digital phase controller - Google Patents

Abstract

PURPOSE:To extract a clock having no phase difference with the twice accuracy of conventionality by detecting a signal having the least phase difference with a reference signal from plural signals having a different delay amount in gates and area discriminating. CONSTITUTION:By buffers 1-4, an input signal is delayed in gate delays and plural delay signals are outputted. From these plural delay signals, the delay signals having a near phase to the reference signal and in front and behind of the reference signal are picked up by a D type flip-flop 5, an encoder 6 and a multiplexer 7. Next, By the buffer 8, the buffer 9, an exclusive OR 10 and a D type flip-flop 11, the delay signals extract to the reference signal and in front and behind of flue reference signal and the output having the near phase is detected and area discriminated. Then, by a selector 12, the signals having the least phase difference to the reference signal is picked up. Thus, a write clock to the memory of TBC is controlled to the signal having no phase difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital automatic phase control device having a function of automatically extracting a signal phase-synchronized with a reference signal.

[0002]

2. Description of the Related Art Recently, digital automatic phase control devices have been
It is used for controlling the write clock to the memory of the time base collector (hereinafter referred to as TBC) circuit in order to correct the time base fluctuation that has occurred in the head and tape systems as the performance of TR etc. has improved. ing. Conventionally, this type of digital automatic phase control device controls in a gate delay unit, but in order to improve accuracy, it is necessary to reduce the delay amount of gate delay per gate and increase the number of stages. .. Hereinafter, the configuration and operation of the circuit configured as shown in FIG. 3 will be described with reference to the diagram showing the operation example of FIG. FIG. 3 is a block diagram showing the configuration of a conventional digital automatic phase control device. As components 31, 32, 33, 34 are buffers, which delay the input signal 38 in units of gate delay. 35 is a D-type flip-flop (hereinafter referred to as D-FF),
The signals delayed by the buffers 31, 32, 33 and 34 are latched by the reference signal 39. 36 is an encoder, D
-Detect the highest low level of FF35 output and output the binary code corresponding to it. A multiplexer 37 selects the output of the buffer 31, 32, 33, 34 according to the binary code of the output of the encoder 36.

Next, the operation of the circuit thus constructed will be described. The input signal 38 shown in FIG. 4 is delayed by the buffers 31, 32, 33, and 34 by four steps as shown by the waveforms 40, 41, 42, and 43 in FIG. The D-FF 35 latches the waveforms 40, 41, 42, 43 at the rising edge of the reference signal 39 to find the change point of the input signal 38 delayed by the buffers 31, 32, 33, 34. The encoder 36 detects the highest low level of the output waveforms 44, 45, 46, 47 of the D-FF 35 to output the corresponding binary codes 48, 49. By inputting these binary codes 48 and 49 into the multiplexer 37, the input signal 38 phase-locked with the reference signal 39 can be automatically extracted as the signal 50 in gate delay units.

[0004]

However, in the above-described conventional digital automatic phase control device, even when the phase of the gate delay output rising immediately before the rising edge of the reference signal is close to that of the reference signal, the output of the gate delay rising next is generated. Therefore, it is impossible to faithfully extract a signal that is actually phase-locked with the rising edge of the reference signal.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a highly accurate digital automatic phase control device for extracting the output of the gate delay having the closest phase to the rising edge of the reference signal.

[0006]

In order to achieve the above object, the digital automatic phase control device of the present invention comprises a delay means for outputting a plurality of delay signals obtained by delaying an input signal by different delay amounts in units of gate delay, Among the plurality of delay signals output from the delay means, a selection means for extracting two delay signals before and after which the phase is close to the rising edge of the reference signal and the area determination of the two delay signals are performed, and which delay signal is the reference It has a detection means for detecting whether it is close to the rising phase of the signal.

[0007]

In the digital automatic phase control device of the present invention having the above-mentioned structure, the two delay signals before and after the reference signal having a phase close to that of the reference signal are picked up by the selecting means from a plurality of gate units having different delay amounts. By detecting the signal having the smallest phase difference from the reference signal among the delayed signals by the detecting means, the signal having the phase closest to the phase of the reference signal can be extracted, so that the write clock to the memory of the TBC is changed. , The tape is synchronized with the temporal fluctuation generated in the head system, the video signal is written to the memory, and the read clock is a fixed clock to minimize the temporal fluctuation of the video signal. be able to.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of a digital automatic phase controller according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing the configuration of a digital automatic phase control device in one embodiment. 1, 2, 3, 4 are buffers as constituent elements, and delay means delays an input signal in units of gate delay and outputs a plurality of delayed signals. 5 is a D-FF, and buffers 1, 2,
The plurality of delayed signals delayed by 3 and 4 are latched. An encoder 6 detects the highest low level of the output of the D-FF 5 and outputs a binary code corresponding to it. Numeral 7 is a multiplexer, which receives the input signal and the buffer 1 according to the binary code of the output of the encoder 6.
A selection means is configured by selecting from a plurality of delayed signals of 2, 3, 4 outputs. A buffer 8 has a delay amount of the multiplexer 7. 9 is a buffer,
It has half the delay amount of buffers 1, 2, 3, and 4.
Reference numeral 10 is an exclusive OR (hereinafter referred to as XOR), which extracts the difference between the output of the multiplexer 7 and the output of the buffer 9. Reference numeral 11 is a D-FF, which latches the output of the XOR 10 with the output of the buffer 8. Reference numeral 12 is a selector, which switches the outputs of the two systems of the multiplexer 7 by the output of the D-FF 11 and constitutes a detecting means.

The mutual operation of the components configured as described above will be described. The input signal 13 is output by the buffers 1, 2, 3 and 4 to a plurality of delayed signals which are delayed by four stages as waveforms 15, 16, 17 and 18 with a delay amount of one gate as shown in FIG. Next, D-FF5
By latching the plurality of delayed signals at the rising edge of the reference signal 14, the change point of the input signal 13 delayed by the buffers 1, 2, 3, 4 is found, and the output signals 19, 20 of the D-FF 5 are found. , 21 and 22 are detected by the encoder 6 at the highest low level, the binary codes 23 and 24 corresponding thereto are output. By inputting it to the multiplexer 7, the reference signal 14
To the rising edge of, the waveform rising next is the waveform 1 of the plurality of delayed signals output from the buffers 1, 2, 3, and 4.
Extract from 5, 16, 17, and 18. Separately from that, by inputting the input signal 13 and the waveforms 15, 16, 17, 18 of the plurality of delayed signals to the multiplexer 7, the input signal 13 and its rising that is one before the rising of the reference signal 14 Waveforms of multiple delayed signals 1
Extract 5,16,17,18. So the reference signal 1
With respect to the rising of 4, the signal 26 rising next and the signal 25 rising one before are extracted. The signal 25
Buffer 9 with half the delay of buffers 1, 2, 3, 4
The signal and the signal 26 delayed by are input to the XOR 10, and the difference signal 28 thereof is a signal obtained by delaying the reference signal 14 by the delay amount buffer 8 of the multiplexer 7 and latched by the D-FF 11, whereby the phase of the reference signal 14 is delayed. This phase is selected when is close to the signal 25 which rises one before,
The control signal 29 of the selector 12 becomes low level, and the output signal 30 includes the input signal 13 phase-synchronized with the reference signal 14.
Can be automatically extracted in units of gate delay.
When the phase of the reference signal 14 is close to the next rising signal 26, that phase is selected, the control signal 29 of the selector 12 becomes high level, and the output signal 30 is the input signal phase-synchronized with the reference signal 14. 13 can be automatically extracted in units of gate delay. FIG. 2 shows the case where the phase of the signal 25 is selected.

As described above, according to the digital automatic phase controller of the embodiment of the present invention, the output of the phase closest to the gate-delayed input signal 13 with respect to the phase of the reference signal 14,
It is possible to faithfully extract the region before and after the phase discrimination.

[0011]

As is apparent from the above description, the digital automatic phase control device of the present invention detects the signal having the smallest phase difference as the reference signal from the signals having different delay amounts in a plurality of gate units, By performing the area discrimination, the signal with the closest phase to the phase of the reference signal can be extracted. So far, even if the previous phase matches the reference signal, the next The error that had extracted the phase has disappeared, and it has become possible to perform phase control with double the precision up to now. Further, the accuracy of phase control can be improved by increasing the number of stages of gate delay. In that case, DF
Since the number of Fs, encoders, multiplexers, etc. must be increased accordingly, the cost will be increased, but according to the present invention, the accuracy can be improved with almost no increase in cost.

Further, by utilizing the digital automatic phase control device of the present invention, it is possible to minimize the temporal shaking that occurs in the head and tape system of the VTR and the like, and to obtain a stable image with less shaking. Can be played.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a digital automatic phase controller according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the digital automatic phase controller according to the embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional digital automatic phase control device.

FIG. 4 is a timing chart showing the operation of the conventional digital automatic phase control device.

[Explanation of symbols]

 1,2,3,4 buffer 5,11 D-type flip-flop (D-FF) 6 encoder 7 multiplexer 8 and 9 buffer 10 exclusive OR (XOR) 12 selector

Claims (2)

[Claims] 1. A delay means for outputting a plurality of delay signals obtained by delaying an input signal by different delay amounts in units of gate delay, and a delay of a reference signal among the plurality of delay signals output from the delay means, The detection means includes a selection means for extracting two delay signals before and after having a phase close to each other, and a detection means for discriminating the area of the two delay signals to detect which delay signal is closer to the rising phase of the reference signal. A digital automatic phase control device which uses the detected signal as an output signal. 2. The digital automatic phase control device according to claim 1, wherein the area of the detecting means is compared with the reference signal by using a gate whose delay amount is half the delay amount per gate of the delay means.