JP2520886B2 - Phase difference detector - Google Patents

Description

TECHNICAL FIELD The present invention relates to a phase difference detection device, and more particularly to a phase difference detection device for detecting a phase difference between first and second signals containing periodic components.

BACKGROUND ART For example, in a time axis correction device (TBC) that corrects the time axis of a composite video signal by the NTSC standard color television system, a phase control oscillator (PLL) is driven in synchronization with a horizontal sync signal separated from an input video signal. Then, the video signal is converted into a digital signal by this phase-locked PLL output and is written in the TBC memory. The video signal written in the TBC memory is read from the TBC memory according to the stable reference signal.

The write clock when the video signal is stored in the TBC memory is synchronized with the PLL output, and this absorbs the fluctuation of the time axis contained in the input video signal. However, in reality, the PLL causes a slight phase delay when following the synchronizing signal of the input video signal, and fluctuations occur in the reproduced image represented by the output video signal unless the tracking error is corrected.

In order to correct the tracking error of the PLL, the phase of the color burst signal can be used in the NTSC composite video signal. That is, the tracking error of the PLL is determined by comparing the color burst signal of the input video signal with the color burst signal formed by the PLL, and the read timing of the video signal from the TBC memory is corrected by the phase corresponding to the error. . As a result, the time axis correction device outputs the video signal in a form in which the tracking error of the PLL is removed.

However, in the case of a video signal that does not take the form of an NTSC composite video signal, that is, a video signal that does not have a color burst signal, such as that recorded on a video floppy used in an electronic still camera, etc. The PLL tracking error could not be corrected with the time axis correction device for video signals.

OBJECT The present invention aims to provide an improved phase difference detection device.

DISCLOSURE OF THE INVENTION A phase difference detecting apparatus according to the present invention includes a plurality of delay stages for delaying an input signal by a predetermined delay time, and delay means for outputting the delayed signals from the corresponding delay stages, respectively. The first gate means for giving the earliest of the second signals to the delay means as an input signal, and the later of the first and second signals as the third signal. It has a second gate means and a plurality of inputs respectively connected to the respective delay stages of the delay means, and holds the states of the signals given to the plurality of inputs in response to the third signal. Output means for outputting a fourth signal representing the state.

According to the present invention, further, the signal conversion means for receiving the video signal including the first synchronization signal and converting it into corresponding digital data, and the first storage means for accumulating the video signal data output by the signal conversion means, Sync separation means for extracting the first sync signal from the video signal, and a phase control oscillator for forming a second sync signal in phase with the extracted first sync signal. Write control means for accumulating video signal data in one storage means, phase difference detection means for detecting a phase difference between the first synchronizing signal and the second synchronizing signal, and a reference signal of a predetermined frequency. And a read control means for reading the video signal data from the first storage means according to the reference signal, and a phase of the video signal data read from the first storage means according to the detected phase difference. Fix In the time axis correction device for a video signal, the phase difference detection means has a plurality of delay stages for delaying the input signal by a predetermined delay time, and each delay stage corresponds to each delayed signal. Output from the delay means, first gate means for providing the delay means with an earlier arrival of the first and second synchronizing signals as an input signal, and one of the first and second synchronizing signals. It has a second gate means for outputting the later one as a third signal, and a plurality of inputs respectively connected to the respective delay stages of the delay means, and the state of the signal given to the plurality of inputs is determined by the third state. Output means for holding in response to a signal and outputting a fourth signal indicating the held state.

Description of Embodiments Next, an embodiment in which the phase difference detection device according to the present invention is applied to a video signal time base correction device will be described in detail with reference to the accompanying drawings.

Referring to FIG. 2, in a time axis correction device according to an embodiment of the present invention, an input terminal 10 to which a video signal is input is an image data memory via a preprocessing circuit 12 and an analog / digital conversion circuit (ADC) 14. Connected to 16. Input terminal
The video signal input to 10 need not be in the form of an NTSC composite video signal and therefore may not have a color burst signal. For example, it may be of a format recorded on a video floppy used in an electronic still camera or the like.

The video signal input to the input terminal 10 undergoes preprocessing by the preprocessing circuit 12, is converted into digital data representing the level by the ADC 14, and is written in the image data memory 16 from the write port 18.

The image data memory 16 is a RAM or a shift register having a storage capacity capable of accumulating video signal data for at least one horizontal scanning (1H) period of the video signal. The writing is performed by the sync separation circuit 20 and the phase control oscillator (PLL) 22.
It is performed in synchronization with. The sync separation circuit 20 has an input terminal 10
The horizontal sync signal HDI is extracted from the video signal given to
This is output to output 24. The PLL 22 is a phase locked loop which forms a phase-controlled sync signal in synchronization with the input horizontal sync signal HDI and supplies the sync signal from its output 26 to the ADC 14 and the image data memory 16.

The sync signal output 26 of the PLL 22 is connected to the write control input of the image data memory 16. A write control circuit for the image data memory 16 and the error data memory 36 is configured by the PLL 22 and its connecting line. PLL output 26
In response to the sync signal of, the ADC 14 converts the video signal of its input 28 into a corresponding digital signal, and the digital signal is written in the image data memory 16.

Therefore, when the video signal input to the input terminal 10 includes a fluctuation on the time axis, the PLL 22 basically follows this and generates a synchronization signal at its output 26. In response to the sync signal, the ADC 14 performs analog / digital conversion, and this digital data is written in the image data memory 16. Therefore, basically, the video signal data is stored in the image data memory 16 in a form in which the time base fluctuation of the input video signal is corrected.
Stored in.

A phase error detection circuit 32 is also connected to the horizontal sync signal output 24 of the sync separation circuit 20. Phase error detection circuit 32
Is also connected to the output 30 of the PLL 22 and receives from it the horizontal sync signal HDP generated. The phase error detection circuit 32 is
As will be described later in detail, this is a circuit that compares the phases of both horizontal synchronizing signals HDI and HDP to determine the phase difference and the retardation. The determination result, that is, the error data is output to the output 34 in the form of digital data.

The output 34 of the phase error detection circuit 32 is the error data memory 36.
Connected to the write port of. Error data memory 36
Is a RAM or shift register having a storage capacity capable of accumulating error data for at least 1H period. The synchronization signal output 26 of the PLL 22 is also connected to the write control terminal of the error data memory 36. The writing is performed in response to the synchronizing signal from the PLL 22, and is therefore synchronized with the writing in the image data memory 16.

The read port 38 of the image data memory 16 is connected to the device output 46 via a phase correction circuit 40, a digital-analog conversion circuit (DAC) 42 and a post-processing circuit 44. The read port 48 of the error data memory 36 is also connected to the phase correction circuit 40. The reference signal output 52 of the reference oscillator 50 is connected to the read control inputs of both memories 16 and 36. The reference oscillator 50 is a grain oscillation circuit that generates a reference signal at its output 52 at a stable frequency. A read control circuit for both memories 16 and 36 is configured by these.

The phase correction circuit 40 synchronizes the phase of the video signal data read from the image data memory 16 in synchronization with the reference signal from the reference oscillator 50 with the horizontal sync signal received from the reference signal output 54 of the reference oscillator 50 as a reference. It is also a functional unit that corrects for each period by an amount corresponding to the error data read from the error data memory 36 in synchronization with the reference signal and outputs the corrected data to the output 56.

The DAC 42 is a signal conversion circuit that converts the phase-corrected video signal output from the output 56 of the phase correction circuit 40 into an analog signal. This analog signal is post-processed by the post-processing circuit 44, and is output from the device output 46 as a video signal having a stable time axis.

For example, as shown in FIG. 1, the phase error detection circuit 32 includes an active delay line 100, D-type flip-flops 102 and 104,
The encoder 106, the AND gate 108, and the OR gate 110 are connected and configured as shown. AND gate 108,
One input of the OR gate 110 and the clock input of the D-type flip-flop 104 are connected to the horizontal sync signal output 24 of the sync separation circuit 20. Also AND gate 10
The horizontal sync signal output 30 of the PLL 22 is connected to the other input of the 8 and the OR gate 110 and the D input of the D-type flip-flop 104. The output 112 of the AND gate 108 is connected to the clock input CLK of the D flip-flop 102.

The active delay line 100 has a tapped delay line 114 and a buffer amplifier 116. In the present embodiment, the delay line 114 uses eight taps, and a delay output with a delay time td of 5 nanoseconds is obtained for each stage of taps. Therefore, the error detection resolution of this phase error detection circuit 32 is 5 nanoseconds. A buffer amplifier 116 is connected to each tap, and their outputs HD1 ...
HD8 is connected to the D input of D flip-flop 102. This constitutes a delay stage.

The D-type flip-flop 102 has eight Q outputs Q1 to Q8. The level states of the corresponding D inputs HD1 to HD8 are output to these Q outputs Q1 to Q8. This output level state is maintained when the clock input CLK becomes high level.

The eight outputs Q1 to Q8 of the D-type flip-flop 102 are connected to correspond to the eight inputs 118 of the encoder 106. The encoder 106 is an encoding circuit that encodes the level states of these eight inputs 118 to form corresponding phase error data and outputs it to its output 34. This encoding is for converting the error data into a form in which the phase correction circuit 40 can easily execute the phase correction calculation of the video signal data later.

There are two types of encoding rules for the D-type flip-flop 104.
Is selectively set by the Q output 120 of the. The D-type flip-flop 104 is a polarity determination circuit that compares the phase of the input horizontal synchronization signal HDI received from the output 24 of the sync separation circuit 20 with the phase of the PLL horizontal synchronization signal HDP received from the output 30 of the PLL 22, and determines the delay between the two. is there.

As shown by the solid line in FIG. 3, the input horizontal synchronization signal HDI
If the rising edge of is delayed from the rising edge of the PLL horizontal sync signal HDP, the OR is generated at the rising edge of the input horizontal sync signal HDI at time t1.
The output 122 of the gate 110 becomes a high level, and the taps HD1 to HD8 of the delay line 114 output a high level with a delay of td per stage.

Next, at time t2, the PLL horizontal synchronizing signal HDP rises, which causes the output 112 of the AND gate 108 to go high. Therefore, the D flip-flop 102 latches the input state at that time. As shown in the figure, for example, if the rising edge of the input horizontal synchronizing signal HDI is delayed from the rising edge of the PLL horizontal synchronizing signal HDP by a time Δ, that is, in this example, a delay time td is 3 times or more and 4 times or less, Tap output HD
Latched when 1 to HD3 are high level and the same HD4 to HD8 are still low level. Therefore, the output 118 of the D-type flip-flop 102 outputs logic "1" for Q1 to Q3 and logic "0" for Q4 to Q8, as shown on the right side of FIG. This is because the input horizontal sync signal HDI is the PLL horizontal sync signal HD.
This example shows a delay of 15 to 20 nanoseconds from P.

The D-type flip-flop, that is, the polarity determination circuit 104,
Since the rising edge of the input horizontal synchronizing signal HDI is delayed from the rising edge of the PLL horizontal synchronizing signal HDP, a logic "0" is output to the Q output 120 at the latch time t2. So encoder 106
Encodes the latched logic state, adds a code indicating the delay of both horizontal synchronizing signals to create error data, and outputs 34
Output to. This error data is stored in the error data memory 36.

As shown by dotted lines 150 and 152 in FIG. 3, when the rising edge of the input horizontal synchronizing signal HDI is ahead of the rising edge of the PLL horizontal synchronizing signal HDP, the output of the OR gate 110 is output at the rising edge of the PLL horizontal synchronizing signal HDP at time t1. 122 goes high, time t2
AND gate 108 at the rising edge of the input horizontal synchronizing signal HDI at
Output 112 goes high. The polarity determination circuit 104 outputs a logic “1” to the Q output 120 at the time point t2 of the latch. Other operations are the same as those in the case where the rising edge of the input horizontal synchronizing signal HDI is delayed from the rising edge of the PLL horizontal synchronizing signal HDP described above.

As shown schematically in FIG. 4 during the 1H period, when the video signal 170 including the horizontal sync signal HDI is input to the input terminal 10, the sync separation circuit 20 separates the horizontal sync signal HDI, and the PLL 22 And the phase error detection circuit 32. PLL22
Inputs the synchronizing signal from its output 26 into the ADC 14 and the image data memory 16 in synchronization with the input horizontal synchronizing signal HDI.
At that time, the PLL 22 follows the input horizontal synchronizing signal HDI with a certain time delay Δ as shown in FIG. 4 (B). The ADC 14 performs A / D conversion in response to the sampling pulse 172 generated with such a tracking delay Δ.

Therefore, of the video signal 170, the shaded portion 178 in FIG. 7A is sampled, and the image information of the leading portion 174 thereof is not sampled and is lost. Moreover, the sampling pulse of the portion 176 near the end of the 1H period does not sample the image information because the video signal of the portion 176 does not already carry the image information of the effective screen area. Therefore, the same (C)
As illustrated in FIG. 2, digital data 178 a including image information of the shaded portion 178 of the same (A) is output from the ADC 14 and stored in the image data memory 16. This image data does not include image information in the portion 176a corresponding to the sampling pulse 176. In this way, if there is a tracking delay Δ of the PLL 22 with respect to the input horizontal synchronizing signal HDI, part of the image information of the original video signal is sampled and stored, and is stored in the image data memory 16.

On the other hand, the phase error detection circuit 32 receives the input horizontal sync signal HDI from the sync separation circuit 20 and the PLL horizontal sync signal HDP from the PLL 22.
The phases are compared to determine the phase difference and the retardation. In this example, phase error data indicating that the latter is delayed by the time Δ with respect to the former is output from the output 34 and accumulated in the error data memory 36. The accumulation in the error data memory 36 is performed in synchronization with the writing in the image data memory 16 in response to the synchronization signal given from the output 26 of the PLL 22.

Thus, the image data memory 16 and the error data memory
The 1 H worth of video signal data and phase error data respectively stored in 36 are read out to respective outputs 38 and 48 in synchronization with the stable reference signal supplied from the output 52 of the reference oscillator 50. The video signal data is input to the input 38 of the phase correction circuit 40 in a form shown in analog form for convenience in FIG. That is, the video signal data is output at a predetermined time with reference to the horizontal synchronizing signal HD input from the output 52 of the reference oscillator 50.
178a is read from the image data memory 16 to the phase correction circuit 40. Therefore, the image information of the leading portion 170 in the original 1H video signal 170 (FIG. 4A) remains missing,
Video signal data 178a from the beginning t3 of the effective video signal period
Is read. The corresponding phase error data is input to the phase correction circuit 40 from the output 48 of the error data memory 36.

Therefore, the phase correction circuit 40 delays the phase of the output video signal data 178a by a time Δ according to the phase error data, as shown in FIG. Therefore, the output 56 of the phase correction circuit 40 outputs the video signal 170a in a form in which the leading portion 174a of the video signal has no image information for the period Δ and the entire video signal data 178a is delayed by the phase Δ. As can be seen, the video signal 170a output at the output 56 of the phase correction circuit 40
, The image information of the beginning portion 174 of the original video signal 170 is missing, but the image information 178 carried by the original video signal 170 is at a regular time position as the signal 178a, that is, the image information 1 of the original video signal 170.
It carries the same phase as 78. Therefore, the fluctuation of the time axis due to the tracking delay Δ of the PLL 22 is substantially removed from the output video signal 170a.

This video signal is converted into a corresponding analog signal by the digital / analog conversion circuit 42, subjected to necessary post-processing by the post-processing circuit 44, and is output from the device output 46 as a video signal with stable time axis at a predetermined rate. Is output.

In a system where the PLL horizontal sync signal HDP is always delayed with respect to the input horizontal sync signal HDI, the phase error detection and detection circuit
The 32 AND gates 108, OR gates 110 and D-type flip-flops 104 may not be provided. In that case, as shown in FIG. 6, the output 24 of the sync separation circuit 20 is directly connected to the clock input CLK of the D-type flip-flop 102, and the delay line 114.
The output 30 of the PLL 22 is directly connected to the input 122 of the. Delay line
The operations of the 100, D-type flip-flop 102 and the encoder 106 are similar to the case where the rising edge of the input horizontal synchronizing signal HDI is delayed from the rising edge of the PLL horizontal synchronizing signal HDP with reference to FIG.

In addition, the PLL horizontal sync signal for the input horizontal sync signal HDI
In a system in which HDP always advances, PLL2 is applied to the clock input CLK of the D-type flip-flop 102 with the configuration shown in FIG.
The second output 30 may be input, and the input 122 of the delay line 114 may be modified so that the output 24 of the sync separation circuit 20 is input.

It should be noted that the embodiments described here are for describing the present invention, and the present invention is not necessarily limited thereto. Modifications and variations that can be made by those skilled in the art without departing from the spirit of the present invention. Modifications are included in the scope of the present invention.

For example, in the phase difference detecting device according to the present invention, the signal whose phase difference is to be detected is not limited to the video signal. The detected signal may be a signal including some form of periodic component such as a synchronization signal. Therefore, the present invention is, for example, a servo control mechanism of a circuit driving device such as a magnetic disk spindle motor or a magnetic head drum motor.
It is effectively applied to a circuit that detects the phase difference between two signals.

Effect As described above, according to the present invention, the phase error between the sync signal of the input video signal and the sync signal formed by the phase control oscillation system is detected, and the phase of the video signal read out from the image memory for time axis correction is calculated as follows. By correcting according to the phase error, the tracking error generated in the phase control oscillation system is absorbed and a stable video signal on the time axis is output. Therefore, the time axis can be effectively corrected even for the video signal having no color burst signal. Since the tracking error is absorbed by the digital database, the circuit configuration is simple and the stability and accuracy are excellent.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of a phase error detection circuit according to the present invention, FIG. 2 is a functional block diagram showing an overall configuration example of a time axis correction device to which the present invention is applied, and FIG. Timing waveform chart for explaining the operation of the phase error detection circuit shown in the figure, FIGS. 4 and 5 are schematic timing waveform charts for explaining the operation of the embodiment shown in FIG. 2, FIG. FIG. 9 is a functional block diagram similar to FIG. 1 showing another embodiment of the phase error detection circuit. Description of symbols for main parts 16 …… Image data memory 20 …… Sync separation circuit 22 …… PLL 32 …… Phase error detection circuit 36 …… Error data memory 40 …… Phase correction circuit 50 …… Reference oscillator

Claims (3)

(57) [Claims] 1. A sync separation means for receiving a video signal including a first horizontal sync signal and extracting the first horizontal sync signal from the video signal, and a phase synchronization with the extracted first horizontal sync signal. A phase control oscillator that forms a second horizontal synchronizing signal, and detects a phase difference between the first and second horizontal synchronizing signals. A first gate means for outputting whichever of the two horizontal synchronizing signals arrives earlier; and a plurality of delay stages for delaying the signal from the first gate means by a predetermined delay time, respectively. Delay means for outputting the delayed signal from each corresponding delay stage; second gate means for outputting the later one of the first and second horizontal synchronization signals as the third signal; Each delay stage of the delay means A plurality of inputs connected to each other, and a state of a signal given to the plurality of inputs is changed to a third state.
And a means for holding the signal in response to the signal and outputting a fourth signal indicating the held state. 2. The apparatus according to claim 1, wherein the output means holds a state of a signal given to the plurality of inputs in response to a third signal and outputs a fourth signal. And a coding means for coding the fourth signal and outputting it as a signal representing the phase difference between the first signal and the second horizontal synchronizing signal. Phase difference detector. 3. The apparatus according to claim 2, wherein said encoding means has a discrimination means for discriminating the delay of the first and second horizontal synchronizing signals, A phase difference detecting device characterized in that the fourth signal is encoded accordingly.