JPH0319578A - Video signal processing unit - Google Patents

Video signal processing unit

Info

Publication number
JPH0319578A
JPH0319578A JP1155309A JP15530989A JPH0319578A JP H0319578 A JPH0319578 A JP H0319578A JP 1155309 A JP1155309 A JP 1155309A JP 15530989 A JP15530989 A JP 15530989A JP H0319578 A JPH0319578 A JP H0319578A
Authority
JP
Japan
Prior art keywords
circuit
synchronizing signal
horizontal synchronizing
horizontal
guarantee
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1155309A
Other languages
Japanese (ja)
Inventor
Yoshinobu Oishi
大石 義信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1155309A priority Critical patent/JPH0319578A/en
Publication of JPH0319578A publication Critical patent/JPH0319578A/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)
  • Picture Signal Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE:To guarantee the missing of a horizontal synchronizing signal and also to reduce noise component caused in a synchronizing separator circuit in a weak electric field by providing a horizontal synchronizing signal guarantee circuit and a noise elimination circuit. CONSTITUTION:The unit consists of a horizontal synchronizing signal guarantee circuit 3, a noise elimination circuit 4, a clock generating circuit 5, a horizontal synchronizing signal separator circuit 1 and a video signal digital processing circuit 2. A leading edge detection circuit 6 in the horizontal synchronizing signal guarantee circuit 3 detects the edge of an inputted horizontal synchronizing signal and resets a horizontal synchronizing signal generating circuit 7 with the pulse to generate a horizontal synchronizing signal for each horizontal scanning period. An AND gate 8 of the noise elimination circuit 4 compares the phase of the horizontal synchronizing signal from the horizontal synchronizing signal separator circuit 1 and the phase of the horizontal synchronizing signal from the horizontal synchronizing signal generating circuit 7 and a edge leading detection circuit 9 detects the leading edges of the following signals with the trailing edge of the horizontal synchronizing signal as the time axis. Thus, a dropout caused at the reproduction of a video tape recorder due to the missing of the horizontal synchronizing signal or the fluctuation of period is eliminated and the horizontal synchronizing signal in compliance with the broadcast standards is generated.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、欠落或いは周期の変動した水平同期信号を保
証又は補正すると共にドロップアウトで生じたスキュー
歪みをディジタル処理回路で補正した映像信号処理装置
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device that guarantees or corrects a horizontal synchronizing signal that is missing or has a variable period, and also corrects skew distortion caused by dropouts using a digital processing circuit. It is something.

従来の技術 近年、映像信号の処理にディジタル信号処理回路が多く
利用されるようになってきた。
2. Description of the Related Art In recent years, digital signal processing circuits have come into widespread use for processing video signals.

以下に従来の映像信号処理装置について説明する。第3
図は従来の映像信号処理装置のブロック図であり、1ぱ
水平同期信号分離回路、2ぱ映像信号デイジタル処理回
路である。
A conventional video signal processing device will be described below. Third
The figure is a block diagram of a conventional video signal processing device, in which 1 part is a horizontal synchronizing signal separation circuit and 2 parts is a video signal digital processing circuit.

以上のよりに構戊された映像信号処理装置について、以
下その動作を説明する。
The operation of the video signal processing device configured as described above will be explained below.

映像信号ディジタル処理回路2には、水平同期信号分離
回路1から直接、入力される。
The video signal digital processing circuit 2 is directly inputted from the horizontal synchronization signal separation circuit 1 .

発明が解決しようとする課題 しかしながら上記の従来の構戊では、水平同期信号分離
回路1から直接、映像信号ディジタル処理回路2に入力
されるので、弱電界等で水平同期信号が欠落したり、ノ
イズ等が水平同期信号に乗った場合に映像信号ディジタ
ル処理回路2が誤動作をするという問題点を有していた
Problems to be Solved by the Invention However, in the above-mentioned conventional structure, since the horizontal synchronizing signal separation circuit 1 directly inputs the video signal to the digital processing circuit 2, the horizontal synchronizing signal may be lost due to weak electric fields, etc., or noise may occur. There is a problem in that the video signal digital processing circuit 2 malfunctions when the horizontal synchronizing signal is applied to the horizontal synchronizing signal.

本発明は上記従来の問題点を解決するもので、水平同期
信号の欠落を保証し、かつノイズ成分を除去することの
できる映像信号処理装置を提供することを目的と−する
SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide a video signal processing device that can guarantee the absence of a horizontal synchronizing signal and remove noise components.

課題を解決するための手段 この目的を達或するために本発明の映像信号処理装置は
、一水平走査期間をカウントし、水平同期信号を発生す
る水平同期信号保証回路と水平同期信号の後縁からある
一定期間、入力信号を遮断する回路から構成されている
Means for Solving the Problems To achieve this object, the video signal processing device of the present invention includes a horizontal synchronization signal guarantee circuit that counts one horizontal scanning period and generates a horizontal synchronization signal, and a trailing edge of the horizontal synchronization signal. It consists of a circuit that blocks input signals for a certain period of time.

作用 この構成によって、水平同期信号の欠落保証及び水平同
期信号の後縁に生じるノイズ成分を除去することができ
る。
Effect: With this configuration, it is possible to guarantee the omission of the horizontal synchronizing signal and to remove noise components occurring at the trailing edge of the horizontal synchronizing signal.

実施例 以下、本発明の一実施例について、図面を参照しながら
説明する。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例における映像信号処理装置の
ブ07ク図を示すものである。第1図にもいて、3は水
平同期信号保証回路、4はノイズ除去回路、6はクロノ
ク発生回路、なお1は水平同期信号分離回路、2は映像
信号ディジタlレ処理回路で、これらは従来例の構成と
同じものである。
FIG. 1 shows a block diagram of a video signal processing device according to an embodiment of the present invention. Also shown in Fig. 1, 3 is a horizontal synchronization signal guarantee circuit, 4 is a noise removal circuit, 6 is a chronograph generation circuit, 1 is a horizontal synchronization signal separation circuit, and 2 is a video signal digital processing circuit. This is the same configuration as the example.

以上のように構成された本実施例の映像信号処理装置に
ついて以下その動作を説明する。
The operation of the video signal processing apparatus of this embodiment configured as described above will be described below.

まず、水平同期信号分離回路1に入力された水平同期信
号は、水平同期信号保証回路3とノイズ除去回路4に入
力される。水平同期信号保証回路3では、入力された水
平同期信号を立上り検出回路6でエッジ検出し、このパ
ルスで水平同期信号発生回路7をリセットし、水平走査
期間毎に水平同期信号を発生する。
First, the horizontal synchronization signal input to the horizontal synchronization signal separation circuit 1 is input to the horizontal synchronization signal guarantee circuit 3 and the noise removal circuit 4. In the horizontal synchronization signal guarantee circuit 3, the edge of the input horizontal synchronization signal is detected by the rising edge detection circuit 6, and the horizontal synchronization signal generation circuit 7 is reset with this pulse to generate a horizontal synchronization signal every horizontal scanning period.

更に、水平同期信号保証回路3から出力された水平同期
信号は、ノイズ除去回路4に入力される。
Furthermore, the horizontal synchronization signal output from the horizontal synchronization signal guarantee circuit 3 is input to the noise removal circuit 4.

ノイズ除去回路4では、水平同期信号分離回路1からの
水平同期信号と水平同期信号発生回路7からの水平同期
信号とをANDゲート8で位相比較し、水平同期信号の
後縁が時間軸で後に来る信号の立上りを立上り検出回路
9で検出する。このバμスを基準として、一定期間、水
平同期信号をノイズ除去パルス発生回路10でHi(h
に固定し、ANDゲート8とノイズ除去パルス発生部1
0とをORゲート11を通して、映像信号ディジタル処
理回路2に入力する。つ曾り、ノイズ除去回路4では、
入力される水平同期信号の周期が放送規格値よりも長く
或いは短くなった場合には、水平同期信号保証回路3か
らの水平同期信号を用い、放送規格値の周期で入力され
ている場合には、入力水平同期信号を用いる方法を採用
している。1た、ビデオテーブレコーダ(以下VTRと
記す)の再生時に生じるドロップアウトによるスキュー
歪み対策を行う。第2図に、水平同期信号が欠落し2た
場合とドロップアウトが生じた場合に映像信壮ディジタ
ル処理回路2に入力される水平同期信号(第2図中では
、出力水平同期信号と記す)の状態を図示している。第
2図(a)は正常に水平同期信号が入力された場合、第
2図(b)は、水平同期信号に欠落が生じた場合、第2
図(0)は、水平同期信号にドロップアウトが生じた場
合を図示してかり、各々が補正された信号は、出力水平
同期信号である。
In the noise removal circuit 4, the phase of the horizontal synchronization signal from the horizontal synchronization signal separation circuit 1 and the horizontal synchronization signal from the horizontal synchronization signal generation circuit 7 is compared by an AND gate 8, so that the trailing edge of the horizontal synchronization signal is located later on the time axis. The rising edge of the coming signal is detected by the rising edge detection circuit 9. Based on this bus μ as a reference, the horizontal synchronizing signal is set to Hi (h
and the AND gate 8 and the noise removal pulse generator 1
0 is input to the video signal digital processing circuit 2 through the OR gate 11. In the noise removal circuit 4,
If the cycle of the input horizontal synchronization signal is longer or shorter than the broadcast standard value, the horizontal synchronization signal from the horizontal synchronization signal guarantee circuit 3 is used, and if the cycle is input at the broadcast standard value, , a method using an input horizontal synchronization signal is adopted. First, countermeasures are taken against skew distortion caused by dropouts that occur during playback of a video table recorder (hereinafter referred to as VTR). Figure 2 shows a horizontal synchronization signal that is input to the video digital processing circuit 2 when the horizontal synchronization signal is missing (2) or when a dropout occurs (referred to as the output horizontal synchronization signal in Figure 2). The state is illustrated. Figure 2 (a) shows when the horizontal synchronizing signal is input normally, and Figure 2 (b) shows when the horizontal synchronizing signal is missing.
Figure (0) illustrates a case where a dropout occurs in the horizontal synchronization signal, and each corrected signal is the output horizontal synchronization signal.

以上のように本実施例によれば、水平同期信号保証回路
とノイズ除去回路を設けることにより、水平同期信号の
欠落や周期変動史には、ビデオテーブレコーダ(VTR
)の再生時に生じるドロップアウトを除去し、放送規格
に準じた水平同期信号を発生することができる。
As described above, according to this embodiment, by providing the horizontal synchronization signal guarantee circuit and the noise removal circuit, it is possible to eliminate the loss of the horizontal synchronization signal and the periodic fluctuation history of the video table recorder (VTR).
), it is possible to eliminate dropouts that occur during playback and generate a horizontal synchronization signal that complies with broadcasting standards.

発明の効果 本発明は、水平同期信号保証回路とノイズ除去回路を設
けることにより、弱電界中に同期分離回路に生じる水平
同期信号欠落の保証及びノイズ戊分を軽減することがで
き、更に、VTRの再生時に生じるドロップアウトによ
り、テレビ画面上に現われるスキューを無くすという効
果を得ることができる優れた映像信号処理装置を実現で
きるものである。
Effects of the Invention By providing a horizontal synchronization signal guarantee circuit and a noise removal circuit, the present invention can guarantee horizontal synchronization signal loss and reduce noise that occurs in the synchronization separation circuit during a weak electric field. It is possible to realize an excellent video signal processing device that can obtain the effect of eliminating skew that appears on a television screen due to dropouts that occur during playback.

【図面の簡単な説明】 第1図は木発明の一実施例における映像信号処理装置の
ブロック図、第2図は、水平同期信号を補正する場合の
状態を示すタイミング図、第3図は従来の映像信号処理
装置のブロック図である。 1・・・・・・水平同期信号分a回路、2・・・・・・
映像信号ディジタル処理回路、3・・・・・・水平同期
信号保証回路、4・・・・・・ノイズ除去回路、5・・
・・・・クロック発生回路、6・・・・・・立上りエッ
ジ検出回路、7・・・・・・水平同期信号発生回路、8
・・・・・・ANDゲート、9・・・・・・立上りエッ
ジ検出回路、10・・・・・・ノイズ除去パルス発生回
路、11・・・・・・ORゲート。
[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a block diagram of a video signal processing device in an embodiment of the invention, Fig. 2 is a timing diagram showing the state when correcting a horizontal synchronization signal, and Fig. 3 is a conventional 1 is a block diagram of a video signal processing device of FIG. 1...Horizontal synchronization signal a circuit, 2...
Video signal digital processing circuit, 3...Horizontal synchronization signal guarantee circuit, 4...Noise removal circuit, 5...
... Clock generation circuit, 6 ... Rising edge detection circuit, 7 ... Horizontal synchronization signal generation circuit, 8
...AND gate, 9 ...rising edge detection circuit, 10 ...noise removal pulse generation circuit, 11 ...OR gate.

Claims (1)

【特許請求の範囲】[Claims] 一水平走査期間をカウントし、水平同期信号を発生する
回路と、水平同期信号の前縁或いは後縁からある一定期
間に生じるノイズ成分を除去する回路とを備えた映像信
号処理装置。
A video signal processing device that includes a circuit that counts one horizontal scanning period and generates a horizontal synchronizing signal, and a circuit that removes noise components that occur during a certain period from the leading edge or trailing edge of the horizontal synchronizing signal.
JP1155309A 1989-06-16 1989-06-16 Video signal processing unit Pending JPH0319578A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1155309A JPH0319578A (en) 1989-06-16 1989-06-16 Video signal processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1155309A JPH0319578A (en) 1989-06-16 1989-06-16 Video signal processing unit

Publications (1)

Publication Number Publication Date
JPH0319578A true JPH0319578A (en) 1991-01-28

Family

ID=15603077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1155309A Pending JPH0319578A (en) 1989-06-16 1989-06-16 Video signal processing unit

Country Status (1)

Country Link
JP (1) JPH0319578A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04313962A (en) * 1991-04-08 1992-11-05 Mitsubishi Electric Corp Synchronization correction circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04313962A (en) * 1991-04-08 1992-11-05 Mitsubishi Electric Corp Synchronization correction circuit

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