JPH04313962A - Synchronization correction circuit - Google Patents

Abstract

PURPOSE:To obtain a horizontal synchronizing signal in which a pulse number is unchanged when a synchronization pulse of the horizontal synchronizing signal is missing or a fault pulse is added to the horizontal synchronizing signal. CONSTITUTION:The correction circuit is provided with a counter circuit 1 counting a clock CK and reset for a horizontal synchronizing period, a latch circuit 13 latching a prescribed output for a period when a pulse is outputted from an output terminal A of the counter circuit 1 till a pulse is outputted from an output terminal B, a latch circuit 14 latching a prescribed output for a period till a pulse is outputted from an output terminal C, a NAND circuit 8 receiving an output of latch circuits 13, 14, a NAND circuit 7 receiving an output of the NAND circuit 8 and an inverted horizontal synchronizing signal HSYC and a NOR circuit 6 receiving an inverted output of the NAND circuit 7 and a pulse from the output terminal C.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization correction circuit for correcting a horizontal synchronization signal in a composite image signal of a television.

0002

2. Description of the Related Art FIG. 5 is a circuit diagram of a conventional synchronization correction circuit of this type. When a time longer than the time from the rising edge of the horizontal synchronizing signal HSYC to the next falling edge is counted, the clock CK is input to the trigger terminal T of the counter circuit 15 which outputs a one-shot pulse. The one-shot pulse output from the output terminal C of the counter circuit 15 is input to one input terminal of the NOR circuit 16. The horizontal synchronizing signal HSYC is input to the NOT circuit 17, and its output signal is input to the other input terminal of the NOR circuit 16. Horizontal synchronization signal HSY corrected from NOR circuit 16
C' is output, and its horizontal synchronizing signal HSYC' is input to the low active reset terminal #R of the counter circuit 15.

Next, the operation of this synchronization correction circuit will be explained with reference to FIG. 6, which shows a timing chart of signals of each part. First, a case where the horizontal synchronizing signal HSYC is normal will be explained. Horizontal synchronization signal HSY shown in Figure 6(a)
When C is input to the NOT circuit 17, the horizontal synchronizing signal H
SYC is inverted and one input terminal of the NOR circuit 16 is
“H” when horizontal synchronization signal HSYC is “L” level
level, and the output of the NOR circuit 16 becomes "L" level. Then, the reset terminal #R of the counter circuit 15 is
The counter circuit 15 is reset. In this reset state, the horizontal synchronization signal HSYC is “L”
Lasts for a certain period of time at the level. That is, the counter circuit 15 starts counting the clock CK from the rising edge of the horizontal synchronizing signal HSYC, is reset at the next falling edge of the horizontal synchronizing signal HSYC, and repeats the same operation. Then, a horizontal synchronizing signal HSYC similar to the horizontal synchronizing signal HSYC inputted to the NOT circuit 17 is output from the NOR circuit 16.

Next, when the horizontal synchronizing signal HSYC becomes abnormal and does not fall at a predetermined period, the horizontal synchronizing signal HS
The operation of correcting YC will be explained. Now, the horizontal synchronizing signal HS shown in FIG. 6(a) is input to the NOT circuit 17.
When YC stops falling as shown by the broken line and a synchronization pulse Z is missing, the counter circuit 15 is not reset and the count value of the counter circuit 15 increases to reach a predetermined value. Then, the one-shot pulse P is output from the output terminal C of the counter circuit 15 as shown in FIG. 6(b), and the output of the NOR circuit 16 becomes "L" level.
As shown in FIG. 6(c), the NOR circuit 16 outputs a one-shot pulse P' for correcting the missing synchronizing pulse Z. Thereby, a corrected horizontal synchronizing signal HSYC' is obtained by making it equal to the number of synchronizing pulses of the horizontal synchronizing signal HSYC input from the NOR circuit 16 to the NOT circuit 17.

[0005]

[Problem to be solved by the invention] By the way, when a negative abnormal pulse is added to the horizontal synchronizing signal HSYC input to the NOT circuit 17, when the abnormal pulse falls, the horizontal synchronizing signal HSYC falls. The counter circuit 15 is reset as in the case. Then, the output of the NOR circuit 16 becomes "L" level. Therefore, NOR
From the circuit 16, an abnormal pulse is added to the synchronization pulse,
Horizontal synchronization signal HSYC′ after correction with increased number of pulses
This causes a problem in that the vertical height of the displayed image changes, which adversely affects the displayed image. In view of such problems, the present invention is provided with a pulse addition means and a pulse removal means, so that when a synchronization pulse of the horizontal synchronization signal is missing or an abnormal pulse is added, the horizontal synchronization signal is corrected accordingly. The purpose of this invention is to provide a synchronization correction circuit that can perform the following steps.

[0006]

[Means for Solving the Problems] A synchronization correction circuit according to the present invention has a first time shorter than the time from the end of a horizontal synchronization period of a horizontal synchronization signal in a composite image signal to the start of the next horizontal synchronization period. If a pulse occurs during the timing period, the generated pulse is removed, and a second time period longer than the period from the end of the horizontal synchronization period of the horizontal synchronization signal to the start of the next horizontal synchronization period is set. If there is no synchronization pulse during the period in which the clock is being measured, the configuration is such that a pulse is added.

[0007]

[Operation] If a pulse is added to the horizontal synchronizing signal during the period in which the first time is measured from the end of the horizontal synchronizing period of the horizontal synchronizing signal, the added pulse is removed. During the period in which the second time is being measured from the end of the horizontal synchronization period,
If there is no synchronization pulse of the horizontal synchronization signal, add a pulse. As a result, even if the number of pulses of the horizontal sync signal increases or decreases,
A horizontal synchronization signal is obtained that is corrected so that the number of pulses does not increase or decrease.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to drawings showing embodiments thereof. FIG. 1 is a circuit diagram of a synchronization correction circuit according to the present invention. A clock CK is input to the trigger terminal T of the counter circuit 1. The output signal from output terminal A of counter circuit 1 is input to the other input terminal of NOR circuit 5, and output signal from output terminal B
The output signal from the output terminal C is input to the second input terminal of the three-input NOR circuit 2, and the output signal from the output terminal C is input to one input terminal of the NOR circuit 3 and one input terminal of the NOR circuit 6. The output signal of the NOR circuit 5 is a 3-input NOR
The output signal of circuit 2 is input to the third input terminal of circuit 2, and the output signal of circuit 2 is NOR.
It is input to the other input terminal of the ND circuit 8.

The output signal of the NAND circuit 8 is input to one input terminal of the NAND circuit 7. Horizontal synchronization signal HSYC
is input to NOT circuit 9, and its output signal is NAND
It is input to the other input terminal of the circuit 7. The output signal of the NAND circuit 7 is input to the NOT circuit 12, and the output signal is input to the other input terminals of the NOR circuit 6, NOT circuits 10 and 3.
The signal is input to the first input terminal of the input NOR circuit 2. NOT
The output signal of the circuit 10 is input to the NOT circuit 11,
The output signal is input to the other input terminal of the NOR circuit 4.

The output signal of the NOR circuit 4 is
It is input to the other input terminal of circuit 3, and its output signal is NOR
The signal is input to one input terminal of the circuit 4 and one input terminal of the NAND circuit 8, and a low active output prohibition signal #MASK is output from the output side of the NOR circuit 3. The NOR circuit 6 receives the corrected horizontal synchronizing signal H.
SYC' is output, and its horizontal synchronizing signal HSYC' is connected to the low active reset terminal # of the counter circuit 1.
input to R. The NOR circuits 3 and 4 constitute a latch circuit 14, and the NOR circuits 2 and 5 constitute a latch circuit 13.

The counter circuit 1 receives the corrected horizontal synchronizing signal H.
After SYC' rises, a one-shot pulse is output from output terminal A, and a one-shot pulse is counted by counting the time shorter than the time from the rising edge of horizontal synchronizing signal HSYC' to the next falling edge, that is, the first time. A shot pulse is output from output terminal B, and a one-shot pulse is output from output terminal C by counting a time longer than the time from the rising edge of the horizontal synchronizing signal HSYC to the next falling edge, that is, the second time. It has become.

Next, the correction operation by the synchronization correction circuit configured as described above will be explained with reference to FIGS. 3 and 4 showing timing charts of various signals. First, the timing of the signals output from the output terminals A, B, and C of the counter circuit 1 is shown in Figure 2.
This is explained by: Composite image signal SV shown in Figure 2(a)
Color burst CB from the end of horizontal synchronization period H of D
During this period, the pulse PA is output from the output terminal A as shown in FIG. 2(c). Also, during the period of front porch FP, pulse PB is output from output terminal B as shown in Fig. 2(d).
Output. Furthermore, in the back porch BP after the next horizontal synchronization period H, and during the period up to the color burst CB, as shown in FIG.
e) Output pulse PC from output terminal C as shown in FIG. However, the pulse PC from the output terminal C is not output because the counter circuit 1 is reset when the next horizontal synchronization period H is reached and the horizontal synchronization period HSYC falls, and the horizontal synchronization signal HSYC rises. to the next horizontal synchronization period H
When the horizontal synchronizing signal HSYC does not fall, a pulse PC is output from the output terminal C.

Now, FIG. 3 (
a) When the horizontal synchronization signal HSYC shown in
The output of the T circuit 9 goes to the "L" level, and the output of the NAND circuit 7 to which the output is input goes to the "H" level regardless of the output P1 of the NAND circuit 8. And NOT
The output of circuit 12 becomes "L" level, and NOR circuit 6
is input to. Here, if the horizontal synchronizing signal HSYC falls periodically within a predetermined time, no pulse is output from the output terminal C of the counter circuit 1, so the NOR
The output of circuit 6 becomes "H" level. Thereby, the counter circuit 1 starts counting the clock CK.

After the horizontal synchronizing signal HSYC rises, the "L" level output of the NOT circuit 12 becomes NOT.
It is inverted by the circuit 10 and further inverted by the NOT circuit 11, and the "L" output of the NOT circuit 11 is inputted to the NOR circuit 4, and the output of the NOR circuit 4 becomes "L" level. Therefore, the output of NOR circuit 3 becomes "H" level, and the low active mask signal # shown in Figure 3(g) is generated.
MASK is not output, and one input terminal of the NAND circuit 8 is held at the "H" level.

On the other hand, the counter circuit 1 counts the clock CK and outputs "H" from the output terminal A as shown in FIG. 3(b).
” level pulse PA is output, the output of the NOR circuit 5 becomes the “L” level, and is input to the third input terminal of the 3-input NOR circuit 2. 3-input NOR circuit 2 first
The "L" level output of the NOT circuit 12 is input to the input terminal, and the second input terminal is at the "L" level because the pulse PB is not output from the output terminal B of the counter circuit 1. Therefore, the low active output #, 2 of the 3-input NOR circuit 2 is at the “H” level, and the output is input to the NOR circuit 5, and the 3-input NOR circuit 2
The output #P2 of R circuit 2 is “H” as shown in Fig. 3(f).
" level is input to the other input terminal of the NAND circuit 8, and the output P1 of the NAND circuit 8 is as shown in FIG.
) is held at the "L" level as shown in FIG.

After that, when the "H" level pulse PB is output from the output terminal B of the counter circuit 1 as shown in FIG. 3(c), the output #P2 of the 3-input NOR circuit 2 becomes as shown in FIG. 3(f). As shown, it is inverted to the "L" level. Then, the output P1 of the NAND circuit 8 is inverted to the "L" level as shown in FIG. 3(e). In other words, the output #P2 of NOR circuit 2 is as shown in Figure 3(f)
As shown in , the period from the output point of pulse PA to the output point of pulse PB is at "H" level, and that period is N.
The output P1 of the AND circuit 8 is as shown in Fig. 3(e).
It is held at "L" level. The output of the NAND circuit 7 changes according to the horizontal synchronizing signal HSYC input to the NOT circuit 9, regardless of the output P1 of the NAND circuit 8, and the corrected horizontal synchronizing signal HSYC' output from the NOR circuit 6 is , NOT are obtained in synchronization with the horizontal synchronizing signal HSYC input to the circuit 9 as shown in FIG. 3(h).

By the way, when a synchronization pulse dropout Z occurs as shown by the broken line in FIG. 3(a), the horizontal synchronization signal HSYC does not fall during the horizontal synchronization period, and therefore
is no longer reset, and the pulse PC shown in FIG. 3(d) is output from the output terminal C. Then, the output of the NOR circuit 3 goes to "L" level, and the low active mask signal #MASK is output, and the output of the NAND circuit 8, P1, is caused by the "L" level output of the NOR circuit 3.
is inverted to “H” level as shown in Figure 3(e), and
It is held at the "H" level until the next pulse PA is output from the output terminal A and the output #P2 of the three-input field circuit 2 is inverted.

Then, the output P1 of the NAND circuit 8 is "H"
At the point when the level is inverted, the output of the NAND circuit 7 becomes “H”.
” level, the output of the NOT circuit 12 becomes the “L” level, and is input to the NOR circuit 6. The NOR circuit 6 receives an "H" level pulse from the output terminal C shown in Figure 3(d), and as a result, the NOR circuit 6 outputs a negative pulse P' as shown in Figure 3(h). As a result, a pulse for the synchronization pulse missing Z is added, and the number of pulses of the horizontal synchronization signal HSYC' outputted from the NOR circuit 6 becomes equal to the number of pulses of the horizontal synchronization signal HSYC inputted to the NOT circuit 9.

As a result, a horizontal synchronizing signal HSYC', which is a corrected horizontal synchronizing signal HSYC, is obtained from the NOR circuit 6, so that, for example, the horizontal synchronizing signal HSYC
Malfunctions of circuits controlled based on the number of pulses can be prevented. In addition, when synchronization pulse missing Z occurs, Figure 3 (
g) If the mask signal #MASK shown in is output and input to an image display circuit (not shown), image display is prohibited during the period when the mask signal #MASK is generated, and an image is added due to the synchronization pulse missing Z. This pulse P' can prevent an adverse effect on the displayed image.

Next, the signal in FIG. 4 (a) input to the NOT circuit 9
) Between the horizontal synchronization period of the horizontal synchronization signal HSYC and the next horizontal synchronization period, negative noise pulses NP, N
When P and NP are added, for example, if the first noise pulse NP is input to the NOT circuit 9, NO
The output of the T circuit 9 becomes "H" level. During the period from when the pulse PA is output from the output terminal A of the counter circuit 1 until the pulse PB is output from the output terminal B, the output P1 of the NAND circuit 8 becomes "L" as shown in FIG. 3(e). ” level, the output of the NAND circuit 7 goes to the “H” level, the output of the NOT circuit 12 goes to the “L” level, and the pulse PC from the output terminal C of the counter circuit 1 is given. NOR when not
The output of circuit 6 remains at the "H" level.

The corrected horizontal synchronizing signal HSYC' shown in FIG. 3(g) output from the NOR circuit 6 has the following:
A pulse corresponding to the noise pulse NP shown in FIG. 3(a) is not generated. Therefore, a corrected horizontal synchronizing signal HSYC' equal to the number of pulses when no noise pulse NP is added to the horizontal synchronizing signal HSYC input to the NOT circuit 9 is obtained, and is not affected by the noise pulse NP. Therefore, for example, the operation of a circuit controlled based on the number of pulses of the horizontal synchronizing signal HSYC can be performed without being affected by the noise pulse NP.

In this way, the horizontal synchronizing signal HSYC
When a synchronizing pulse missing Z occurs, a pulse PC is output from the output terminal C of the counter circuit 1, and a NOR circuit 6 is generated based on the logic between the pulse PC and the output of the NOT circuit 12.
A pulse corresponding to the synchronization pulse missing Z is output from
The number of pulses of the horizontal synchronizing signal HSYC is corrected. On the other hand, the period from when the pulse PA is output from the output terminal A of the counter circuit 1 until the pulse PB is output from the output terminal B is determined by the output #P2 of the latch circuit 13.
Since the output P1 of the AND circuit 8 is held at the "L" level, even if a noise pulse NP is added to the horizontal synchronizing signal HSYC within that period, the output of the NAND circuit 7 will not be held at the "H" level.
The corrected horizontal synchronizing signal HSYC', which is the output of the NOR circuit
No pulse corresponding to P is added, and the horizontal synchronization signal HSYC
' is corrected so that the number of pulses does not increase.

In this way, even if a synchronizing pulse of the horizontal synchronizing signal is missing or a noise pulse is added to the horizontal synchronizing signal, there is no missing synchronizing pulse, and the horizontal synchronizing signal is the same as the horizontal synchronizing signal without noise pulses. A synchronization correction circuit that can obtain a horizontal synchronization signal can be provided. Therefore, by using this synchronization correction circuit, it is possible to prevent erroneous control of the circuit controlled based on the number of pulses of the horizontal synchronization signal. In this embodiment, the horizontal synchronization period is set at the "L" level, but the same effect can be obtained even if it is set at the "H" level.

[0024]

Effects of the Invention As described in detail above, according to the present invention, when a synchronization pulse is missing in the horizontal synchronization signal or when an abnormal pulse is added to the horizontal synchronization signal, it is corrected and the number of pulses is increased. Therefore, it is possible to provide a synchronization correction circuit that can obtain a horizontal synchronization signal with a constant value. Therefore, when this synchronization correction circuit is used, an excellent effect can be obtained in which the displayed image is not adversely affected even if the number of pulses of the horizontal synchronization signal changes.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a synchronization correction circuit according to the present invention.

FIG. 2 is a timing chart of a composite image signal and each part signal.

FIG. 3 is a timing chart of various signals when a synchronization pulse is missing.

FIG. 4 is a timing chart of various signals when a noise pulse is added.

FIG. 5 is a block diagram showing the configuration of a conventional synchronization correction circuit.

FIG. 6 is a timing chart of signals of each part of the synchronization correction circuit in FIG. 5;

[Explanation of symbols]

1 Counter circuit 2
3-input NOR circuit 3, 4, 5
,6 NOR circuit

Claims (1)

[Claims] 1. In a synchronization correction circuit that corrects a horizontal synchronization signal in a composite image signal, a first time period is measured that is shorter than the time from the end of a horizontal synchronization period of the horizontal synchronization signal to the start of the next horizontal synchronization period. a second time period longer than the time from the end of the horizontal synchronization period of the horizontal synchronization signal to the start of the next horizontal synchronization period; and the first time period from the end of the horizontal synchronization period of the horizontal synchronization signal. pulse removing means for removing pulses generated during the period in which the second time is being counted; and pulse adding means for adding a pulse when there is no synchronizing pulse in the period in which the second time is being counted from the end of the horizontal synchronizing period. A synchronization correction circuit comprising: