JPH0243876A - Synchronizing signal circuit for color television set - Google Patents

Abstract

PURPOSE:To stably obtain a synchronizing signal by providing a signal width measurement circuit and an interval measurement circuit with respect to each synchronizing signal and extracting a signal satisfying the condition being within a prescribed value by each circuit simultaneously as a horizontal/vertical synchronizing signal. CONSTITUTION:A synchronizing separator circuit 11 comprising frequency separation means or the like separates and extracts a horizontal synchronizing signal and a vertical synchronizing signal and the width of each synchronizing signal is measured by measurement circuit 21, 22 respectively. If the width is shorter than or longer than the prescribed width, the signal is disregarded as not being the normal synchronizing signal. Then the interval of each synchronizing signal is measured by measurement circuits 31, 32, and if the interval narrower than or wider than the prescribed interval, the signal is eliminated. Thus, the horizontal synchronizing signal and the vertical synchronizing signal with the correct signal width and the regular signal interval are obtained at output terminals 41, 42 and even if the state of the reception signal is changed, the synchronizing signals and the chrominance signals are obtained stably.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a synchronization signal circuit for color television that can stably obtain synchronization signals and color signals. The purpose is to provide a circuit for separating and extracting synchronizing signals that can stably obtain a horizontal synchronizing signal/vertical synchronizing signal separating circuit for the signal of the receiving composite video signal terminal, and a signal width measurement for each synchronizing signal. The apparatus includes a circuit and an interval measuring circuit for each synchronizing signal, and each circuit extracts, as horizontal and vertical synchronizing signals, signals that simultaneously satisfy the respective predetermined values.

[Industrial Field of Application] The present invention relates to a synchronization signal circuit for color television that can stably obtain synchronization signals and color signals.

Circuits for extracting synchronization signals in conventional color television receivers tend to malfunction when the input signal state changes due to noise. Therefore, it has been desired to develop a technique for stably obtaining a synchronization signal even when the input signal condition is poor.

[Prior Art] In a color television receiver, when obtaining a horizontal synchronization signal and a vertical synchronization signal, processing as shown in the waveform diagram of FIG. 7 is performed. FIG. 7A shows a signal waveform including a synchronization signal and a luminance signal, and the composite synchronization signal is separated by a slice level SL. The obtained waveform is shown in FIG. 7B. The waveform shown in FIG. 7B is sliced through a differentiating circuit and only the falling portion of the waveform is extracted to obtain the horizontal synchronizing signal shown in FIG. 7C. At this time, when there is noise in the input signal, the waveform is differentiated to obtain an output similar to a regular synchronization signal.

Next, it passes through an integration circuit to obtain a vertical synchronization signal. In addition, in order to obtain the color burst gate signal required in the color synchronization circuit, this gate signal is generated from the horizontal synchronization signal which has been synchronously separated.

[Problems to be Solved by the Invention] Since the above-mentioned synchronization signals, especially the horizontal synchronization signals, are separated by a differentiating circuit, malfunctions are likely to occur due to changes in the input signal state such as noise being mixed into the received signal. Furthermore, since the slice level fluctuates minutely, it is not possible to perform separation so that the synchronization signal rises at the same time for each scanning line. When punching out a color burst signal, if the generation of the horizontal synchronization signal, which is the basis of the color burst gate signal, is disturbed, the reproduction of the color signal naturally becomes defective.

The purpose of the present invention is to improve the above-mentioned drawbacks and to provide a circuit for separating and extracting the synchronization signal so that the synchronization signal and color signal can be stably obtained even when the state of the received signal changes. .

[Means for Solving the Problems] FIG. 1 is a diagram showing the basic configuration of the present invention. In FIG. 1, 10 is a composite video signal input terminal, 11 is a horizontal synchronization signal/vertical synchronization signal separation circuit, 21 is a horizontal synchronization signal signal width measurement circuit, 22 is a vertical synchronization signal signal width measurement circuit, 3
Reference numeral 1 denotes a signal interval measurement circuit for horizontal synchronization signals, 32 a signal interval measurement circuit for vertical synchronization signals, 41 an output terminal for horizontal synchronization signals, and 42 a signal interval measurement circuit for vertical synchronization signals.

The present invention has the following configuration. That is, a horizontal synchronization signal/vertical signal synchronization signal separation circuit 11 for the signal of the received composite video signal terminal 10, a signal width measurement circuit 21, 22 for each synchronization signal, and an interval measurement circuit 31 for each synchronization signal.
．． 32, and each circuit extracts, as a horizontal and vertical synchronizing signal, a signal that satisfies the respective predetermined values or less at the same time.

FIG. 2 is a diagram showing the configuration of another invention, in which numeral 43 indicates a color signal carrier gate signal terminal, 50 a PLL circuit, and 60 a clock counting circuit. The structure of the other invention is as follows.

a PLL circuit that generates a clock synchronized with a color signal carrier obtained by frequency-separating the received composite video signal;
and a counting circuit that counts clocks output from the L circuit,
The objective is to obtain a horizontal synchronization signal, a vertical synchronization signal, and a color signal carrier gate signal from the counting circuit.

[Operations] As shown in Fig. 1, the received composite video signal is processed by a synchronization separation circuit 11 using frequency separation means or the like to separate the horizontal synchronization signal and
Separate and extract the vertical sync signal.

Next, the width of each synchronizing signal is measured in measuring circuits 21 and 22. Those that are extremely shorter or longer than the predetermined width are considered not to be regular synchronization signals and are removed. Next, the circuit 31.3 measures the interval between each synchronization signal.
Measure at 2.

At this time, too, extremely narrow or wide spaces are removed compared to the predetermined spacing. As a result, horizontal synchronization signals and vertical synchronization signals having regular signal widths and regular signal intervals are obtained at the output terminals 41 and 42.

Next, in the configuration shown in FIG. 2, a color signal carrier wave is extracted from the received composite video signal by frequency separation, and a clock synchronized with the color signal carrier wave is generated in a PLL circuit 50. By applying this clock to the counting circuit 60 and counting, a horizontal synchronizing signal, a vertical synchronizing signal, and a color signal carrier gate signal can be obtained from terminals 41, 42, and 43, respectively.

[Embodiment] FIG. 3 is a diagram showing a signal width measuring circuit and an interval measuring circuit for synchronizing signals as an embodiment of the present invention, and FIG. 4 mainly shows a waveform diagram of the horizontal synchronizing signal in FIG. 3. There is. In FIG. 3, 22. ．． 24 is an amplifier down counter; 23.
25 is a clock pulse generator, 26.27 is a differentiation circuit,
32.34 is a clock counter, 33.35 is a clock pulse generator, 36.37 is a counter value decoder, 38
39 indicates a gate.

The case of extracting an accurate horizontal synchronization signal will be explained with reference to FIG. A horizontal synchronizing signal and a vertical synchronizing signal separated by known frequency separation or the like are separately applied to count designation terminals of up/down counters 22 and 24. Each clock pulse is input to the counter 2224 and counted. Clock pulse generator 23.25
The oscillation frequency of is set high enough to distinguish between long and short synchronization signal widths. The counters 22 and 24 are designed such that, for example, when the synchronization signal is "H", the counters count down, and when the synchronization signal is "L", the counters count up.
The count is configured to stop when the count reaches "0" or all "1".

Therefore, the counter 22 starts counting clocks when the synchronization signal arrives, as shown in FIG. 4B. Before the synchronization signal of a predetermined width rises (before the synchronization signal disappears), the counter 22
It is shown that the counter 22 detects when all "1" and when all "0" are reached, and outputs from the counter 22 during that time. Therefore, the time during which the output is generated approximately corresponds to the width of the synchronizing signal. In addition, since the count value of the counter 22 does not reach all "1" due to the short width of the noise, the fourth
The output will not be as shown in Figure C.

Next, differentiation at the rising edge of the output shown in FIG. 4C, which is recognized as a synchronizing signal, is performed in differentiating circuits 26 and 27 shown in FIG. The fourth diagram shows the differential circuit output. The output of the differentiating circuit 26 is applied to the gate 38, and the gate 38 outputs only a predetermined horizontal synchronizing signal to the terminal 41. The counter 32 is reset at the falling edge of the output. Figure 4E
As shown in FIG. 3, the counter 32, which has been reset by the differential output corresponding to the predetermined synchronizing signal, starts counting 1.2- again. Then, counting is continued until near the end of the time corresponding to the interval at which the synchronizing signal arrives, and when the maximum count value, for example m, has been counted, that value is decoded by the decoder 36. Control of the gate 38 is started according to the decoded value, and the synchronization signal effective range shown in FIG. 4F is started.

Next, for example, when the count value 2 is decoded, the effective range ends. Only the differential circuit output within the synchronizing signal effective range shown in FIG. 4F is taken out to the terminal 41 and becomes the signal shown in FIG. 4G, so this signal is taken as a regular horizontal synchronizing signal. The vertical synchronization signal at terminal 42 is also obtained by a similar operation.

FIG. 5 is a diagram showing an embodiment of another invention. In FIG. 5, 51 is a 3.58 M I (z band pass filter), 52 is a phase detection circuit, 53 is a low pass filter, and 54 is a crystal oscillation circuit that can finely change the oscillation frequency. 52, 53, and 54 constitute a known PLL circuit. 61 is a horizontal period counter, and 62 is a vertical period counter.

A color burst signal (color signal carrier wave) is extracted from the composite video signal by a filter 51, and then the phases of the color burst signal and the oscillation circuit 54 are synchronized in a PLL circuit. On the other hand, the following relationship exists between the color burst signal frequency Esc and the horizontal and vertical synchronizing signal frequencies fi and fv.

f o = f sc/227.5 f v = f H/266.5 Therefore, f. If the counters 61 and 62 count a predetermined number using the clock as a clock, the output at that time can be used as a synchronization signal. Once the position of the synchronization signal is determined by the means shown in Figures 3 and 4, the synchronization signal can be obtained from the stable output of the crystal oscillator circuit without having to extract the synchronization signal from the input video signal. be able to.

The color burst gate signal can also be obtained by decoding the count value of the counter 61.
This signal is also stable.

Next, FIG. 6 is a diagram showing an improved configuration of FIG. 5. In FIG. 6, 55 is a horizontal/vertical synchronization signal separation circuit that uses a frequency separation circuit, etc., and 56.57 is a phase detection circuit that detects the horizontal/vertical synchronization signal output from the separation circuit 55 and the horizontal period counter 61. - Something that detects the phase difference with the synchronization signal equivalent count output of the vertical period counter 62, 5
8 is an error detection circuit, and when there is an error of more than a predetermined value in the output of each phase detection circuit 56, 57, a counter 6162
to be reset. With this circuit, the synchronous signal separation circuit 5
If the output of the PLL circuit is fixed by the output of the counter 5, the outputs of the counters 61 and 62 can be used as horizontal/vertical synchronizing signals and color burst gate signals as long as the output of the error detection circuit does not occur.

[Effects of the Invention] In this way, according to the present invention, the in-vehicle TV/ship T
Even when used in a noisy place such as V, or when conventional synchronization signal circuits cannot properly synchronize due to large changes in reception conditions, it is possible to obtain synchronization signals extremely stably. Color signals can be extracted accurately. It is also effective when performing video signal processing, such as when storing or reading video signals in a memory, because a very accurate synchronization signal is obtained.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the principle configuration of the present invention, Figure 2 is a diagram showing the configuration of another invention, Figure 3 is a diagram showing the configuration of an embodiment of the invention in Figure 1, and Figure 4 is a diagram showing the configuration of an embodiment of the invention. 3 is an operation waveform diagram, FIGS. 5 and 6 are diagrams showing the configuration of an embodiment of the invention of FIG. 2, and FIG. 7 is an operation explanatory diagram of a conventional synchronization signal circuit. 10--Receiving composite video signal terminal 11--Horizontal/vertical synchronizing signal separation circuit 21.22-m
- Signal width measurement circuit 31, 32 - Interval measurement circuit 41 - Horizontal synchronization signal output terminal 42 - Vertical synchronization signal output terminal Patent applicant Fujitsu Limited Agent Patent attorney Eisuke Suzuki

Claims (1)

[Claims] I. A horizontal synchronization signal/vertical synchronization signal separation circuit (11) for the signal of the received composite video signal terminal (10), and a signal width measurement circuit (21) (22) for each synchronization signal, each For color television, comprising interval measuring circuits (31) and (32) for synchronizing signals, and each circuit extracting signals that simultaneously satisfy respective predetermined values as horizontal and vertical synchronizing signals. Synchronous signal circuit. II, a PLL circuit that generates a clock synchronized with a color signal carrier obtained by frequency separation from a received composite video signal, and a counting circuit that counts the clock output from the PLL circuit. A synchronization signal circuit for color television, characterized in that it obtains a vertical synchronization signal and a color signal carrier gate signal. III. The horizontal and vertical synchronization signals obtained with the configuration described in claim II and the horizontal and vertical synchronization signals obtained directly by separating the horizontal and vertical synchronization signals from the received composite video signal. A synchronization signal circuit for a color television, comprising a phase difference detection circuit for detecting a phase difference, and controlling generation of the horizontal and vertical synchronization signals according to claim 2 by the output of the phase difference detection circuit.