JP2775801B2 - Video signal processing circuit - Google Patents

Description

The present invention relates to a clamp circuit to which a video signal is input, a low-pass filter to which an output of the clamp circuit is input, and a video signal to which an output of the low-pass filter is input. The present invention relates to a video signal processing circuit including a synchronization signal separation circuit for detecting a synchronization signal from the inside, wherein the clamp circuit clamps a video signal while a synchronization signal is input from the synchronization signal separation circuit.

[Conventional technology]

Conventionally, for example, a home video magnetic recording / reproducing device (hereinafter, VTR)
In the video signal processing circuit, the leading end of a horizontal synchronizing signal in the video signal (hereinafter, abbreviated as a sync chip) during recording and reproduction so that the luminance level of the video signal does not fluctuate during recording and reproduction. Is clamped to a predetermined DC potential.

FIG. 4 is a block diagram showing a conventional example of this kind of video signal processing circuit, and FIG. 5 is a timing chart showing the operation of the conventional example of FIG.

The video signal or the FM-modulated video signal S ₀ is subjected to predetermined processing by the signal processing circuit 1 and is output to the clamp circuit 2 as the video signal S ₁ . The output S ₂ of the clamp circuit 2 is
Low-pass filter 4 through the (hereinafter abbreviated as LPF 4), the output signal S ₃ as output to the synchronizing signal separation circuit 5, the synchronizing signal separation circuit 5 sync signal pulse train that is synchronized with the synchronizing signal portion of the video signal input S Output as ₄ . Synchronizing signal S ₄ of the synchronizing signal separation circuit 5 gives the operating point for the clamping operation with respect to the clamp circuit 2. That is, a period in the synchronization signal S ₄ is input to the control input of the clamp circuit 2 clamps the DC potential clamp circuit 2 is set in advance the video signal input. Therefore, a signal in which the sync tip level of the video signal is clamped to a predetermined DC potential is output from the clamp circuit 2.

The operation of the conventional example shown in FIG. 4 will be described with reference to FIG.

Synchronizing signal separation circuit 5 compares the comparison value V _TH of the synchronizing signal portion of the delayed video signal which is an output signal S ₃ of the LPF 4, the period in which the DC potential of the output signal S ₃ is less than the comparison value V _TH outputs a synchronization signal S _4. Period the synchronization signal S ₄ is output, the clamp circuit 2 clamps the predetermined V _C becomes DC potential input video signal as the output signal S _2.
The output of the clamp circuit 2 is input to the signal processing circuit 3 in the next stage. Here, in the case of a VTR, at the time of recording, a recording video signal is input to the signal processing circuit 1 and the signal processing circuit 1
For example, a luminance signal and a chrominance signal are separated, and the signal processing circuit 3 performs emphasis processing, FM modulation processing, and the like. On the other hand, during playback, the FM-modulated video signal
The signal is input to the signal processing circuit 1 and FM demodulation processing and the like are performed. In the signal processing circuit 3, de-emphasis processing and the like are performed. As described above, in the conventional example, the level of the luminance signal during recording and reproduction in the VTR does not fluctuate.
It has a function of clamping the sync tip level in each video signal to the same DC potential.

[Problems to be solved by the invention]

The above-described conventional video signal processing circuit is designed to stably generate a synchronization signal by the synchronization signal separation circuit 5.
The LPF4 before slicing the comparison value V _TH of the synchronizing signal portion of the video signal, and delays the video signal. Therefore, as shown in FIG. 5, the synchronizing signal of the synchronizing signal separating circuit 5 is also delayed. As a result, the clamp circuit 2 clamps not only the sync tip in the input video signal but also a part of the back porch. Also clamps, damaging the video signal. In the case of a VTR, a color subcarrier reference signal (color burst signal) is superimposed on the back porch in the post-processing of the circuit of FIG. There is a disadvantage that the signal cannot be reproduced.

[Means for solving the problem]

A video signal processing circuit according to the present invention includes: a high-pass filter that differentiates an output of a clamp circuit; a comparator that receives an output of the clamp circuit as an input while the synchronous signal separation circuit outputs a synchronous signal; A pulse generation circuit that outputs a one-shot pulse of a preset pulse width in synchronization with the output, and outputs the synchronization signal of the synchronization signal separation circuit to the clamp circuit only while the pulse generator does not output the one-shot pulse. A switching circuit.

[Action]

The comparator compares only the differential output of the high-pass filter that is output while the synchronization signal separation circuit is outputting the synchronization signal, and the pulse output circuit outputs a one-shot pulse based on the comparison output. However, when the one-shot pulse is output, the switch circuit does not cause the clamp circuit to perform the clamp operation.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the video signal processing circuit of the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment of FIG.

This embodiment is different from the conventional example shown in FIG.
(Hereinafter referred to as HPF6), a comparator 7, and a switch circuit 8
And a pulse generation circuit 9.

The HPF 6 outputs a differential output of the output of the clamp circuit 2.
The comparator 7 outputs the HPF6 during the period when the synchronization signal is output.
Outputs the derivative output of. The pulse generation circuit 9 includes a comparator 7
And outputs a one-shot pulse of a predetermined width in accordance with the comparison output from. Switch circuit 8 is when the pulse generating circuit 9 does not enter the one-shot pulse outputs a synchronization signal S ₄ to the clamp circuit 2, while they enter the one-shot pulse output of the synchronization signal S ₄ Stop.

Next, the operation of the embodiment of FIG. 1 will be described with reference to FIG.

HPF6 outputs the output signal S ₅ by differentiating the rising of the output signals S ₁ of the signal processing circuit 1, the fall. The comparator 7 outputs the output signal
Of S _5, comparison value V in a period of the synchronization signal S ₄ is outputted
Detecting the above signal _THL outputs the output signal S _6. When the output signal S ₆ is output, the pulse generator 9 outputs the output signal S ₇ of pulse width W. The switch circuit 8 outputs the output signal S ₇
There while being output does not output the sync signal S ₄ to the clamp circuit 2 can not perform the clamping operation range according to the back porch period of the input signal S ₀ with respect to the clamp circuit 2.

 FIG. 3 is a block diagram showing a second embodiment of the present invention.

During recording, the switch circuit 17 of the signal processing circuit 1
The C circuit 10 and the Y / C separation circuit 11 are selected, and at the time of reproduction, the limiter circuit 12, the FM demodulation circuit 13, and the main de-emphasis 14 are selected. The switch circuit 27 of the signal processing circuit 3 has a non-linear emphasis 18, a main emphasis 19,
A white / dark clip 20, an FM modulation circuit 21 is selected, and a non-linear deemphasis 22, a noise canceller 23, and a Y / C mix 24 are selected during reproduction. Therefore, the same clamp circuit 2 is used in both modes by the switch circuits 17 and 27.
Can be used.

〔The invention's effect〕

As described above, the present invention provides a clamp circuit that clamps a sync tip level in a video signal to a predetermined DC potential with a synchronization signal delayed with respect to a synchronization signal portion of an input video signal. The trailing edge of the synchronization signal is detected, a gate pulse is generated by this detection output, and the clamp operation of the clamp circuit is stopped by this gate pulse output during this period, thereby clamping the back porch of the video signal without damaging it. There is an effect that the operation can be realized. Therefore, not only does the level fluctuation of the luminance signal be prevented, but in the case of, for example, a VTR, there is no effect on the color burst signal superimposed on the back porch as post-processing. It should be noted that the present invention can provide the same effect not only in video signal processing in a VTR but also in other video fields.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of a video signal processing circuit of the present invention, FIG. 2 is a timing chart showing the operation of the embodiment of FIG. 1, and FIG. FIG. 4 is a block diagram showing a conventional example, and FIG. 5 is a timing chart showing the operation of the conventional example shown in FIG. 1,3 ... signal processing circuit, 2 ... clamp circuit, 4 ... LPF, 5 ... synchronous signal separation circuit, 6 ... HPF, 7 ... comparator, 8,17,27 ... switch circuit, 9 …… Pulse generation circuit, 10 …… AGC circuit, 11 …… Y / C separation circuit, 12 …… Limiter circuit, 13 …… FM demodulation circuit, 14 …… Main de-emphasis circuit, 15,26 …… Reproduction system signal Processing circuit, 16,25 Recording signal processing circuit, 18 Non-linear emphasis circuit, 19 Main emphasis circuit, 20 White dark clipping circuit, 21 FM modulation circuit, 22 Non-linear de-emphasis circuit , 23 ... Noise canceller circuit, 24 ... Y / C mix circuit.

Claims (1)

(57) [Claims] 1. A clamp circuit to which a video signal is inputted, a low-pass filter to which an output of the clamp circuit is inputted, and a synchronizing signal separating circuit which receives an output of the low-pass filter as input and detects a synchronizing signal from the video signal. A video signal processing circuit that clamps a video signal while the synchronization signal is being input from the synchronization signal separation circuit; a high-pass filter that differentiates an output of the clamp circuit; A comparator that outputs the output of the clamp circuit while outputting the pulse signal; a pulse generation circuit that outputs a one-shot pulse having a preset pulse width in synchronization with the output of the comparator; A switch circuit for outputting the synchronization signal of the synchronization signal separation circuit to the clamp circuit only while the shot pulse is not being output. A video signal processing circuit, characterized in that: