JPS60134590A - Line sequential discriminating circuit - Google Patents

Abstract

PURPOSE:To attain discrimination operation at a predetermined prescribed position by constituting the titled circuit that a discriminating signal is generated based on a pulse synchronized with a horizontal synchronizing signal and whose one horizontal scanning period is ensured. CONSTITUTION:A synchronizing signal separating circuit 58 separates a horizontal synchronizing signal SYN from a composite video signal NTSC. A horizotal scanning period interval converting circuit 59 inputs the signal SYN so as to extract an HD pulse of 1H period and inputs the result to a frequency division circuit 27 having a reset terminal. The circuit 27 inputs the HD pusle and gives 1/2-frequency-division thereto. On the other hand, a line sequential color difference signal LSS comprising color difference signals R-Y and B-Y is inputted to a clamp circuit 22, where the signal is clamped to a prescribed potential. The clamped line sequential chrominance signal is sampled by a sampling circuit 23. When a sampled value is larger than a reference voltage, a reset pulse generating circuit 25 outputs a reset signal to the circuit 27. Thus, the discrimination signal ID corresponding to the line sequential color difference signal is obtained from the circuit 27.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a line-sequential discriminating circuit.
The present invention relates to a circuit useful for determining whether a signal in each horizontal scanning period is one of two types of color signals, for example, R-Y and B-Y color difference signals.

<Prior Art> In France and other countries, a line-sequential television system called the SECAM system has been standardized.

In this SECAM system, there are two color difference signals B-Y.

The subcarriers are alternately switched in each R-Yel horizontal scanning period, and the subcarriers are frequency-modulated with two subcarriers having slightly different frequencies and superimposed on the luminance signal to form a carrier video signal. Therefore, in the demodulation system for the carrier video signal, the color difference signal R-, which is omitted every horizontal scanning period, is delayed by one horizontal scanning period and taken out in parallel with the ratio signal and other signals.
'Y, B-Y'el Color difference signal R-Y before horizontal scanning period
, B-Y to obtain two independent and continuous color difference signals R-Y and B-Ye.

For this reason, the demodulation system is provided with a switch for alternately extracting a signal delayed by one horizontal scanning period and a signal not delayed by one horizontal scanning period. Taking out two types of color signals in parallel in this way is called synchronization, and the switch for this purpose is called a synchronization switch.The synchronization switch in the O3ECAM system is switched as follows. That is, two color difference signals RY,
When obtaining a line sequential signal from B-Y, the frequency of the subcarrier for each horizontal scanning period is different, and the demodulation system determines whether it is a color difference signal R-Y or B-Y based on the frequency difference. This discrimination signal is used to switch the synchronization switch.

When creating a discrimination signal from the frequency difference of subcarriers, conventionally, a burst signal is passed through two narrowband bandpass filters in parallel, and the entire discrimination signal is generated by detecting the magnitude of the filter output. In this case, the band of the bandpass filter must be made as narrow as possible in order to accurately extract each subcarrier wave separately from each other without being affected by noise or the like. However, the narrower the band, the greater the delay in the output of the filter, which causes the problem that the switching timing for synchronization is delayed and one color difference signal is inserted one after another in the middle of one color difference signal. arise.

Such a problem occurs not only in the television system using SECAM, but also in the case where two color difference signals are made line sequential and each color difference signal uses two subcarriers "f: FM modulation system 7" which have slightly different frequencies. Naturally, this problem also occurs when an FM luminance signal is frequency division multiplexed (FDM) obtained by Fpo modulating the main carrier wave with a line-sequential chrominance signal or luminance signal, is recorded on a recording medium, and is then reproduced.

<Object of the Invention> The present invention solves the problems caused by the above-mentioned filtering, and provides line 111 with almost no delay in determination timing.
The purpose of this invention is to provide a next-order discrimination circuit.

<Configuration of the Invention> The configuration of the present invention that achieves this object is such that two types of color signals are alternately selected for each horizontal scanning period and made line sequential, and the potential of the horizontal blanking period after demodulation is set to 2. A discrimination circuit that inputs line-sequential color signals obtained by demodulating signals modulated differently among different types of color signals, and outputs a discrimination signal for the type of color signal, and separates a horizontal synchronization signal. Sync 1
G separation circuit, synchronization (a horizontal scanning period interval conversion circuit that inputs the output pulse of the G separation circuit and extracts a pulse of one horizontal scanning period period), and inputs the pulse output from the horizontal scanning period interval conversion circuit. and a frequency divider circuit that divides the frequency by two, and a discrimination pulse that generates a discrimination pulse so that discrimination information based on the potential during the horizontal blanking period between two types of color signals and the output of the frequency divider circuit have a predetermined correspondence relationship. This is a line sequential discrimination circuit equipped with a pulse generation circuit.

In another configuration, two types of color signals are alternately selected every horizontal scanning period to be line sequential, and the potentials in the horizontal blanking period after demodulation are different between the two types of color signals. A discrimination circuit inputs a line-sequential color signal obtained by demodulating a modulated signal and outputs a discrimination signal corresponding to the type of color signal, comprising a synchronization signal separation circuit for separating a horizontal synchronization signal, and a synchronization signal a horizontal scanning period interval conversion circuit that inputs the output pulse of the separation circuit and extracts a pulse of one horizontal scanning period period;
A frequency dividing circuit that inputs the pulse of the horizontal scanning period interval conversion circuit and divides the frequency by two, and has a reset terminal, and triggers in synchronization with the tie or mink of either the rising or falling edge of the output signal of the frequency dividing circuit. and a clamp pulse generation circuit that outputs a clamp pulse within a horizontal blanking period;
A clamp circuit clamps the demodulated seven-plane sequential color signal to a predetermined potential, and a clamp circuit clamps the clamped line sequential color equalization signal to a horizontal blanking line immediately after the clamped horizontal blanking period at least among each horizontal blanking period. A sampling circuit that performs sampling during the erasing period and compares each sample value with a reference value, and outputs a pulse that resets the frequency dividing circuit when a predetermined condition of whether the sandal value is larger or smaller than the reference value is satisfied. A line sequential discrimination circuit is provided with a reset pulse generation circuit, and obtains the discrimination signal from a frequency dividing circuit.In still another configuration of the present invention, two types of color signals are alternately transmitted every horizontal scanning period. The line-sequential color signal obtained by demodulating the signal that has been selected to line-sequentially and modulated so that the potential of the horizontal blanking period after demodulation is different between the two types of color signals is input, and the line-sequential color signal is input. A discrimination circuit that outputs a discrimination signal corresponding to the type of signal, and includes two sample-and-hold circuits that input demodulated line-sequential color signals, and a complete comparison of the output signals of these two sample-and-hold circuits. a synchronizing signal separation circuit that separates all horizontal synchronizing signals; a horizontal scanning period interval conversion circuit that inputs the output pulses of the synchronizing signal separation circuit and extracts all pulses of one horizontal scanning period; and a horizontal scanning period interval conversion circuit that A frequency dividing circuit that inputs the circuit pulse and divides the frequency by two, and a frequency dividing circuit that is triggered in synchronization with either the rising or falling timing of the output signal of the frequency dividing circuit, and divides one sample within the horizontal blanking period. - Triggered in synchronization with the timing at which the sampling pulse generation circuit outputs the sampling pulse that operates the hold circuit and the rising or falling timing of the output signal of the frequency dividing circuit, whichever is not triggered. , another sampling pulse generation circuit that outputs a sampling pulse for operating the other sampling/holding circuit within a horizontal blanking period, an output signal of the frequency dividing circuit, and an output signal of the comparator. This is a line-sequential discrimination circuit that is equipped with an exclusive OR gate that outputs all the discrimination No. 13.

As can be seen from the above configuration, the present invention can be applied as long as the potential between each horizontal blanking rib in the demodulated line-sequential color signal is different between two types of color signals, and the modulation method is FM modulation. It does not matter whether it is a PM modulation method or a PM modulation method.

Furthermore, the two types of color signals are not limited to R-Y and B-Y color difference signals. Furthermore, the present invention can be applied not only to television systems but also to various recording systems such as VTR1 rotating disc system.

<Effects of the Invention> Since the present invention generates a discrimination signal based on the potential difference in the horizontal blanking period of the demodulated line-sequential color signal, the delay in discrimination timing is reduced compared to the SECAM system using a narrowband bandpass filter. This can be almost ignored, and color signal discrimination can be performed correctly without delay. At this time, in the present invention, a horizontal scanning period interval conversion circuit is provided, and the discrimination is performed based on a pulse that is synchronized with the horizontal synchronization signal and ensures one horizontal scanning period, so that the discrimination position can also be reliably determined. It can be at any desired position. In other words, even if extra pulses occur between horizontal synchronization signals due to dropouts,
This can be cut and a discrimination operation can be performed at a predetermined position.

<Example> The present invention will be fully explained below with reference to the drawings. For reference, Figure 1 shows a simplified example of the configuration of a magnetic recording system using the line sequential method, Figure 2 shows a simplified example of the configuration of its reproduction system, and Figure 3 shows the operation of the synchronization switch. This is shown for reference along with all related signals, and these will be briefly explained in advance. In FIG. 1, as an example, 1 is an input terminal for a bright dust signal Y, 2 is an input terminal for one color signal, e.g., R-Y, 3 is an input terminal for the other color signal, e.g., B-Y, and 4 is an input terminal for a carrier wave. FM modulator of about 7MHz, 5 has a carrier wave of 1.2
MHz FM modulator, 6 is F with a carrier wave of 1.3 MHz.
7 is an M-sequential switch, 8 is an adder circuit, 9 is a recording amplifier, 10 is a recording head, and 11 is an input terminal for a switch control signal. The switch control signal is generated based on a horizontal drive signal (so-called HD pulse') generated at each starting edge of one horizontal scanning period, that is, 1H, and is an on/off signal that repeats rising and falling every 1H, that is, HfH. signal (fn is the horizontal scanning frequency). In Figure 2, 1
2 is a playback head, 13 is a head amplifier, 14 is a bypass filter for separating FM luminance signals, 15 is an FM demodulator, 1
6 is a low-pass filter for FM line sequential color difference signal separation, 1
7 is an FM demodulator, 18 is a 1H delay line, 19 is a simultaneous switch, and 20 is an input terminal for a discrimination signal ID.

Now, the demodulated line sequential color difference signal LSS repeats R-Y and B-Y in the order shown in FIG. -Y
It is assumed that the potential VL of the horizontal blanking period HBLKRY is higher than the potential VL of HBLKRY. 1 liter, the level of discrimination No. 16 ID is shown in Figure 3 (b)
As shown in FIG. 10″ of ID
, the contact 19a of the synchronization switch 19 corresponds to "1".
, 19b, 19c, 19d By turning f on/on, RY and B-Y are separated from each other.
Two continuous color difference signals are obtained. However, the change point of the discrimination signal is the same as the change point during recording.

Next, an embodiment of the present invention will be described with reference to FIG.

In FIG. 4, 21 is the demodulated line-sequential color difference signal LS.
22 is a clamp circuit, 23 is a sampling switch, 24 is an input terminal for sampling pulse SP, 25 is a reset pulse generation circuit, 26 is a reference voltage Vr
The setting terminal 27 of ef is a frequency dividing circuit using a flip-flop F/Fe, and a pulse, for example, an HD pulse, is applied every 1H. 29 is an output terminal of the discrimination number ID, and 30 is a clamp pulse generation circuit using a mono-staple multivibrator M/M.

The operation of the line sequential discrimination circuit shown in FIG. 4 will be explained. now,
As shown in FIG. 5(a), the line sequential color difference signal LSS entering the clamp circuit 22 starts from the R-Y color difference signal, and the R-Y color difference is lower than the potential ML during the horizontal blanking period of No. 1g. Potential VB during horizontal blanking period of B-Y color difference signal
It is assumed that the HD pulse generated during the horizontal blanking period is input to the frequency dividing circuit 27 as shown in FIG. Furthermore, when the first color difference signal R-Yl is input and the first pulse HDI is input, the frequency dividing circuit 27
The output from the ζ terminal happens to be “1” as shown in Figure 5(d).
Assume that the clamp pulse generation circuit 3o is triggered by the output from the rising terminal #. Then, by appropriately selecting the time constant, the clamp pulse generation circuit 30
As shown in FIG. 5(8), a clamp pulse CP1 is output to the Q terminal during the horizontal blanking period. This ensures that the potential of HBLK1 during the first horizontal blanking period becomes the clamp potential vcp. On the other hand, if the sampling pulse SP is given every 1H as shown in FIG. 5(C), the sample value obtained by the first sampling pulse SP1 is the clamp potential Vcp as shown in FIG. 5(f). For simplicity, the reset pulse generation circuit 25 is assumed to output a reset pulse by directly comparing the input terminal with the reference voltage Vref. For example, a reset pulse is output only when Vref < input voltage...Equation (1). Set it to do so. Therefore, by setting the clamp potential so that Vcp (Vref set (2)),
No reset pulse is generated during the first sampling. Therefore, even if the second pulse HDz is input to the frequency dividing circuit 27, the ζ terminal output only falls and no clamp pulse is output. The potential of the next horizontal blanking period HBLK2 is as described above (the potential vn during the horizontal blanking period of B-Y is higher than that of R-
1. The potential is higher than the potential VL during the horizontal blanking period of Y. HBLKt corresponding to the first color difference signal R-Yl
Since HBL was clamped at the clamp potential Vcp, HBL
It becomes higher than the clamp potential Vcp of Kl. Therefore, since the sample value obtained by the second sampling pulse SPz is Vcp + (VH-VL), Vref (Vcp + VH-ML □...Equation (3)
By setting the reference potential Vref' of the reset pulse generation circuit 25 so as to satisfy the following, when the sampling switch 23 is turned on, the reset pulse RP is outputted as shown in FIG. 5(g). . When this reset pulse is output, the four-terminal output of the frequency dividing circuit 27 immediately rises. This causes the second clamp pulse C
P2 occurs and the potential of HBLKz is clamped. Next, even if the third pulse HD3 is input to the frequency dividing circuit 27, the Q
The terminal output only falls and no clamp pulse is output.
I (The potential of BLK3 is not clamped. However, the sample value obtained by the third zumbling pulse SPs is Vcp (VH - VL) because the previous potential of HB LKt was clamped to Vcp. o Vn
)Vr, and from equation (2), Yap −VH+V
t, < Vref Since the equation (4) holds true, no reset pulse is generated this time. Next, the fourth pulse HD
4 is input to the frequency dividing circuit 27, the Q terminal output rises, a clamp pulse CPa is generated, and the potential of HBLK4, which is the BY color difference signal, is clamped. Even if the sampling switch 23 is turned on in this state and the clamp level Vcp is input to the reset pulse generation circuit 25, a reset pulse will not be generated because it is Vcp (Vref). The type and the level of the silk terminal output of the frequency dividing circuit 27 completely correspond to each other after B-Yz. Therefore, the Q terminal output of the frequency dividing circuit 27 shown in FIG. 5(h) is used as the discrimination signal input terminal of FIG. 20, when the first color difference signal is input, the correspondence relationship with the type of color difference signal does not match, and the frequency dividing circuit 27
Regardless of whether the output is "1" or "0#", from 2H onwards, the discrimination signal ID corresponding to the line-sequential color difference signal shown in FIG. Even if a dropout occurs during the process, the discrimination signal ID correctly corresponds to the next color difference signal after 2H of completion of the dropout.

Furthermore, the HD pulse in this embodiment converts the composite video signal NTSC, which is a standard signal of the NTSC system, supplied to the input terminal 57, into a synchronization signal separation circuit 58 and a horizontal scanning period interval conversion circuit (hereinafter referred to as an H rate conversion circuit). abbreviated)
59. At this time, the synchronization signal separation circuit 58 separates the horizontal synchronization signal SYN from the composite video signal NTSC. Further, the H rate conversion circuit 59 inputs the output pulse of the synchronizing signal separation circuit 58 and extracts a pulse having a cycle of one horizontal scanning period, in this embodiment, an HD pulse.

More specifically, the H rate conversion circuit 59 is formed by combining, for example, a flip-flop circuit 59a and a one-shot multivibrator 59b, as shown in FIG.

FIGS. 7(a) to 7(d) are waveform diagrams showing waveforms of each part of this H rate conversion circuit 59. The operation of the H rate conversion circuit 59 will be explained based on FIGS. 7(a) to 7(d). First, the flip-flop circuit 59a
When the horizontal synchronizing signal SYN, which is the output pulse of the synchronizing signal separation circuit 58 as shown in FIG. 7(a), is supplied to the input terminal C of the becomes HI state. On the other hand, the reset terminal R is connected to the resistor R1e
Since it is connected to the output terminal Q through the
As shown in FIG. 2, the voltage gradually increases and reaches the reset voltage after a set time Tl determined by the time constant of the resistor R1 and the capacitor C1. At this point, the flip-flop circuit 59 is reset and the output terminal Q becomes
At the same time as the L, / state is reached, the charge in the capacitor C1 is discharged through the diode Dre, so that the reset terminal R returns to its original state.

Thereafter, the same operation is repeated every time the horizontal synchronization signal SYN is supplied to the input terminal C. At this time, as shown in FIG. (In addition to the issue SYN, its synchronized Lusu Ps+
There are cases where pulse P1, which is noise, is included between rPB2. This occurs due to dropout, etc., but such unnecessary pulse P1 is generated by the H rate conversion circuit 59.
will be removed.

That is, if the set time T+ is set to be a little shorter than the horizontal scanning period 1H, the state of the output terminal Q will not change depending on the pulse Pi. Therefore, the one-shot multivibrator 59b will be triggered by the rising edge of the output terminal Q. If this is done, the HD pulse sent out from the output terminal Q will be completely synchronized with the horizontal synchronizing signal SYN without being affected by noise, and will become a pulse that rises every horizontal scanning period. Incidentally, when the H rate conversion circuit 59i is not passed, the pulse Pl is supplied to the frequency dividing circuit 27, and the synchronization switch 1 is activated at an inappropriate position, such as in the middle of the line sequential color difference signal LSS.
9 will be switched.

Note that the H rate conversion circuit 59 is a non-retriggerable one-shot circuit instead of the flip-flop circuit 59a.
It can also be formed using a multivibrator.

In the explanation of the operation according to the embodiment shown in FIG. 4, the reset pulse generation circuit directly converts the input sample value to the reference potential Vre.
f and output a reset pulse when formula (1) holds, formula (2) and formula (
However, if we use the input voltage (Vref...Equation (5)) as the condition for generating the reset pulse instead of Equation (1), we can set it so that , the relationship between the 4-terminal output of the frequency divider circuit 27 and the type of color difference signal is simply reversed from the previous explanation.Furthermore, even if the setting of the magnitude relationship of the potentials in each horizontal blanking period is reversed, The relationship between the q terminal output of the frequency dividing circuit 27 and the type of color difference signal is simply reversed from the previous explanation.Furthermore, it is not always necessary to directly compare the sample value with the 1 to 1 digit; Because amplifiers etc. are inserted in the middle,
A voltage or current proportional to the sample value is often compared with a reference value.An example of this case (il-8
This will be explained with reference to FIG. In addition, the clamp pulse CP
It only needs to appear during the horizontal blanking period, so the Q of the frequency divider circuit 27
The clamp pulse generation circuit 30 may be triggered in synchronization with the falling timing of the terminal output.Furthermore, the clamp pulse generation circuit 30 may be triggered by the Q terminal output instead of the calculation terminal output of the frequency dividing circuit 27. Discrimination signal ID=e from Q terminal
It is also possible to output it.

In FIG. 8, a differential amplifier 31, a changeover switch 32,
A reset pulse generation circuit 25 is constituted by a constant current circuit 33, a current mirror circuit 34, a comparator 35, and a current detection resistor R. The rest is the same as the circuit shown in FIG.

The operation will be explained with reference to FIG. However, when comparing FIG. 9 with FIG. 5, the waveform of FIG. 9(f) is the same as that of FIG.
), and for the sake of simplicity, the other two figures (a) are each other, (b) are each other, (c) are each other, (
d) between each other, (e) between each other, (g) between each other, and (h) between each other. In other words, VH>V
Suppose that the Q terminal output of the frequency divider circuit 27 rises to 11 when the color difference signal of R Yl is inputted. Therefore, the potential of HBLK1 during the first horizontal blanking period is clamped to vCp. On the other hand, the sampled signal is applied to the input terminal of the differential amplifier 31. The output of the differential amplifier 31 is applied to one contact A of a changeover switch 32, and is supplied to a current mirror circuit 34 through this switch 32 only during the sampling period. A constant current circuit 33 is connected to the other contact B of the changeover switch 32, and the constant current circuit 33 is connected to a current mirror circuit 34 except during the sampling period. The comparator 35 has a voltage E between the terminals of a resistor connected to the output of the current mirror circuit 34.
R is given and compared in magnitude with a reference voltage Vref. V
When the voltage ER caused by the resistor R is smaller than ref, the comparator 35 outputs a reset pulse RP.

By the way, even if a constant voltage Eb'e is applied to the other input terminal of the differential amplifier 31, and the lamp voltage Vcp is sampled and input, the current mirror is slightly smaller than the constant current circuit 33, but almost the same. Current can be drawn from the circuit 34. Therefore, even if the potential of HBLKI clamped by the first clamp pulse CPl is sampled, the voltage ER between the terminals of the resistor R hardly decreases, and the bias voltage Eb and the reference voltage are The voltage Vref' is selected in advance. As a result, no reset pulse is generated. Therefore, even if the second pulse HD2 is input to the frequency dividing circuit 27, the clamp pulse does not start. Therefore, the sample value Vcp+(VH-
Furthermore, the bias voltage Eb and reference voltage Vref' are selected so that when Vt, ) is applied to the differential amplifier 31, the output current decreases significantly and the voltage ER between the terminals of the resistor R becomes sufficiently smaller than Vref. . In this way gb,
If Vref 'c is selected, a reset pulse is generated at the second sampling, and the potential of HBLK2 is clamped. Next, the third Norculus HDs is the frequency divider circuit 27.
Even if it enters the current state, the Q terminal output will fall, so it will not be clamped. Also, the magnetic potential of HBLKs is Vcp-(Vn-VL,
), so Seratonokurusu doesn't appear either.

When the fourth pulse HD4 enters the frequency dividing circuit 27, HBL
Since the potential of K4 is clamped, no reset pulse is generated. The same applies thereafter, and the Q terminal output or Q terminal output of the frequency divider circuit 27 can be used as the discrimination signal ID.0 Note that the current mirror circuit 34 is used to expand the dynamic range, so it is basically unnecessary. Also, in this embodiment, as in the embodiment shown in FIG. 4, the HD pulse is obtained as the output signal of the H rate conversion circuit 59. Shown below.

In FIG. 10, the transistor 36.degree. 41 and the capacitor 48 constitute a clamp circuit 221c. The transistor 39 corresponds to the sampling switch 23, and the transistor 39 and the transistor 40 are turned on and off in opposite directions and correspond to the changeover switch 32. Furthermore, transistor 4
1 and transistor 42 constitute a differential amplifier 31, and transistors 44 and 45 constitute a current mirror circuit 34. The three resistors 46, 47.degree. 38 provide the differential amplifier 31 with an appropriate bias voltage Eb. In addition, -
For example, the constant current circuit 33 flows 2 mA, the current detection resistor R is 2Ω, and the voltage ER between the terminals of this resistor R is 2 V at the second sampling from the steady state of 4 V.
It is supposed to go down. In FIG. 8, a capacitor 48 is for DC regeneration.

The sampling pulse can also be generated at a timing opposite to that of the clamp pulse generation circuit 30. For example, if a clamp pulse is generated at the rising edge of the output signal of the frequency dividing circuit 27, a sampling pulse may be generated at the falling edge of the same signal.

An example of such an embodiment is shown in FIG. 11. In FIG.
is a clamp circuit, 23 is a sampling switch, 25 is a reset pulse generation circuit, 27 is a frequency dividing circuit, 29 is an output terminal for the discrimination signal ID, 30 is a clamp pulse generation circuit,
49 is a sampling pulse generation circuit. The clamp pulse generation circuit 30 uses a monostaple multivibrator that is triggered by the rising edge of the Q terminal output of the frequency dividing circuit 27, while the sampling pulse generating circuit 49 uses a monostaple multivibrator that is triggered by the falling edge of the Q terminal output of the frequency dividing circuit 27. A monostaple multivibrator is used. Of course, it is equivalent to use a monostaple multivibrator that is triggered by the rising edge of the Q terminal output of the frequency dividing circuit 27. Note that the sampling pulse must not be so wide as to exceed the horizontal blanking period. sampling switch 23
The reset pulse RPk can be obtained by simply comparing the output level when the sampling switch 23 is turned on by the comparator 35 with the reference voltage Vref. Other points of circuit operation are similar to those shown in FIGS. 4, 8, and 10. In particular, the HD pulse also has the same H rate = switching circuit 5.
It is obtained as the output signal of 9. FIG. 12 shows operational waveforms of the reporting unit shown in FIG. 11.

Each of the embodiments shown in FIGS. 4, 8, 10, and 11 described above directly or indirectly compares the potential in the horizontal blanking period immediately after the clamped horizontal # line erasing period with a reference value. By doing so, the type of color difference signal is determined. This method has the advantage that by clamping the potential during the horizontal blanking period immediately before the determination, extremely accurate determination can be made regardless of the picture pattern.

Of course, since the discrimination is performed using the potential during the horizontal blanking period, it can be said that there is almost no delay in the discrimination compared to the case where discrimination is performed based on the frequency difference using a filter.

'Next, a description will be given of an invention in which a vehicle is discriminated based on a color signal without clamping, with reference to FIGS. 13, 14, and 15.

FIG. 13 shows a line sequential discrimination circuit according to one embodiment. In the figure, 21 is an input terminal for the line sequential color difference signal LSS, 50 and 51
52 is a frequency dividing circuit that divides the frequency of the input pulse by two; 53 and 54 are sampling pulse generating circuits; 55 is a comparator; and 56 is an exclusive OR gate. The hold time of the two sample and hold circuits 53 and 54 is set to 2H.The zero frequency divider circuit 52 does not require a reset function, and simply dividing the frequency by two is sufficient.

The two sampling pulse generating circuits 53 and 54 generate sampling pulses SPa alternately every 1H within each horizontal blanking period.

spb', and here uses a rising trigger monostable multivibrator and a falling retrigger monostable multivibrator, both of which are triggered by the q terminal output of the frequency dividing circuit 52. Now, assuming that the line-sequential color difference signal LSS and the four-terminal output of the frequency dividing circuit 52 have the correspondence relationship shown in FIGS. 14(a) and (b), the two sampling pulses SPa,
SPb ト4'! The correspondence relationship with the sequential color difference signal LSS is as shown in FIG. 4(c) and (d). According to this sampling, if the potential VLO on the R-Y side is lower than the potential VH on the B-Y side, the lower voltage on the R-Y side is always input to the positive input terminal of the comparator 55. ,
Conversely, since the higher voltage of BY is always input to the negative input terminal, the output of the comparator 55 is always "0". Therefore, by taking the exclusive OR of the output of the comparator 55 and the four-terminal output of the frequency dividing circuit 52, the first
Obtain the signal shown in Figure 4 (,). On the other hand, line sequential color difference signal LSS
The correspondence relationship between and the Q terminal output of the frequency dividing circuit 52 is shown in FIG.
a).

Let us consider a case where the situation is reversed to that shown in FIG. 15 (a) and (b). In this case, the correspondence relationship between the two sampling pulses SPa and SPb and the line sequential color difference signal LSS is also reversed as shown in FIGS. 15(c) and 15(d).

Therefore, the output of the comparator 55 is always "1". However, if we take the exclusive OR of the output of the comparator 55 and the 4-terminal output of the frequency divider circuit 52, we get FIG. 13 (,),
The correspondence between (a) and (b) in FIG. 14 matches the correspondence between (a) and (b) in FIG. 13. Therefore, instead of the Q terminal output of the 0 frequency divider circuit 52, which can be used as the output all discrimination signal of the exclusive OR gate 56, the Q terminal output may be given to the exclusive OR gate 56, or the sampling pulse generating circuit 53. The same thing can be said if it is given to 54.

In this embodiment as well, the HD pulse is obtained as the output signal of the H rate conversion circuit 59, similar to the embodiment shown in FIG.

[Brief explanation of drawings]

Figure 1 is a simplified configuration diagram of a magnetic recording system shown as an example of the line sequential method, Figure 2 is a simplified configuration diagram of its reproduction system, Figure 3 is an explanatory diagram of the operation of the reporting section in Figure 2, and Figure 4 is a bookmarking diagram. A circuit diagram of one embodiment of the invention, FIG. 5 is an explanatory diagram of the operation of the content section in FIG. 4, FIG. 6 is a circuit diagram extracting the H rate conversion circuit, and FIG.
a) to FIG. 7(d) are waveform diagrams showing the waveforms of each part in FIG. 6, FIG. 8 is a circuit diagram and circuit diagram showing one embodiment of the reset pulse generation circuit, and FIG. 9 is a diagram showing the notification section in FIG. 8. FIG. 10 is a more specific circuit diagram of FIG. 8, FIG. 11 is a circuit diagram of another embodiment, FIG. 12 is an explanatory diagram of the operation of the reporting section,
FIG. 13 is a circuit diagram showing another embodiment of the invention, and FIGS. 14 and 15 are explanatory diagrams of the operation of each part of the 131st part, respectively. In the drawing, 22 is a clamp circuit, 23 is a sampling switch, 25 is a reset pulse generation circuit, 27 is a frequency divider circuit with a reset terminal, 30 is a clamp pulse generation circuit, 31 is a differential amplifier, 32 is a changeover switch, and 33 is a Constant current source, 35 is a comparator, 49 is a sampling pulse generation circuit, 50 and 51 are sample and hold circuits, 52 is a frequency division circuit, 53 and 54 are sampling pulse generation circuits, 55 is a comparator, 56 is an exclusive OR gate , 58 is a synchronization signal separation circuit, and 59 is a horizontal eclipse period interval conversion circuit (H rate conversion circuit).
It is. Patent Applicant Fuji Photo Film Co., Ltd. Agent Patent Attorney Mitsuishi Shibu (and 1 other person)

Claims (5)

[Claims] (1) Two types of color signals are alternately selected every horizontal scanning period to be line sequential, and the potentials during the horizontal blanking period after demodulation are modulated to be different between the two types of color signals. This is a discrimination circuit that inputs a line-sequential color signal obtained by demodulating the signal and outputs a discrimination signal for the type of color signal, and includes a synchronization signal separation circuit that separates a horizontal synchronization signal, and an output pulse of the synchronization signal separation circuit. A horizontal scanning period interval conversion circuit that inputs the pulse and extracts a pulse synchronized with one horizontal scanning period, a frequency dividing circuit that inputs the pulse output from the horizontal scanning period interval conversion circuit and divides the frequency by two, and a two-product type A line sequential discrimination circuit comprising a discrimination pulse generation circuit that generates a discrimination pulse so that discrimination information based on the potential of a horizontal l@ line erasing period between color signals and the output of a frequency dividing circuit have a predetermined correspondence relationship. (2) Two types of color signals are alternately selected and line-sequentialized every horizontal scanning period, and the potentials during the horizontal blanking period after demodulation are modulated to be different between the two types of color signals. A discrimination circuit inputs a line-sequential color signal obtained by demodulating a signal and outputs a discrimination signal corresponding to the type of color signal, and includes a sync signal separation circuit that separates a horizontal sync signal; a horizontal scanning period interval conversion circuit that inputs an output pulse and extracts a pulse of one horizontal scanning period period; a frequency dividing circuit that inputs the pulse of the horizontal scanning period interval conversion circuit and divides the frequency by two, and has a reset terminal; A clamp pulse generation circuit that is triggered in synchronization with either the rising or falling timing of the output signal of the frequency dividing circuit and outputs all two pulses within the horizontal blanking period, and a demodulated line-sequential color signal. A clamp circuit clamps the clamped lines to a predetermined potential, and each horizontal blanking line sequentially outputs the color signal to the clamped line. a sampling circuit that samples in a horizontal R-line blanking period immediately after the clamped horizontal blanking period at least in the previous period; and comparing each sample value with a reference value;
It is equipped with a reset pulse generation circuit that outputs a pulse that resets the frequency dividing circuit when a predetermined condition such as whether the sample value is larger or smaller than a reference value is satisfied, and the frequency dividing circuit obtains the above-mentioned discrimination (IF code). Line sequential discrimination circuit. (3) In claim 2, the reset pulse generation circuit includes a differential amplifier that fully differentially amplifies the output signal of the sampling circuit and a signal at a constant level, and an output signal of the differential amplifier and a signal at a constant level. A line characterized in that it has a switch that alternately selects a signal and a signal at a timing that coincides with a sampling pulse of a sampling circuit, and a comparator that compares an output signal of this switch or a signal proportional to the signal of this output with a reference value. Sequential discrimination circuit. (4) In claim 2, the sampling circuit is synchronized with the sampling switch and with the rising or falling timing of the output signal of the frequency dividing circuit, whichever is the timing at which the clamp pulse generation circuit is not triggered. a sampling pulse generation circuit that outputs a pulse that operates a sampling switch during a horizontal blanking period immediately after a horizontal blanking period that is triggered and clamped; A line sequential discrimination circuit characterized by having a comparator that compares a value with a reference value. (5) Two types of color signals are alternately selected every horizontal scanning period to be line-sequential, and the potentials during the horizontal blanking period after demodulation are different between the color ID codes of the two panicles. A discrimination circuit which inputs a line-sequential color signal obtained by demodulating the modulated I= signal and outputs a discrimination signal corresponding to the line class of the color signal, the circuit receiving the demodulated line-sequential color signal 2. A comparator that compares the magnitude of the output signals of these two sample and hold circuits, a synchronization signal separation circuit that separates the horizontal synchronization signal, and an output pulse of the synchronization signal separation circuit that is input. 1. A horizontal scanning period interval conversion circuit that extracts all pulses of the horizontal scanning period period, a frequency dividing circuit that inputs the pulses of the horizontal scanning period interval conversion circuit and divides the frequency by two, and a rising or falling frequency of the output signal of the frequency dividing circuit. a sampling pulse generation circuit that outputs a sampling pulse that is triggered in synchronization with the timing of one of the two and operates one of the sample-and-hold circuits within the horizontal blanking period; triggered in synchronization with the falling timing at which the sampling pulse generation circuit is not triggered;
Another sampling pulse generation circuit outputs a sampling pulse for operating the other sample-and-hold circuit within a horizontal blanking period, and the output signal of the frequency dividing circuit and the output signal of the comparator are inputted to generate a discrimination signal. A line sequential discriminating circuit comprising an exclusive OR gate that outputs.