JP2531152B2 - Video color signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention provides a single-system color signal in which two-system color signals are time-axis compressed and the two-system color signals are alternately arranged. A video color signal suitable for use in processing the two-system color signal formed on the reproducing side of a video tape recorder (VTR) that is recorded and time-axis-expanded on the reproducing side to form the two-system color signal. It relates to a processing circuit.

[Conventional technology]

2. Description of the Related Art Conventionally, there is known a VTR that records and reproduces a luminance signal and a color signal on different tracks.

FIG. 4 shows an example of such a VTR recording system. In the figure, a luminance signal Y and color difference signals RY and BY which are video signal outputs are recorded.

The high frequency range of the luminance signal Y is emphasized by the pre-emphasis circuit 1 and is FM-modulated by the FM modulator 2 to become an FM luminance signal Y _FM , which is supplied to the rotary magnetic heads H _Y1 and H _Y2 via the amplifier 3. It

On the magnetic tape 4, these heads H _Y1 and H _Y2 are used to make diagonal recording tracks for each field as shown in FIG.
T _Y is formed.

The color-difference signals RY and BY are compressed by the time axis compressor 5 into 1/2 on the time axis, respectively, and as shown in FIG. 6, the RY and BY signals are sequentially arranged within one horizontal section. Be lined up.

This time-compressed color difference signal C is high-frequency emphasized by the pre-emphasis circuit 6 and then FM-modulated by the FM modulator 7, and the FM color-difference signal C _FM is further transmitted via the amplifier 8 to the rotary magnetic heads H _C1 , H. Supplied to _C2 . On the magnetic tape 4, oblique recording tracks T _C are formed for each field by the heads H _C1 and H _C2 as shown in FIG.

Incidentally, P _C represents the horizontal synchronizing pulses in the C of Figure 6.

As shown in FIG. 5, the recorded luminance signal Y and chrominance signals RY and BY are reproduced by the reproducing system in the reverse process of the recording system, but the chrominance signals RY and BY are reproduced. Since the time axis is compressed, the time axis is doubled in the reproducing system.

By the way, the time axis compressor 5 of the recording system shown in FIG.
Charge transfer device (CCD) with capacity for horizontal period (1H)
It is configured by using four. That is, two RY signals are used and two BY signals are used.
The signal and BY signal are alternately input to the first and second CCDs by 1H for every 1H, and 1H is output at 1 / 2H from the output side.
A compressed color difference signal C is formed.

In such a time axis compressor 5, the RY signal and B
-When the characteristics of the first and second CCDs used for each of the -Y signals do not match, the RY signal and the BY signal obtained by time-axis expansion in the reproduction system are each 1H. There is a problem that a level difference occurs and noise including DC offset is mixed and output as a change in hue or brightness in the color demodulation circuit.

Therefore, in order to remove the noise including the DC offset component, conventionally, a comb filter including a delay line 9 having a delay time of 1H and an adder 10 as shown in FIG. 7 is used. It was This adder 10 has the same resistance value of 3
It is configured by connecting a number of resistors in a J-shape and outputs the average of two input signals a and b, (a + b) / 2.

As is well known, the color difference signal has a line correlation. On the other hand, as described above, noise such as DC offset caused by CCD at the time of recording has a frequency component that is an integral multiple of 1/2 of the horizontal frequency f _H , and therefore its phase is inverted every 1 _H.

Therefore, in the adder 10, the input signal A containing noise as shown in FIG. 8A and the output signal B of the 1H delay line 9 as shown in FIG. 8B are The noise including the DC offset is canceled by averaging as shown in FIG.

However, in the period in which there is no correlation between the input signal A and the output signal B, the level of F _r of the output signal of the comb filter is halved by averaging as shown in the waveform C of FIG. , BK, a 1/2 level color signal which does not exist in the input signal A appears.

For this reason, there is a problem that the reproduced image becomes lighter in color, especially at the edges, and color bleeding occurs in the vertical direction of the screen.

In order to solve the above-mentioned problems, the one described in JP-A-61-156993 has been proposed.

The comb filter circuit described in the above publication is shown in FIG.
This will be described with reference to FIG.

The color signal supplied from the input terminal IN is commonly supplied to the 1H delay line 9, the first adder 10 and the subtractor 11, and the output of the delay line 9 is commonly supplied to the adder 10 and the subtractor 11. It

The subtractor 11 has a half of the difference between the two input signals a and b, It is designed to output.

20 designates a clip correlator as a whole, an amplifier 12,
It comprises a clipper 13, a small-amplitude pass correlator 14, and two clamp circuits 15 and 16.

The output signal D having no line correlation from the subtractor 11 is supplied to one input terminal 11a of the clip type correlator 20, passes through the amplifier 12, the clipper 13, and the clamp circuit 15, and then one of the small amplitude pass type correlators 14 is supplied. Is supplied to. Clip correlator 20
The output signal D is supplied to the other input terminal of the through the clamp circuit 16.

The output of the small-amplitude pass correlator 14 and the addition output C of the first adder 10 are supplied to the second adder 18 and the addition output K
Is output to the output terminal OUT.

The operation of the configuration shown in FIG. 9 will be described with reference to FIG.

The color signal A (shown in FIG. 10A) input to the input terminal IN passes through the 1H delay line 9 and is delayed by 1H as shown in FIG. 10B. Therefore, the output C of the first adder 10 is
As shown in FIG.

Further, the signal shown in FIG. 10D obtained by subtracting the signal shown in FIG. 10B from the signal shown in FIG. 10A is output from the subtracter 11 as D.

The output D of the subtractor 11 is amplified by the amplifier 12, and then the clipper
When the low level portion is cut at 13, the signal shown in FIG. 10E is obtained.

The small-amplitude pass correlator 14 correlates the signal shown in FIG. 10E with the signal shown in FIG. 10D and outputs the smaller amplitude to obtain the signal shown in FIG. The output signal J of the small-amplitude pass correlator 14 and the first adder 10 shown in FIG.
The output C of the above can be added by the second adder 18 to obtain the color signal shown in FIG.

As is clear from the signal shown by K in FIG. 10, it can be seen that the color signal from which the noise that the color does not become light and the bleeding does not occur is removed is obtained by the configuration shown in FIG.

However, the one shown in FIG. 9 has analog processing, and since glass or CCD is used as the 1H delay line, there is a problem that linearity, S / N, frequency characteristics, temperature characteristics, etc. change. It was

An invention that solves such a problem has already been filed as Japanese Patent Application No. 61-81619.

 The above invention will be described with reference to FIGS. 11 and 12.

In the configuration shown in FIG. 11, the color signals converted into digital signals in the reproduction system are supplied to the latch circuits 21 and 22.

In the figure, the data R-Y _D from the delay circuit 26 is supplied to one of the switch circuits 30R forming the dropout compensation circuit 23. Output data R of this switch circuit 30R
-Y _D1 is supplied to the shift register 31R forming the 1H delay line, and the output data R-Y _D2 of this shift register 31R is supplied to the other of the switch circuit 30R.

Also, the output data RY _D1 of the switch circuit 30R is the ROM 32
R, for example, supplied to the P-ROM as the upper bits of the address signal, and output data RY of the shift register 31R.
_D2 is supplied to ROM32R as the lower bit of the address signal.

In this case, the output data R-Y _D1 and R-Y _D2 are stored at the address of the ROM 32R specified by the output data R-Y _D1 and R-Y _D2.
When there is a correlation with, the data {(R−Y _D1 ) + (R−Y _D2 )} / 2 = R−Y _D12 is stored, and when there is no correlation, the data R−Y
_D1 is remembered.

The output data of the ROM 32R is latched by the latch circuit 33R and supplied to the D / A converter 24.

A dropout pulse generator (not shown) supplies the switch circuit 30R with a dropout pulse D _P when there is a dropout in the color signal, and the shift register 31R and the latch circuit 33R receive a clock 1 / 2R · C from the reference clock.
K'is supplied.

In the above configuration, when the dropout pulse D _P is not supplied to the switch circuit 30R, the current data R-Y _D is output as the output data R-Y _D1 of the switch circuit 30R, and the dropout pulse D _P is output. When supplied, the output data RY _D1 of the switch circuit 30R is 1H.
The previous data R-Y _D2 is output and the dropout is compensated.

Also, from the ROM32R, data is read from the address designated by the output data R-Y _D1 and the shift register 31R output data R-Y _D2 of the switching circuit 30R. That is, when there is a correlation between the output data R-Y _D1 and R-Y _D2 , {(R-Y _D1 ) + (R-Y _D2 )} / 2 = R-Y _D12 is read. This data is the average of the current data R-Y _D1 and the data R-Y _D2 1H before.

When there is no correlation between the output data R-Y _D1 and the output data R-Y _D2 , the data R-Y _D1 is read. This data is the current data.

For example, the output data R-Y _D1 of the switch circuit 30R is the 12th
As shown in the figure, it changes with time (A in the figure shows its analog waveform), while the output data RY _{D2 of the} shift register 31R.
When it changes with time as shown in FIG. 4D (C shows its analog waveform), the output data of the ROM 32R changes with time as shown in FIG. In this example, the data RY _D1 is [1111110
1], when the data RY _D2 is [11111111], there is a correlation, and the data of the average value of both data [1111111]
0] is output.

Further, in FIG. 11, also a system of data B-Y _D are configured similarly to the shape of the data R-Y _D described above, the same applies to the operation.

Therefore, according to the configuration of FIG. 11, the correlation is digitally uniformly determined by the ROMs 32R and 32B and processed. Therefore, problems such as linearity, S / N, f characteristics, and temperature characteristics are eliminated.

[Problems to be solved by the invention]

However, in such a video color signal processing circuit, the presence or absence of correlation is determined by the difference level of | a−b |, and when this difference level becomes less than or equal to a predetermined value, an average value is output. Therefore, there is a problem when the level of the color signal is small.

That is, in the case of a high-level color signal, looking at the current signal level and the signal level 1H (one horizontal period) before, and if there is a correlation when the difference is less than a predetermined value, Even if the arithmetic average value of is output, the arithmetic average value does not decrease much due to dubbing and there is no problem.However, if the color signal has a small level, it is possible to output the arithmetic average value by a similar method. In addition, there is a problem that the arithmetic mean value is greatly reduced, the color of the boundary portion is lightened, and the resolution is reduced.

For example, if there is a correlation with a level of 5% or less, the level decreases every time dubbing is repeated, as shown in the following table, and this level decrease causes noise to increase and color unevenness to become noticeable. .

The present invention provides a video color signal processing circuit for solving the above problems.

[Means for solving problems]

As shown in FIG. 1 (a), the conventional video color signal processing circuit compares the level of the current color signal with the level of the color signal 1H before, and the level difference is within the shaded range. In contrast to the case where there is a correlation and the arithmetic mean value is output, the video color signal processing circuit of the present invention, for example, as shown in FIG.
Do not use correlation in the following cases.

[Action]

With the video signal processing circuit having the characteristic shown in FIG. 1 (b), the current data is output without detecting the correlation at the low level. Therefore, as shown in the following table, the level of the color signal should be dubbed. Even if repeated, it does not change from the first level.

In this case, DC due to non-uniformity of CCD characteristics during recording
Since noise such as offset is 5% or less in the full range, the level L is set to, for example, 1/4 full range as shown in FIG. 1 (b), and below that, signal processing is performed without correlation. However, the noise at that time is about 1%, and there is almost no problem even if it is directly output.

Further, the noise component is sufficiently suppressed by the comb filter for a large level color signal.

〔Example〕

FIG. 2 (a) shows an embodiment of the present invention. In FIG. 2A, the color signal Aa is converted into digital data A by the A / D converter 40. The data A is the current data, and the data B is the data 1H before passing through the 1H shift register 41.

The current data A is supplied to the first adder 42, the subtractor 43, and the switch circuit 47 as the first data. The data B 1H before is supplied to the first adder 42 and the subtractor 43.

The first adder 42 adds both data A and B and supplies the added data (A + B) to the second adder 45. The subtractor 43 calculates difference data (AB) which is uncorrelated data of both data A and B, and supplies it to the correlation detector 44.

The correlation detector 44 detects that there is a correlation only when the level of the difference data (A-B) is within a certain range, and the output data f (A-
B) = 0 is output. When there is no detection that there is a correlation, the output data f (AB) = (AB) is output.
FIG. 3 shows the characteristics of such a correlation detector 44. In the figure, when the difference data (A-B) is within ± P, there is a correlation.

The output data f (AB) of the correlation detector 44 is supplied to the second adder 45. The second adder 45 outputs the output data of the correlation detector 44 when the data A and B are correlated with each other.
Since (A−B) = 0, (A + B) is output, and when there is no correlation, 44 output data f (A− of the correlation detector
B) = (AB) is output, so the second adder 45
Then, the calculation of (A + B) + (A−B) = 2A is performed, and the data of 2A is output.

However, the output data of the second adder 45 is the divider
At 46, it is divided into 1/2, so the second to switch circuit 47
When there is a correlation between data A and B as input data of,
The data of (A + B) / 2, which is the arithmetic mean of both data, is supplied, and when there is no correlation between the data A and B, the current data A is supplied.

As the switch signal of the switch circuit 47, for example, the upper 2 bits of the current data A is used. MSB, MS which are the upper 2 bits
When both B-1 are "0", data A is 25% of full level.
The following low level is judged, and the current data A is output as it is. The switch circuit 47 is controlled so as to output the output data of the divider 46 when either MSB or MSB-1 is "1".

As described above, the embodiment shown in FIG. 2 (a) operates, so that when the level of the color signal is small, regardless of the presence or absence of the correlation between the current data A and the data 1H before. The current data A is output, and the color deterioration does not occur even if the dubbing is repeated.

Upper 2 bits of data A as a control signal for the switch circuit 47
When both are "0", the data A is output as it is. In this case, when the level of the data A is 25% or less of the full level, the circuit for specially generating the control signal Is unnecessary, the configuration is simple.

Of course, the level at which the output data of the switch circuit 47 is switched to the data A is not limited to 25%, and may be any level as required.

FIG. 2 (b) shows the embodiment shown in FIG. 2 (a) by RO
Two signals A to embody using the M table
New data is read using n and Bn as address signals. 50 is an A / D converter to which RY color signals are input, 51 is a 1H shift register, 52 is memory, 53 is a latch circuit, 54 is It is a D / A converter.

In the case of this embodiment, the level data A _n of the current color signal
With the level data B _n of 1H before and 1H, the addition average value data is directly output from the memory 52 configured by the ROM.

That is, if the video data is composed of 8 bits, when A _n is “00000000” to “00111111”, the same data as the data of A _n is read regardless of the value of B _n . When A _n is from “00111111” to “11111111” |
A when A _n / B _n | is smaller than a predetermined ratio K (eg 1 dB)
Outputs the data of the value of _n + B _n / 2 and outputs A when | A _n / B _n |> K
It is designed to output the same data as the data of _n .

It goes without saying that the BY color difference signal is similarly configured.

FIG. 2 (c) shows still another embodiment of the present invention, in which 60 is an A / D converter, 61 is a shift register, 62 is an adder, 63 is an arithmetic unit, 64 is a divider, Reference numeral 65 is a comparator, and 66 is a digital switcher.

This embodiment by similarly adder 62 the Example A _n
+ B _n is formed, and the functional data of A _n + B _n by the arithmetic unit 63,
For example, (A _n + B _n ) / 2, (2A _n + 3B _n ) / 5, etc. are formed, and such function data or A _n is selected and output by the digital switcher 66. Is, for example, | B _n in the second divider 64.
/ A _n | is calculated, and this value P is compared with the value E = | 1 ± ΔE | input to the comparator 65, and (1 + ΔE)>P> (1-Δ
In the case of E), "0" level is input to the input NAND gate NA as no correlation and the upper 2 bits of A _n are also input. Then, only when | B _n / A _n | ≈1 and the level of the color signal is high, the arithmetic mean data of the computing unit 63 is output.

〔The invention's effect〕

As described above, the present invention does not detect the correlation in the low-level input color signal and outputs the input color signal as it is. Therefore, even if the dubbing is repeated, the change in the low-level color signal level does not occur. Disappear. That is, even if the dubbing is repeated, the color of the boundary line does not become light and the color does not shift in the vertical direction.

Further, by detecting the low-level color signal from the upper bits of the digital color signal, it is possible to stably detect the low-level color signal without being affected by temperature or the like.

Furthermore, since the signal processing is performed digitally, it is less susceptible to external noise, temperature, etc., and stable operation is possible.

[Brief description of drawings]

FIGS. 1 (a) and 1 (b) are characteristic diagrams when a correlation is detected,
2 (a), (b) and (c) are block diagrams showing an embodiment of the present invention, and FIG. 3 is a correlation detection characteristic shown in FIGS. 2 (a), (b) and (c). Figures and 4 are VTR recording circuit diagrams,
FIG. 5 is an explanatory view showing a recording pattern of a tape, FIG. 6 is a signal waveform diagram, FIG. 7 is a block diagram of a comb filter, FIG. 8 is a waveform diagram for explaining the principle of the present invention, and FIG. Is a block diagram of a conventional signal processing circuit, FIG. 10 is a waveform diagram of the configuration shown in FIG. 9, FIG. 11 is a block diagram of another embodiment, and FIG. 12 is a waveform of the configuration shown in FIG. It is a figure. In the figure, 40 is an A / D converter, 41 is a 1H shift register, 42 and 45 are adders, 43 is a subtractor, 44 is a correlation detector, 46 is a divider, 47
Is a switch circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noboru Fujii 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) Reference JP-A-61-295794 (JP, A)

Claims (1)

(57) [Claims] 1. A means for demodulating color signals of two systems compressed on a time axis, a delay means for delaying the demodulated video color signal by at least one horizontal period, and a color signal and a delay delayed by the delay means. Correlation detection means for detecting correlation with the previous color signal, averaging means for outputting a weighted averaged video color signal of the output signal of the delay means and output signal before delay, and weighted average by the averaging means Video color signal,
Or extraction means capable of extracting and outputting either of the video color signals before weighted averaging, when the demodulated video color signal is below a predetermined level, or the correlation detection means is uncorrelated If it is determined that the video color signal demodulated by the extraction means is output, and the level of the video color signal is equal to or higher than a predetermined value and the correlation detection means determines that there is a correlation, the weighting is performed. An image color signal processing circuit, which is configured to output an averaged image color signal.