JPH01233896A - Signal discrimination circuit for demodulation - Google Patents

Abstract

PURPOSE:To attain sure discrimination by connecting a signal voltage processing means to each signal voltage storage means via a capacitor so as to suppress potential fluctuation of a switching control signal fed to generating means. CONSTITUTION:An output of sample-and-hold circuits 1, 2 is inputted to sample- and-hold circuits 3, 4 via capacitors C0, C1 respectively and sample-holding is applied again by the sample-and-hold circuits 3, 4. The signal subjected to sample and hold by the sample-and-hold circuits 3, 4 is inputted to a subtractor 14, where they are subtracted and the output of the subtractor 14 is inputted to a multiplier 15. The output of the multiplier 15 is inputted to a correction circuit 16 to generate a correction pulse and the correction pulse generated by the correction circuit 16 is fed to a flip-flop 17 to invert a 1/2fH pulse of the flip-flop circuit 17. Thus, the deviation of a DC level such as a discriminator is interrupted by the capacitance and the production of the correction pulse without malfunction is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a demodulation signal discrimination circuit applied to a SECAM type television receiver.

[Summary of the invention]

The present invention sends a carrier color signal of a SECAM television signal to two demodulating means by a changeover switch circuit, and operates a signal voltage holding means and a switching control signal generating means in accordance with the outputs of the two demodulating means. In a demodulation signal discrimination circuit that generates a required switching control signal, by connecting a signal voltage processing means to each signal voltage holding means via a capacitor, potential fluctuations in the signal supplied to the switching control signal generating means can be suppressed. This is to suppress the difference and make reliable judgments.

[Conventional technology]

The SECAM television signal includes a frequency-modulated carrier color signal, and each line (lH) has (R-
The color difference signals of Y) and (B-Y) are sequentially switched signals. The center frequencies are different between the color difference signal (R-Y) line and the color difference signal (B-Y) line, and the color difference signal (R-Y) side is a 4.4Ml type 1 color difference signal (B-y). Each side has 4.25 MHz unmodulated carriers.

Hitherto, as a signal demodulation circuit for demodulating such a SECAM system television signal, one using a variable phase shifter, for example, has been known, and is disclosed in Japanese Patent Laid-Open Nos. 62-95088 and 62-95090. There is related prior art as described in publications.

In some cases, the signal demodulation circuit is provided with a demodulation signal discrimination circuit that identifies which color difference signal is being sent and controls the correct changeover switch accordingly.

FIG. 7 shows a conventional circuit configuration in which signals from a discriminator in a signal demodulation circuit are used to discriminate and correct signals. As shown in FIG. 7, the carrier color signal is input to the circuit, and the
The output of the changeover switch circuit 101, which is switched under the control of the A f N pulse, is supplied to discriminators 102 and 103, respectively. The output of the discriminator 02 (waveform (a) in FIG. 8), that is, the color difference signal (RY), is supplied to the sample and hold circuit +04. The sample and hold circuit 104 samples and holds the unmodulated carrier portion bso and outputs it (waveform shown in FIG. 8). In parallel, the output of the discriminator 103 (waveform (C) in FIG. 8), that is, the color difference signal (B-Y) is sent to the sample hold circuit 10.
5. In the sample hold circuit 105,
The unmodulated carrier portion bs+ of the color difference signal is sampled and held, and its output (waveform (d) in FIG. 8) is obtained.

The outputs of these sample and hold circuits 104 and 105 are both supplied to a subtracter 106.
A differential voltage is output from 6.

This subtracter 106 is connected to a multiplier 107, and in this multiplier 107, multiplication by +Af signals (waveform (e) in FIG. 8) from the flip-flop circuit 108 is performed. Then, the output is transmitted to the correction circuit 10 of the required configuration.
Sent to 9th. Here, the output of the multiplier 107 becomes "°H°° level" when the switching state of the control pulse from the flip-flop circuit 108 is correct, and "
becomes L” level. Therefore, in the correction circuit 109,
A correction pulse can be sent to the flip-flop circuit 108 for correction only in the event of an error, and normally such operation will ensure that the correct line-by-line signal is sent to each discriminator. Control of the changeover switch j1 will be performed.

[Problems to be Solved by the Invention] However, as described above, in the circuit configuration shown in FIG.
4,105, the voltage is sampled and held as it is. Then, if the deviation in the DC level is extreme, the correction circuit 109 generates an erroneous correction pulse, and if this continues for a long time, the color may disappear, especially when adjusting the discriminator. Malfunction of the correction circuit 109 makes its adjustment difficult.

Therefore, an object of the present invention is to provide a demodulation signal discrimination circuit that realizes reliable discrimination.

[Means to solve the problem]

In order to achieve the above object, the demodulation signal discrimination circuit of the present invention includes a changeover switch means to which a carrier color signal of a SECAM television signal is supplied and controlled by a changeover control signal, and each output of the changeover switch means. Supplied 1st. a second demodulating means; a first signal voltage holding means to which the output of the first demodulating means is supplied; and a second signal voltage holding means to which the output of the second demodulating means is supplied; a first signal voltage processing means connected to the input side or the output side of the first signal voltage holding means via a capacitor;
a second signal voltage processing means connected to the input side or the output side of the second signal voltage holding means via a capacitor; and the switching control according to the output of the signal voltage holding means or the signal voltage processing means. It is characterized by comprising a switching control signal generating means for generating a signal.

Here, a sample hold circuit or a clamp circuit can be used as the first and second signal voltage processing means.

[Effect]

The capacitor cuts the direct current component of the signal manually input to the first and second signal voltage holding means and the signal output. Therefore, it is possible to reliably generate a switching control signal.

〔Example] Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment This embodiment is the first embodiment. This is an example in which the first and second signal voltage processing means connected to the output side of the second signal voltage holding means via a capacitor are sample and hold circuits.

First, the block configuration of the demodulation signal discrimination circuit of this embodiment is shown in FIG. 1. This circuit is provided with a changeover switch circuit 11 to which a carrier color signal of a SECAM television signal is supplied.

This changeover switch circuit 11 is switched and controlled by the 'A f N pulse from the flip-flop circuit 17. Due to this switching operation, one of the two outputs of the changeover switch circuit 11 is connected to the discriminator 12.
and the other is input to the discriminator 13.

The discriminator 1 as such a demodulating means
At 2 and 13, demodulation is performed, respectively.

The output of the discriminator 12 is a color difference signal (R-Y), and the output of the discriminator 13 is a color difference signal (B-
Y).

The color difference signal from the discriminator 12 is input to a sample hold circuit 1 which is a first signal voltage holding means, and the color difference signal from the discriminator 13 is input to a sample hold circuit 2 which is a second signal voltage holding means. Enter. These sample and hold circuits 1.2 can sample and hold the signal level of the unmodulated carrier portion of each color difference signal, and output the signal level, as will be described later.

The output of the sample and hold circuit 1.2 is input to the sample and hold circuit 3.4 via capacitors C, , C, respectively. Since the capacitors C, , C, are provided in series, they can block the DC component and differentiate the output signal of the sample-and-hold circuit 1.2.

The signals thus input through the capacitors Co and C+ are sampled and held again by the sample and hold circuits 3 and 4, respectively. The level at which this sample is held is determined by each discriminator 12.
This is unrelated to the DC level shift of No. 13.

The signals sampled and held by the sample and hold circuit 3.4 are both manually subtracted by a subtracter 14. The output of the subtracter 14 is input to a multiplier 15. The multiplier 15 receives the output from the subtracter 14 as well as the '/2f pulse from the flip-flop circuit 17.

The output of this multiplier 15 is input to a correction circuit 16 for generating correction pulses. And this correction circuit 16
The correction pulse generated in the above flip-flop circuit 1
'A of this flip-flop circuit 17.
The f m pulse can be inverted.

The operation of the demodulation signal discrimination circuit of this embodiment having such a configuration will be explained with reference to FIG.

First, the color difference signal (
Suppose that RY) has a waveform like waveform (a) in FIG. Note that in waveform (a), pulse Bs.

The part corresponds to the unmodulated carrier. Then, the output of the sample-and-hold circuit 1, which samples and holds the unmodulated carrier portion of the output from the discriminator 12, holds the level of the pulse Bs for each IH, like the waveform value).

Next, the output of the sample and hold circuit 1 is input to the sample and hold circuit 3 via the capacitor C0.

At this time, in the capacitor IC0, the DC component is cut, and the output waveform of the sample-and-hold circuit 1 is made into a differentiated waveform, as shown in waveform (C) in FIG.

Next, sample and hold circuit 3 is loaded with ! A signal differentiated by c o is input. At this time, the sample and hold circuit 3 holds the voltage immediately after the rise and fall of the waveform (C). here,
Assuming that the voltage is Δ, the rising and falling potential difference of the sample hold circuit 3 has a level of 2Δ as shown in the waveform (d) due to the discharge of the capacitor C0.

Similarly, on the discriminator 13 side, the color difference signal (B
-Y) has a waveform like waveform (6) in FIG. 2, by holding the pulse Bs corresponding to the unmodulated carrier in the sample hold circuit 2,
The output signal of the sample and hold circuit 2 is a waveform (f
) signal. This is in opposite phase to waveform (b). And the above content 1c.

A differential waveform (80) is obtained, and this differential waveform (g) has its DC component cut off.Next, the voltage immediately after the rise and fall of the differential waveform (g) is applied to the sample hold circuit 4. , and its output signal is similarly made to have twice 2Δ, as shown by the waveform (b).

Hereinafter, the operation of the demodulation signal discriminating circuit of this embodiment is such that the difference signal between the output signals of the sample and hold circuits 3 and 4 shown by waveforms (d) and (c) is transmitted to the subtracter 14 by the subtracter 14. It is output from 14. Then, the output is multiplied by the y2f n pulse from the flip-flop circuit 17. here,
In the case of a good signal state, an "H" level signal is input to the correction circuit 16, and no correction pulse is generated. Furthermore, when the timing of switching between the color difference signals (R-Y) and (B-Y) is incorrect, a 'L' level signal is input to the correction circuit 16 and a correction pulse is sent to the flip-flop circuit 17. . As a result, the timing of the 'Af++ pulse of the flip-flop circuit is also switched, and the operation of the changeover switch circuit 11 is switched to the correct one.

Next, while referring to FIG.
Or 2. An example of a specific circuit configuration of the capacitor C0 or CI and the sample-and-hold circuit 3 or 4 will be described.

The circuit shown in FIG. 3 first uses transistors Q, , Q whose emitters are commonly connected, transistors Q, , Q whose emitters are connected in common, transistors Q, , Q whose emitters are connected in common, transistors Q, , Q, which are connected as a current mirror, and a constant current source 31 to form a sample and hold circuit. A dynamic amplifier is provided between the commonly connected emitters and the constant current source 31.
Switch 21 controlled by pulse (horizontal same month signal)
is provided. The sample hold container 137 is
The transistor Q5 and the constant current source 32 constitute a buffer.

The output of this sample and hold circuit is input to the capacitor Ice connected in series. A resistor 36 and a power supply 35 are provided at the output terminal of this capacitor 31c0, forming a differentiating circuit.

Next, to the output terminal of the capacitor Ice, transistors Q, , Q whose emitters are commonly connected, transistors Q, , Q, whose emitters are connected in common, transistors Q, , Q, which are connected as a current mirror, and a constant current source 33 are connected to the output terminal of the capacitor Ice, so as to constitute a sample hold circuit. A dynamic amplifier is provided, and a switch 22 controlled by n pulses is provided between the commonly connected emitters and the constant current source 33. A sample and hold capacitor 13B of this sample and hold circuit is connected to its output side, and a buffer is formed by a transistor Qlo and a constant current source 34.

In such a circuit configuration, the switch 21.2
Send n pulses to 2 and receive the voltage during the period corresponding to the unmodulated carrier portion of the color difference signal! ! 137, and after cutting off the DC component as described above, the sample can be held again by the capacitor 38. Then, the capacitor C0 is discharged until the next sample and hold period, and the output signal becomes 2Δ.

In such a circuit configuration, by reducing the time constant applied to the capacitor C0, high-speed discharge can be achieved, and thereby it is also possible to reduce the error.

Second Embodiment This embodiment is an example in which a clamp circuit is used as the first and second signal voltage processing means connected through a capacitor.

First, FIG. 4 shows a block configuration of the demodulation signal discriminating circuit of this embodiment. This circuit is provided with a changeover switch circuit 51 into which a carrier color signal of a SECAM television signal is input. This changeover switch circuit 51
The switching is controlled by the +Af□ pulse from the flip-flop circuit 57. By this switching operation, one of the two outputs of the changeover switch circuit 51 is input to the discriminator 52 and the other is input to the discriminator 53.

The discriminator 5 as such a demodulating means
2.53, demodulation is performed respectively.

The output of the discriminator 52 is a color difference signal (R-Y), and the output of the discriminator 53 is a color difference signal (B-
Y).

The color difference signal from the discriminator 52 is input to a sample hold circuit 41 which is a first signal voltage holding means, and the color difference signal from the discriminator 53 is input to a second signal voltage holding circuit.
The signal voltage is input to a sample hold circuit 42 which is a signal voltage holding means. These sample and hold circuits 41 and 42 can sample and hold the signal level of the unmodulated carrier portion of the color difference signal, respectively, as will be described later.
The signal level is output.

The outputs of the sample and hold circuits 41 and 42 each have a capacitance of C! , C3 to the clamp circuits 43, 44. In this way, the capacitance C,,C.

The signals inputted through the respective clamp circuits 43.
Since the respective output terminal sides of the capacitors C, C3 are clamped to a predetermined potential by 44, only the AC voltage is transmitted to the output terminal sides of the capacitors ICs and Cs. This clamped level is the DC of each discriminator 52, 53.
It is unrelated to the level deviation, therefore, the
The signal that has passed through z and cs does not include any deviation in DC level. The clamp circuit 43 is supplied with a clamp pulse from an AND circuit 59 for timing the clamp. Further, a clamp pulse is supplied to the clamp circuit 44 from an AND circuit 60. The H pulse and the 'A r +1 pulse from the flip-flop circuit 57 are input to the AND circuit 59 . Further, a 1 (pulse) is input to the AND circuit 60, and a zrN pulse from the flip-flop circuit 57 is inputted via the inverter 58.

The output signals from the clamp circuits 43 and 44 are both input to a subtracter 54 and subtracted. The output of the subtractor 54 is
The multiplier 55 is input manually. This multiplier 55 includes a subtracter 5
4, the 'A f N pulse from the flip-flop circuit 57 is also input.

The output of this multiplier 55 is input to a correction circuit 56 for generating correction pulses. And this correction circuit 56
The correction pulse generated in the above flip-flop circuit 5
'A of this flip-flop circuit 57.
The timing of the fs pulse can be changed.

The operation of the demodulation signal discrimination circuit of this embodiment having such a configuration will be explained with reference to FIG.

First, the color difference signal (
RY) has a waveform like the waveform (a) in FIG. 5, and the color difference signal (B-Y) which is the output of the discriminator 53
Assume that the waveform is as shown in waveform (C) in FIG. Note that in the waveforms (a) and (C), each portion of the pulse BS6°Bs corresponds to an unmodulated carrier.

Then, the output of the sample and hold circuits 41 and 42 that sample and hold each of these non-modulated carrier portions is the pulse Bso for each IH, as shown in waveforms (b) and (d).
, Bsl level is maintained.

Next, the output of the sample and hold circuits 41 and 42 is the capacitance c
z is input to clamp circuits 43 and 44 via C3. Here, each clamp circuit 43.44 is connected to the "H" output of the sample hold circuit 41.42 connected to the respective clamp circuit 43.44.
Depending on the level, (F?-Y) clamp pulse (5th
waveform (f)) or (B-Y) clamp pulse (5th
The waveform (turbid) shown in the figure is supplied. Therefore, the DC voltage at the output side terminals of the capacitors C, , C, in the clamp circuits 43 and 44 is fixed at the clamped potential, and therefore only the variation from that DC voltage is applied to the next stage. It will be output to the subtracter 54.

The (RY) clamp pulse supplied to the clamp circuit 43 is obtained by combining the 2ru pulse shown in waveform (e) in FIG. 5 and the H pulse shown in waveform 01) in FIG.
can be obtained through. The (B-Y) clamp pulse supplied to the clamp circuit 44 is a pulse obtained by inverting the 'A f s pulse shown in waveform (e) in FIG. (1) One pulse can be obtained via the AND circuit 59.

Then, due to the functions of the clamp circuits 43 and 44,
Sample hold circuit 4 shown by waveform (b) and waveform (c)
Only the AC component of each output signal of 1.42 is transmitted to the subtracter 54, and the difference signal is output from the subtracter 14. And +AfH from the flip-flop circuit 57 is applied to its output.
The pulses are multiplied. Here, in the case of a good signal state, an "H" level signal is input to the correction circuit 56, and no correction pulse is formed. In addition, the color difference signal (R-Y),
When the switching timing of (B-"l) is incorrect, an "L" level signal is input to the correction circuit 56, and a correction pulse is sent to the flip-flop circuit 57. This causes the flip-flop circuit to AtA
The timing of the t-switch is also changed, and the operation of the changeover switch circuit 51 is switched to the correct one.

Next, referring to FIG. 6, the clamp circuits 43 and 44 are
An example of a specific circuit configuration will be explained.

As shown in FIG. 6, a transistor Q z +
＋Q! T+Q! ! +Q t a
+ A differential amplifier constituted by a constant current source 63 and a switch 62 is connected. A reference voltage V ref is connected to the base of the transistor Q, and a transistor Q z whose emitter is commonly connected to the transistor Q,2 is connected to the reference voltage V ref.
The terminal of the capacitor 161 is connected to the base of the +.

Further, the terminal of the capacitor 161 is connected to a buffer. This buffer consists of transistors Q t s +Q
t b + Q z q + Q z s + A differential amplifier composed of a constant current source 64 and a transistor Q
x+ and a constant current source 65.

To explain the operation of this clamp circuit, the output from the sample and hold circuit whose DC component is blocked by the capacitor 61 is input to the base of the transistor Q□. However, the base voltage vre is connected to the base of the transistor Qzt constituting the differential transistor pair, and therefore, by supplying a clamp pulse to the switch 62, the base of the transistor Qz+ is also fixed to the voltage Vrer. Therefore, the base of the transistor Qzs constituting the buffer is supplied with a signal whose DC level is centered at the voltage V ref, and therefore the clamp circuit outputs the signal of the sample and hold circuit. Output without deviation in DC level is possible.

Note that in the demodulation signal discrimination circuit of this embodiment, the first and second
The signal voltage holding means of the first . The second signal voltage processing means is a re-build circuit,
Although the circuit configuration is such that the clamp circuit is provided on the output side of the sample and hold circuit, it is also possible to provide the clamp circuit at the input end of the sample and hold circuit via a capacitor.

In this case, the clamp pulses may be divided into +Ar and l pulses. Further, the switching control signal generating means includes the above-mentioned subtracter 54. Multiplier 55° flip-flop circuit 57. The circuit configuration is not limited to the correction circuit 56, and other circuit configurations may be used.

[Effects of the Invention] As described above, the demodulation signal discrimination circuit of the present invention can block the deviation of the DC level of the discriminator etc. by the capacitance, and therefore can generate correction pulses without malfunction. Become. This is especially effective when adjusting discriminatory/evening.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the demodulation signal discrimination circuit of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the example, and FIG. 3 is a specific example of the sample-hold circuit and capacitance of the above example. FIG. 4 is a block diagram showing another example of the demodulation signal discrimination circuit of the present invention, and FIG.
The figure is a waveform diagram for explaining the operation of the other example above.
The figure is a circuit diagram showing a specific example of the circuit configuration of the other example of the clamp circuit. Further, FIG. 7 is a block diagram showing an example of a conventional demodulation signal discrimination circuit, and FIG. 8 is a waveform diagram for explaining the operation of the conventional example. 1.2.3, 4, 41.42... Sample hold circuit 43.44... Clamp circuit C+, C1, Cz, C3... Capacity 11.51... Changeover switch circuit 12.13, 5
2.53...Discriminator 14.54...Subtractor 15.55...Multiplier 16.56...Correction circuit 17.57...Flip-flop circuit Patent applicant
Sony Corporation

Claims (1)

[Scope of Claims] Changeover switch means to which a carrier color signal of a SECAM television signal is supplied and controlled by a switching control signal; a first switch to which each output of the changeover switch means is supplied;
a second demodulating means; a first signal voltage holding means supplied with the output of the first demodulating means; and a second signal voltage holding means supplied with the output of the second demodulating means; a first signal voltage processing means connected to the input side or output side of the first signal voltage holding means via a capacitor; and a first signal voltage processing means connected to the input side or output side of the second signal voltage holding means via a capacitor. a second signal voltage processing means; and a switching control signal generating means for generating the switching control signal according to the output of the signal voltage holding means or the signal voltage processing means.