JP2508519B2 - Transmission circuit for predetermined frequency signal - Google Patents

Description

TECHNICAL FIELD The present invention relates to a transmission circuit for transmitting a predetermined frequency signal, for example, a low frequency signal, and more particularly to a circuit suitable for use as an IC.

[Outline of Invention]

The present invention is a signal transmission method in which only a portion near a transient that uses a signal of a predetermined frequency component in the next stage is completely transmitted as direct-current energy, and it is not necessary to externally attach a large capacity, and particularly in a low frequency range. Effective in transmitting frequency signals.

[Conventional technology]

For example, there is a VTR capable of recording and reproducing both a PAL signal and a SECAM signal, but it is convenient if this type of VTR can automatically determine whether the signal to be handled is a PAL signal or a SECAM signal. The applicant previously made this determination by utilizing the fact that the subcarrier frequency of the PAL signal is constant, whereas the subcarrier frequency of the red color difference signal and the blue color difference signal of the SECAM signal are different. We have proposed a discrimination method for performing the above (Japanese Patent Application No. 61-167601, filed on July 16, 1986).

FIG. 3 is a block diagram of the previously proposed discrimination circuit, and FIG. 4 is a time chart for its explanation.

In FIG. 3, (1) is an input terminal to which a line-sequential color signal of a PAL signal or SECAM signal is supplied. The color signal through this input terminal (1) is a switch for color alignment correction in this example. It is supplied to one input end of the circuit (2) and is supplied to the other input end of the switch circuit (2) via the delay circuit (3) of one horizontal period. In this case, as shown in FIG. 4, the PAL signal is input from the input terminal (1) in the periods Ta and Tc, and the SECAM signal is input from the input terminal (1) in the period Tb between them.

The output of the switch circuit (2) is supplied to the color signal processing system. The color signal from the input terminal (1) is supplied to the burst gate circuit (4) to separate the burst signal.
The separated burst signal is supplied to the FM demodulation circuit (5) for demodulation, and in this case, frequency discrimination. As shown in FIG. 4A, the output of the demodulation circuit (5) has a constant peak value because the burst signal frequency of the PAL signal is constant in the input periods Ta and Tc of the PAL signal, while the SECAM signal input period is constant. At Tb, since the burst signal frequency is different for each horizontal section, the peak value repeats high and low for each horizontal section.

This demodulated output is supplied to the sampling and holding circuit (7) through the low pass filter (6). In this sampling hold circuit (7), the peak value of the discrimination output of the burst signal from the demodulation circuit (5) is sampled and held. Therefore, the output of the sampling and holding circuit (7) is the PAL signal input period T as shown in FIG. 4B.
a, becomes Tc in a constant level, 1 / 2f _H to invert the state every horizontal period in SECAM signal input period Tb (f _H is the horizontal frequency) becomes a signal.

This sampling hold output is supplied to the differential amplifier (9) via a large capacity capacitor (8) for DC cutting. Here, since the direct current component of the sampling hold output is not determined in the direct current cut by the capacitor (8), the direct current component is cut and amplified in the amplifier (9) and an appropriate predetermined direct current potential is added to the next stage. This is because The reason why the amplifier (9) is a differential amplifier is that it is convenient to add and output DC,
The direct current is usually added simply by applying a bias.

The output of the differential amplifier (9) is supplied to the synchronous detection circuit (10).

On the other hand, the horizontal sync signal is sent to the PLL circuit (1
2), and from this, a signal of frequency f _H synchronized with the horizontal synchronizing signal is obtained, and this signal is divided by the frequency dividing circuit (13).
The frequency is divided by 1/2 to obtain a 1 / 2f _H synchronous detection signal (FIG. 4D), which is supplied to the synchronous detection circuit (10).

Therefore, as shown in FIG. 4E, the output of the synchronous detection circuit (10) becomes a signal of 1 / 2f _H in the PAL signal input period Ta, Tc and becomes positive or negative in the SECAM signal input period Tb. In this case, it is assumed that the line sequentiality of the color difference signals is correct when the detection output is negative, and in the example of FIG. 4, after the time t ₀ , for example, a VTR reproduction signal (especially a reproduction signal such as variable speed reproduction) becomes The case where the line order of the color difference signals is reversed is shown.

The output of the synchronous detection circuit (10) is integrated by the low-pass filter (14), and its output (Fig. 4F) is supplied to the level comparison circuit (15) and compared with the reference level Lb.
From this, a comparison output signal as shown in FIG. 4G is obtained. This signal becomes a detection signal in a section in which the line-sequential order is reversed. This signal is supplied to the trigger terminal of the flip-flop (16) and its output is inverted. The output of the flip-flop (16) is supplied to the switch circuit (2), and the switch circuit (2) is switched to the opposite state. Since the color signals are changed over by one horizontal cycle, the order of the line-sequential order of the color difference signals is reversed and the color signals are made correct.

The output of the synchronous detection circuit (10) is also supplied to the low pass filter (18) via the polarity inverting circuit (17).
The polarity inversion circuit (17) is supplied with the output of the level comparison circuit (15), and the polarity of the synchronous detection output is inverted during the period in which the line sequentiality is reversed. Therefore, the output of the low-pass filter (6) is always a low level signal during the SECAM signal input period Ta as shown in FIG. 4H. The output of the low-pass filter (18) is supplied to the level comparison circuit (19) and compared with the reference level La. From this, a discrimination signal of the PAL / SECAM signal as shown in FIG. 4F is obtained, and the output terminal ( 2
0).

In this example, since the line-sequential inversion of the color signal cannot be discriminated during the PAL signal input period, the PAL / SECAM discrimination signal is supplied to the reset terminal of the flip-flop (16), and when the PAL signal is input, the flip-flop ( 16) is not reversed.

[Problems to be solved by the invention]

By the way, as the circuit for amplifying the output of the sampling and holding circuit (7) and supplying it to the synchronous detection circuit (10) in the PAL / SECAM discrimination circuit described above, it is necessary to transmit a low frequency signal component of 1 / 2f _H. It is a necessary condition that the DC component of the signal is once removed, and then an appropriate predetermined DC component is added to the circuit of the next stage and then output.

Conventionally, as described above, in order to pass the entire 1 / 2f _H signal component from the sampling and holding circuit (7), first the direct current is cut by the large-capacity capacitor (8),
The amplifier (9) is composed of a differential amplifier, and is biased and output.

By the way, considering the case where this amplifier (9) is integrated into an IC, when a low frequency signal of about 1/2 f _H is directly input to the differential amplifier, the capacitance of the DC cut capacitor is generally several microfarads. The above was necessary, and it could not be made inside the IC, and the capacitor (8) had to be externally attached. Therefore, an external pin is required, which is not preferable as an IC circuit.

The present invention intends to provide a circuit suitable for IC as a circuit for handling relatively low frequency signals without requiring an external capacitor for DC cut.

[Means for solving problems]

The present invention is a circuit which has a capacitor for cutting direct current, and which cuts direct current by this capacitor and then adds a direct current component suitable for the circuit of the next stage to a predetermined frequency component and outputs it. It is provided with means for clamping the signal of the predetermined frequency component with a clamp pulse having a cycle corresponding to the signal of (1) so that the DC component in the vicinity of the transient of the predetermined frequency signal is made constant.

[Action]

In the case of the present invention, not all the signals of the predetermined frequency component are passed, but only the transient part is transmitted, so the capacitor for DC cut may have a small capacity, and this capacitor in the IC Can be obtained. Since the DC potential near the transient is clamped and set, the optimum DC potential is reliably determined in the circuit in the next stage.

〔Example〕

An embodiment of the present invention will be described with reference to FIG. 1. In this example, in the PAL / SECAM discrimination circuit of FIG.
DC cut capacitor (8) and differential amplifier (9)
This is the case when the part of is configured to be suitable for IC.

That is, (21) is the sampling and holding circuit (7).
The input terminal to which the signal SA (Fig. 2A) of 1/2 f _H from is input, and (22) is a DC cut capacitor, which can have a small capacity as described later. It is composed of the capacitance inside the IC, not externally.

(23) and (24) are a pair of transistors forming a differential amplifier, and (25) is a transistor forming a current source of this differential amplifier.

The signal SA (FIG. 2A) of frequency 1 / 2f _H , which is DC-cut by the capacitor (22) through the input terminal (21), is applied to the base-emitter path of the transistor (28) and the base-emitter of the transistor (29). It is supplied to the base of the transistor (23) via the passage.

Then, output signals SO and ▲ ▼ (FIGS. 2C and 2D) are obtained at the output terminals (26) and (27) derived from the collectors of the transistors (23) and (24).

(31) is an input terminal for the clamp pulse CP. In this case, the clamp pulse CP is the input signal as shown in FIG. 2B.
It is a 1 / 2f _H signal synchronized with SA, and is a low level signal only during the clamp period. Therefore, the transistor (3
2) and (33) are off only during the clamp period and on during the other periods. Then, in the clamp section, the transistor (33) is turned off, so that the transistor (34) becomes conductive and the voltage dividing resistors (35) and (36).
A predetermined voltage corresponding to the voltage set at is obtained on the collector side of the transistor (34), and this appears as a clamp voltage on the emitter side of the transistors (37) and (38). The emitter of the transistor (37) is connected to the connection point between the capacitor (22) and the base of the transistor (28). On the other hand, the output voltage on the emitter side of the transistor (38) is supplied to the base of the transistor (24) via the base-emitter paths of the transistors (40) and (41). The connection point between the emitter of the transistor (38) and the base of the transistor (40) is grounded via a capacitor (39) having the same capacity as the capacitor (22).

Therefore, the output signals SO and ▲ ▼ are fixed at the clamp potential during the clamp period. In the period other than the clamp period, the emitter potential of the transistor (37) is in a floating state, the capacitor (22) is charged and discharged according to the voltage change of the input signal SA, and the output signal SO is in the state where the input signal SA is inverted, Output signal ▲ ▼ is the input signal SA
It will be in the same phase as. At this time, since the capacitor (39) and the clamp circuit are also connected to the other transistor (24) side of the differential configuration, the differential amplifier has no DC offset.

As described above, according to the present invention, the signal component transmits the waveforms of the rising and falling transient portions, and the clamp circuit resets the charges of the capacitors (22) and (39) every horizontal period. It's clamped. As a result, as shown in FIGS. 2C and 2D, the gain of the differential amplifier can be twice as large as the normal gain.

In this case, what is transmitted by this differential amplifier is the transient part of the rising and falling edges of the signal, but this is the latter stage circuit, in this case, only the rising and falling edges are transmitted by the synchronous detection circuit. If so, there is no problem even if some waveforms lack accuracy, so there is no problem.

〔The invention's effect〕

According to the present invention, an input signal having a predetermined frequency is clamped by a clamp pulse having a cycle corresponding to the input signal, the DC component near the rising or falling transient of the input signal is made constant, and this transient portion is transmitted. As a result, the capacitor for cutting direct current can have a small capacity, and when it is integrated into an IC, it can be realized by the internal capacity of the IC. Therefore, when integrated into an IC, an external capacitor is not needed, and the number of external pins for that purpose can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a PAL / SECAM discrimination circuit, and FIG.
FIG. 3 is a timing chart for explaining it, FIG. 3 is a circuit diagram of one embodiment of the present invention, and FIG. 4 is a timing chart for explaining it. (21) is an input terminal, (22) is a DC cut capacitor,
(23) and (24) are transistors forming a differential amplifier, (26) and (27) are output terminals, (31) is a clamp signal input terminal, and (37) and (38) are clamped on the emitter side. A transistor that obtains a voltage.

Claims (1)

(57) [Claims] 1. A small-capacity DC-cutting capacitor, which cuts an input signal by DC, and which is suitable for a next-stage circuit for a predetermined frequency component by a differential amplifier having no DC offset. A circuit for adding and outputting a component, comprising means for clamping the signal of the predetermined frequency with a clamp pulse having a cycle corresponding to the signal of the predetermined frequency component, and the clamp period is set by the means for applying the clamp. The DC component near the transient of the predetermined frequency signal is made constant, and the means for applying the clamp is opened except during the clamp period, and the capacitor is charged and discharged according to the voltage change of the input signal, and the output signal is A transmission circuit for a predetermined frequency signal that is obtained.