JPS63244980A - Synchronizing signal detecting circuit - Google Patents

Abstract

PURPOSE:To correctly decide the presence and the absence of a synchronizing signal and in a short time by detecting the detected pulse of a normal horizontal synchronizing only at the time of having a prescribed pulse duration and a prescribed cycle. CONSTITUTION:The horizontal synchronizing signal of the prescribed pulse duration is detected from the pulse string of a composite synchronizing signal separated from a video signal in a pulse duration detecting circuit 29. The presence and the absence of the synchronization of the horizontal synchronizing signal are detected by a horizontal synchronizing detecting circuit 33. According to these circuits, only at the time of having the prescribed pulse duration and the prescribed cycle, the detection pulse of the normal horizontal cycle is detected, the AND of this detecting pulse and a timing pulse obtained from the horizontal counter 27 of a horizontal PLL circuit 23 is fetched in an AND gate 39. The output of the AND gate 39 is passed through an integrating circuit 41 and a slice circuit 42, thereby, the presence and the absence of the synchronizing signal are decided.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention performs automatic channel selection in a television receiver (hereinafter referred to as a TV receiver), particularly in a TV receiver using a liquid crystal display. This invention relates to a synchronization signal detection circuit used for.

(Prior Art) It is well known that in recent years, TV receivers have been miniaturized, and for example, those using liquid crystals have appeared in affordable sizes.

In such liquid crystal TV receivers, etc., an automatic surge channel selection method is used, and the 'y1 station is selected by detecting the presence or absence of a synchronization signal of the selected channel. That is, when a synchronization signal can be detected, channel selection is stopped and the channel has been selected.

Conventionally, a synchronizing signal detection circuit used in the above-mentioned channel selection method is configured as shown in FIG. In this diagram,
A video signal 1 supplied as an input is synchronously separated by a synchronous separating circuit 2 to obtain a composite synchronous signal C8. This composite synchronization signal C8 is sent to a well-known horizontal PLL (phase locked loop) circuit 3.

The horizontal PLL circuit 3 includes a phase comparator 4, an LPF (low pass filter) 5, a VCO (voltage controlled oscillator) 6, and a horizontal counter 7. The oscillation frequency of the VCO6 often varies depending on the system configuration, but in an example of a liquid crystal TV receiver, the frequency of the vCO output CP is, for example, 512X.
fH (approximately 8 MHz). However, fil is the horizontal frequency. Then, the CO output CP is guided to a horizontal counter 7 consisting of nine stages and frequency-divided by 11512. The output HT of the ninth stage of the horizontal counter 7 is fed back to the phase comparator 4, and its phase is compared with the composite synchronization signal C8. FIGS. 5A and 5C show the phase relationship between the composite synchronization signal C8 and the output signal HT. A lock is applied so that the center of signal C8 and the rising edge of HT match in phase. Furthermore,
The signal taken out from the horizontal counter 7 is passed through a gate circuit 8 to obtain a signal T1 timed to the composite synchronization signal O8. This signal @T1 and the signal C8 are ANDed by an AND<AND) gate 9, and the output is sent to a well-known integration circuit 10.
guided by. Figures 5 (a) and (b) show Goo 1 to output T.
1 and signal C8. The pulse width of the signal C8 is about 4.8 μsec, and the width of the logic “1” level of the signal T1 is set to about 12 to 13 μSaC, taking into consideration the steady phase error of the PLL, temperature variations, power supply voltage variations, etc. Also, the signal T1 is a pulse that includes the rising edge of the signal )-IT.The integration circuit 10 is a circuit that integrates the output of the AND gate 9, and the signal @C8 is eight within the logic "1" level of the signal T1. When the voltage is on, the integrated voltage increases.The integrated output is sent to the slice circuit 11 at a predetermined voltage level V r
It is sliced with ef. When the slice output is at a logic "1" level, it indicates that a synchronization signal has arrived and is being detected, and when the slice output is at a logic "0" level, it indicates that no synchronization signal has arrived.

By the way, in the conventional synchronization signal detection described above, since the integration circuit is driven by the result of the logical product of the composite synchronization signal O8 and the signal T1, (1) it is easy to malfunction due to noise components mixed in the signal C8; (2) There have been problems such as the need to reduce the influence of the vertical synchronization signal period.

For this reason, conventional synchronization signal detection solves the above problems (1) and (2) by increasing the integration time constant. Therefore, it takes time to determine the presence or absence of a synchronization signal.
Channel selection took a very long time.

(Problems to be Solved by the Invention) As described above, the conventional synchronization signal detection has a problem in that it takes a long time to determine the presence or absence of a synchronization signal.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a synchronization signal detection circuit that can accurately determine the presence or absence of a synchronization signal and in a shorter time than before.

[Structure of the Invention] (Means for Solving the Problems) The synchronization signal detection circuit of the present invention is a pulse width detection circuit that detects a horizontal synchronization signal of a predetermined pulse width from a pulse train of a composite synchronization signal separated from a video signal. The circuit is equipped with a horizontal period detection circuit that detects the presence or absence of synchronization of the detected horizontal synchronization signal, and generates a regular horizontal synchronization detection pulse only when the pulse width is a predetermined value and the period is a predetermined period. , the presence or absence of a synchronization signal is determined by logically ANDing this detection pulse and the timing pulse obtained from the horizontal counter of the horizontal PLL circuit using an AND gate, and passing the AND output through an integrating circuit and a slicing circuit. .

(Function) In the present invention, since only the horizontal synchronization signal component is detected from the pulse train of the composite synchronization signal, the influence of noise and the vertical synchronization signal period is extremely reduced, and the synchronization signal The presence or absence can be determined accurately and in a short time.

(Example) The present invention will be described below based on the example shown in the drawings.

FIG. 1 is a block diagram of a synchronization signal detection circuit according to an embodiment of the present invention.

In this figure, a video input signal 21 is input to a sync separation circuit 2.
2, where the composite synchronizing signal C8 is separated, and this signal @O8 is supplied to the horizontal PLL circuit 23. Horizontal P
The LL circuit 23 includes a phase comparator 24, an LPF 25, and a VCO 2.
6. Consists of a horizontal counter 27, the output of the VCO 26 is frequency-divided by the horizontal counter 27, and the frequency-divided output HT is phase-compared with the signal C8 by the phase comparator 24 to determine the horizontal frequency fi.
Locked with l. The horizontal counter 27 consists of nine stages,
The signal obtained from this counter is passed through the gate circuit 28 to obtain a timing signal T1 synchronized with the signal C8. On the other hand, the composite synchronization signal C8 is supplied to a pulse width detection circuit 29, and these two circuits perform pulse width detection using the clock φ1 as a reference clock. As the clock φ1, a pulse with a frequency of about 1 μsec outputted from the third stage of the horizontal counter 27 is used, and the pulse width detection circuit 29 uses the composite synchronization signal C.
8 has a pulse width of about 4 μsec or more, it is regarded as a horizontal dosing signal and a detection pulse HP' is output. The pulse width detection circuit 29 consists of, for example, a 4-bit shift register 30, an inverter 31, and an AND gate 32, and the detection pulse 1-IP' is output as an output of the logical product of G3-Ql, G2, G3, and 71+. can get. This detection pulse HP' is supplied to a horizontal period detection circuit 33, and in this circuit 33, the periodicity of the pulse HP' is detected using the clock φ2 as a time reference. As the clock φ2, a pulse with a period of approximately 1 μSec was used, similar to the tarlock φ1. The horizontal period detection circuit 33 includes, for example, a 1-bit shift register 34, a horizontal period counter 35, and an OR (OR).
It consists of a gate 36, a gate circuit 37, and an AND gate 38, and the shift register 34 receives the pulse HP'
Outputs the signal HP'' which is shifted by 1 bit.
P'' is supplied to the gate circuit 37 and the OR gate 36, and the horizontal period counter 35 is a counter for detecting the period of the pulse HP', and the horizontal period of HP' is approximately 64 μsec.
It counts whether or not it is generated every c, and is composed of a 7-bit counter using clock φ2 as a reference clock. The output of the horizontal period counter 35 and the pulse HP'' are input to the gate circuit 37, and control pulses Gl and G2 are obtained as outputs.The control pulse G1 is a periodic control pulse that controls the generation of the pulse HP', and the pulse 1 If ``P' is generated at a predetermined period, the AND gate 38 performs a logical product of G1 and HP' to detect the normal detection pulse width of the horizontal period.

The control pulse G2 is generated when the pulse HP' is not generated for a predetermined period, and the control pulse G2 is generated when the pulse HP' is not generated for a predetermined period.
6 and used to reset the horizontal period counter 35. Then, the detection pulse HP is logically ANDed with the timing pulse T1 by the AND gate 39, and is guided to the integration circuit 41. The integration circuit 41 is set to have a shorter time constant than the integration circuit 10 shown in FIG. 4, and its integration output is supplied to the slice circuit 42, where it is sliced at the voltage level y rer, and an output indicating the synchronization signal detection state is obtained. get.

FIG. 2 shows a time chart of the pulse width detection circuit 27, in which the composite synchronization signal C8 shown in FIG. 2B is input based on the clock φ1 shown in FIG. ~Q4 is shifted and output as shown in (C) to (f) in the same figure, and the AND gate output 1.
A detection pulse as shown in the same figure ((1)) is obtained as P'.

FIG. 3 shows a time chart of the horizontal period detection circuit 33, in which (a) shows the detection pulse HP', and the pulse HP' is shifted to become the pulse HP'' shown in FIG. 3(b). Also, from the gate circuit 37, the same figure (C
) and a pulse G2 indicating that the detection pulse HP' (therefore, pulse HP'') is missing as shown in (d) of the figure are output. Therefore, the pulse width detection pulse IP'
The detection pulse HPtfi having a horizontal period as shown in FIG. This detection pulse HP is obtained when the pulse train of the composite synchronization signal C8 has a predetermined pulse width and a predetermined period.

Therefore, since the noise signal mixed in the composite synchronization signal C8 is not detected, and the vertical synchronization signal portion is not detected, the integration circuit 41 does not perform the integration operation at such times, and the horizontal synchronization signal can be detected accurately.

Note that the pulse width detection circuit 29 described above can have various circuit configurations other than the specific circuit shown in FIG.
1, a pulse with a period of about 1 μsec was used, but if you want to further improve the accuracy, pulses with a period of 0°5 μsec or 0.12
A pulse of 5 μsec or the like may be used as a clock.

Further, it goes without saying that various circuit configurations are possible for the horizontal period detection circuit 33 as well.

[Effects of the Invention] As described above, according to the present invention, it is possible to accurately detect the horizontal synchronization signal without being affected by mixed noise signals or vertical synchronization signals, the constant of the integrating circuit can be shortened, and the synchronization The presence or absence of a signal can be determined in a short time. As a result, when used in a circuit that performs automatic channel selection, the present invention is highly resistant to external disturbances and the time required for channel selection can be shortened compared to the conventional one, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a synchronization signal detection circuit according to an embodiment of the present invention, FIG. 2 is a time chart of various signals in the pulse width detection circuit of FIG. 1, and FIG. 3 is a horizontal period detection circuit of FIG. 1. FIG. 4 is a block diagram of a conventional synchronizing signal detection circuit, and FIG. 5 is a time chart of various signals in FIG. 4. 21... Video signal, 22... Synchronization separation circuit,
23... Horizontal PLL circuit, 24... Phase comparator, 2
5 ・LP F, 26 ・V C01
27... Horizontal counter, 29... Pulse width detection circuit, 33... Horizontal period detection circuit, 39... AND gate, 41... Integrating circuit, 42
...Slice circuit. Figure 2 Figure 3

Claims (1)

[Claims] A synchronization separation circuit that separates a composite synchronization signal from a video signal; The composite synchronization signal is supplied as an input, and a voltage controlled oscillator generates a frequency output N times the horizontal frequency (N: a positive integer). the output is frequency-divided by 1/N by a horizontal counter, and the phase of the frequency-divided output and the composite synchronization signal is compared by a phase comparator;
a horizontal PLL circuit that controls the voltage controlled oscillator based on a DC voltage proportional to the error and locks the output of the horizontal counter to the frequency of the composite synchronization signal; and a predetermined pulse width in the pulse train of the composite synchronization signal. a pulse width detection circuit that outputs a first detection pulse for horizontal synchronization when it detects that a signal having a signal having a period of 1 is included; a horizontal period detection circuit that outputs a second detection pulse of regular horizontal synchronization when periodicity is detected; and an AND circuit that takes an AND of the second detection pulse and the timing pulse obtained from the horizontal counter. , and determining means for integrating the AND output and detecting that the integrated value is equal to or higher than a certain level to determine the presence or absence of a synchronizing signal.