KR100459453B1 - Glich removing circuit for television set - Google Patents

Abstract

The present invention relates to a technique for removing glitches incorporated in the vertical synchronization section of a television receiver. The present invention is a monostable multivibrator (1) for outputting a signal having a "low" section by a section corresponding to a predetermined time constant is triggered by the vertical dynamic period signal (VBi); A horizontal synchronous signal generator 2 for counting the horizontal synchronous signal H _sync and outputting a horizontal synchronous signal H _{sync_50} having a duty ratio 50; And the clock multiplier 3 for multiplication by the horizontal synchronizing signal (H _{sync _50)} outputs a clock signal (CK) in accordance thereto; After reset by the output signal of the monostable multi-vibrator 1 and outputs a signal of the "low" period while the predetermined value is counted by the clock signal (CK) input from the clock multiplier (3) This is achieved by the vertical inter-signal signal output section 4 which generates the vertical inter-signal signal VBi_OUT in the form of glitch removed.

Description

Glitch elimination circuit for television receivers {GLICH REMOVING CIRCUIT FOR TELEVISION SET}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for removing glitches mixed in a vertical synchronization section of a television receiver. In particular, the present invention relates to a television receiver adapted to remove glitches contained in a vertical synchronization signal extracted from video signals of various formats. It relates to a glitch elimination circuit.

In general, in the TV signal processing, the vertical synchronization signal and the horizontal synchronization signal are used to control the trace of the electron beam on the display screen. That is, the vertical synchronization signal is periodically generated so that the electron beam starts from above, and the horizontal synchronization signal is periodically generated so that scanning starts from the left side.

Meanwhile, a process of extracting the horizontal synchronizing signal and the vertical synchronizing signal by using the 480-line interlaced scanning video signal will be described with reference to FIG. 1.

As shown in FIG. 1A, the image signal, in particular, the luminance signal Y includes a horizontal synchronization signal H _sync and a vertical synchronization signal V _sync , and the luminance signal Y is sliced. The composite synchronous signal as shown in 1 (b) is obtained.

In addition, when the RC is integrated with the composite synchronization signal, a waveform as shown in FIG. 1C is obtained. The reason why the integrated signal is not smooth is that an equalization pulse of H _sync / 2 cycle is inserted in the vertical dynamic period VBi, thereby discharging the capacitor.

Since the charging time of the capacitor is longer than the discharge time, the charge accumulates in the capacitor as a whole and the charging voltage drops below the threshold voltage V _{th 1} or V _{th 2} . However, when the charging voltage drops below the threshold voltage V _{th 1} or V _{th 2} , the signal of the vertical driving mechanism VBi transitions to “low” (or “high”) as in FIG. 1 (d), In large terms, the vertical driving section is generated before the vertical driving section VBi on the input luminance signal Y ends.

However, the problem is that there is a lot of glitches (glich) is likely to occur in the vertical drive mechanism (VBi) generated as described above. For example, when the threshold voltage for the vertical driving unit VBi is set to V _th2 , after the charging voltage falls below the threshold voltage V _{th 2} , the vertical driving unit VBi is determined to be “low”. As soon as the voltage rises above the threshold voltage V _{th 2} again and falls below it, glitches are generated as shown in FIG.

As described above, the television receiver according to the prior art does not have an appropriate function for removing the glitch included in the vertical synchronism extracted from the video signals of various formats, which makes it difficult to accurately determine the format of the input video signal. There was a difficulty in displaying the original image as it is.

Accordingly, it is an object of the present invention to provide a glitch removal circuit of a television receiver that removes glitches contained in a vertical synchronous signal extracted from video signals of various formats by using a monostable multivibrator, a horizontal synchronous signal, and a clock signal. have.

Figure 1 (a)-(f) is a waveform diagram showing a synchronization signal extraction process according to the prior art.

2 is a block diagram of a glitch removal circuit of a television receiver according to the present invention;

3 is a detailed circuit diagram of a clock multiplier in FIG.

(A)-(c) is a waveform diagram of each part of FIG.

(A)-(g) is a waveform diagram of each part of FIG.

*** Description of the symbols for the main parts of the drawings ***

1: monostable multivibrator 2: horizontal synchronous signal generator

3: Clock multiplier 4: Vertical synchronizing signal output section

FIG. 2 is a block diagram showing an embodiment of a glitch elimination circuit of a television receiver according to the present invention. As shown in FIG. 2, a block corresponding to a preset time constant is triggered by a vertical dynamic period signal VBi. A monostable multivibrator 1 for outputting a signal having a low "section; A horizontal synchronous signal generator 2 for counting the horizontal synchronous signal H _sync and outputting a horizontal synchronous signal H _{sync_50} having a duty ratio 50; And the clock multiplier 3 for multiplication by the horizontal synchronizing signal (H _{sync _50)} outputs a clock signal (CK) of a frequency corresponding thereto; After reset by the output signal of the monostable multi-vibrator 1 and outputs a signal of the "low" period while the predetermined value is counted by the clock signal (CK) input from the clock multiplier (3) It is composed of the vertical inter-gauge signal output unit 4 for generating the vertical inter-gauge signal (VBi_OUT) of the glitch-free form, described in detail with reference to FIGS. As follows.

5 (a) shows an example of a vertical interlocking signal VBi including glitches at the front and the rear thereof, and these glitches may unexpectedly occur at any time.

Vertical sync signal or horizontal sync signal extraction for the classical 480i (interlace) signal is performed reliably in conventional signal processing integrated devices, but in the case of TVs associated with high-definition set-top boxes (hereinafter referred to as "set-top boxes"). The synchronization signal extracted from the 720P / 108i signal output from the set-top box is more complicated. In addition, in case of DVD 480p output, if the copy protection technique is applied, the shape of the vertical synchronization signal obtained therefrom is usually impossible to use without additional logic processing after passing through the integrator.

For reference, a problem that may occur over vertical synchronization is that an error is first caused when determining the format of an input video signal. That is, by counting one vertical synchronizing unit in units of horizontal synchronizing signal, it is possible to recognize which format the video signal is and perform signal processing suitable for the corresponding format. If there is a glitch in the vertical synchronizing unit, the counter output is absurd. It is output as a small value without the proper format recognition. In addition, when the vertical synchronism signal (actually a glitch) is input in a predetermined period and a very short period of synchronism signal is input, the reset block of the memory may fail and read / write control of the memory becomes impossible. Therefore, a situation in which an image on the screen cannot be displayed normally occurs.

Therefore, in the present invention, the glitch included in the vertical synchronizing mechanism is removed by using the glitch elimination circuit, the horizontal synchronizing signal, and the clock signal having a simple configuration.

When the vertical dynamic period signal VBi, which may include glitches, is input to the monostable multivibrator 1 as shown in Fig. 5A, the monostable stability is determined by the forward falling edge of the vertical dynamic period signal VBi. The multivibrator 1 is triggered and a "low" signal of a predetermined length starts to be output from this time. The pulse width thereof is a time constant (tau = RC) by an externally mounted resistor (R) and a capacitor (C). Is determined.

FIG. 5E illustrates an example in which the monostable multivibrator 1 generates an output signal corresponding to a case in which a glitch exists only in front of the vertical dynamic period signal VBi. As shown in FIG. The time constant (tau = RC) should be set to sufficiently cover the rear side of the vertical dynamic range signal (VBi). However, when there is a glitch behind the vertical dynamic period signal VBi, the monostable multivibrator 1 is retriggered before the "low" section is terminated by this glitch, so Similarly, a signal having a "low" section twice as large as the original low section is output.

If the output signal of the monostable multi-vibrator 1 is output as it is as a vertical dynamic period signal (VBi), the end point is often changed, which causes the start point of the frame to fluctuate so that the vertical position of the screen is shaken. do.

Therefore, in any case, it is necessary to make the end point of the vertical inter-signal signal VBi a constant position with respect to the start point, and it is the vertical inter-interval signal output unit 4 to perform this role. In other words, the counter of the vertical interlocking signal output section 4 is reset by the output signal of the monostable multivibrator 1 and then clock signal as shown in FIG. 5 (d) input from the clock multiplier 3. When the count (CK) is reached and the preset value (eg, 9) is reached, the signal “high” is started to be output. Accordingly, the vertical synchronizing period signal VBi_OUT as shown in FIG.

When setting the count value of the counter, as shown in Fig. 5B, by setting the intermediate point of the horizontal synchronization signal H _sync to be the end point of the vertical synchronization unit signal VBi_OUT, one-line jitter phenomenon In other words, it is possible to prevent the screen from appearing by including the line 1 in the new frame or by pulling it out.

On the other hand, the process of supplying the clock signal to the counter of the vertical inter-unit signal output section 4 will be described as follows.

The counter of the horizontal synchronization signal generator 2 counts the horizontal synchronization signal H _{sync as} shown in FIG. 5B and outputs the horizontal sync signal H _{sync _} 50 having a duty ratio 50 as shown in FIG. 5C. The horizontal synchronous signal generator 2 may be implemented using a monostable multivibrator or counter logic. In the logic design, a clock signal having a frequency higher than that of the horizontal sync signal H _sync may be used as the clock signal of the counter.

The clock multiplier 3 multiplies the horizontal sync signal H _{sync _} 50 having the duty ratio 50 to supply a clock signal CK as shown in FIG. _5D to the vertical inter-interval signal output unit 4. . 3 shows one embodiment of the clock multiplier 3.

That is, the horizontal sync signal H _{sync_50} having a duty ratio 50 as shown in FIG. 4A is directly supplied to one input terminal of the exclusive _oragate XOR, and is slightly delayed through the D-type flip-flop DFF. The horizontal synchronization signal H _{sync _ 50} of the previous timing as shown in FIG. 4B is supplied to the other input terminal. As a result, the multiplied clock signal CK is output from the output terminal of the exclusive or gate XOR as shown in FIG.

As described in detail above, the present invention uses a glitch elimination circuit, a horizontal synchronizing signal, and a clock signal of a simple configuration to remove glitches included in a vertical synchronizing signal extracted from various types of image signals. It is possible to accurately determine the format of the video signal, which has the effect of stably displaying the original video at the correct position.

Claims (3)

A monostable multivibrator for outputting a signal having a "low" section corresponding to a preset time constant triggered by a vertical interlocking signal; A horizontal synchronous signal generator for counting the horizontal synchronous signal and outputting a horizontal synchronous signal having a predetermined duty ratio; A clock multiplier for multiplying the horizontal synchronization signal having a predetermined duty ratio and outputting a clock signal having a corresponding frequency; A vertical dynamic period in which the glitch is removed in a manner of outputting a signal of a "low" section while counting a predetermined value as a clock signal input from the clock multiplier after being reset by the output signal of the monostable multivibrator. A glitch elimination circuit for a television receiver, comprising a signal output unit for generating a vertical driving section for generating a signal. The glitch removal circuit of claim 1, wherein the "low" section of the monostable multivibrator is configured to be set in advance by a time constant. The clock multiplier of claim 1, further comprising: a D-type flip-flop for outputting the horizontal synchronization signal having the predetermined duty ratio in a slightly delayed form in synchronization with a clock signal; And an exclusive ogate configured to output a clock signal of a multiplied form by exclusively calculating the horizontal synchronization signal having the predetermined duty ratio and the output signal of the D flip-flop.