KR0165761B1 - White border apparatus using brightness signal in hdtv - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a white border generation apparatus using a luminance signal in a wide television receiver. In the conventional art, when a video signal having a ratio of 4: 3 is displayed on a screen having a 16: 9 ratio, The present invention has a problem in that the rising edge of the reference horizontal synchronizing signal H. ref supplied in the 1 / N divider from the rising edge of the PLL and the clock oscillation signal A switching signal generator for outputting a high-level switching signal Sa at a portion where the effective screen S starts and a portion at which the effective screen S starts and ends, respectively, by applying a clock pulse CLK supplied from the switching signal generator, The luminance / color difference signal Y (U) (V) or the white border voltage Vc (Vb) (Vb) output from the clamp circuit by the signal Sa is selected, A white border is displayed on the border of the screen so that the effective screen and the blanking portion can be more effectively distinguished.

Description

A white border generator using a luminance signal in a wide television set

FIG. 1 is a circuit diagram according to an embodiment of the present invention; FIG.

Figure 2 is a timing diagram according to one embodiment of the present invention;

FIG. 3 is an exemplary view showing a screen according to the present invention; FIG.

FIG. 4 is a diagram illustrating a screen according to the conventional invention.

DESCRIPTION OF THE REFERENCE NUMERALS

11: clamp circuit 13: synchronous signal separation unit

15: PLL and clock oscillator 17: 1 / N frequency divider

19: Demodulator 21: Clamp circuit

23: Switching Signal Generator 25: Switching IC

27: R. G. B Matrix Va: Clamp voltage

SW1, SW2, SW3: Switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a white border generation apparatus using a luminance signal in a wide television receiver, and more particularly, And to a white border generating device using a luminance signal in a wide television receiver capable of inserting a white border at a boundary between blanking portions.

A typical television receiver processes a video signal input from a broadcasting station or an outside and displays it on a cathode ray tube having a 4: 3 ratio, that is, on a screen so that a viewer can view a video signal inputted from a broadcasting station or from outside.

In this way, when a video signal is displayed on a screen having a 4: 3 ratio and a video signal is viewed, there is a limitation that the number of viewable images is limited. Thus, And the video signal corresponding to the video signal is supplied from the broadcasting station or the outside to the television receiver, so that the width of the screen displayed on the screen is widened so that the video signal can be watched more realistically.

That is, the television receiver has a ratio of 16: 9. That is, a video signal inputted from the outside or a video signal transmitted from a broadcasting station forms a screen of the television receiver so that a video signal of the same ratio as the movie is displayed on the screen of the wide television receiver, So that the video signal can be watched more realistically.

However, in the wide television receiver having the ratio of 16: 9 as described above, since the video signal of FIG. 4 (a) is viewed at a ratio of 16: 9, When a video signal transmitted from a broadcasting station has a ratio of 4: 3, a video signal having a ratio of 4: 3 at the center is displayed on a screen having a ratio of 16: 9 as shown in FIG. 4 (b) A blanking portion B where a black signal is displayed is formed.

At this time, when the effective screen S of the screen on which the video signal is displayed is dark, the blanking portion B formed on the right and left sides of the screen is not distinguished from the effective screen S, The blanking portion B of the screen having the ratio is displayed in black and the effective screen S in which the video signal is output due to the increase of the ABL (Automatic Brightness Limit) voltage has a disadvantage that it becomes brighter than the actual screen.

16: 9, the problem of the above-mentioned problem caused when a video signal having a ratio of 4: 3 is viewed on the screen of the TV receiver is increased, and the viewing effect of the wide TV receiver is doubled. When a video signal having a ratio of 4: 3 is output to a screen of a television receiver having an aspect ratio of 9, a white border is inserted at the boundary between the blanking portion and the effective screen to easily distinguish the blanking portion from the effective screen It is an object of the present invention to provide a white border generation device using a luminance signal in a wide television receiver.

According to an aspect of the present invention, there is provided a video signal processing apparatus including clamping means for adjusting a level of an input video signal Vin by a clamp voltage Va, Demodulating means adapted to output a signal (U) (V), clamping means for adjusting the level of the demodulated luminance signal (Y) and color difference signal (U) (V) A synchronizing signal inherent means for separating the synchronizing signal H.sync from the synchronizing signal H.sync and outputting it to the PLL and clock oscillating means and supplying a clamp pulse to the clamping means; A PLL and a clock oscillating means for oscillating a clock pulse CLK while comparing the phase of a reference horizontal synchronizing signal H. ref of the 1 / N frequency dividing means with a clock of the PLL and clock oscillating means, Pulse (CLK) is divided by 1 / N And a 1 / N dividing means adapted to feed back a horizontal synchronizing signal (H.ref), characterized in that the rising edge of the reference horizontal synchronizing signal (H.ref) supplied from the 1 / And switching signal generating means for counting the clock pulses (CLK) supplied from the clock oscillating means and outputting a high-level switching signal (Sa) at a portion where the effective screen starts and a portion where the effective screen starts and ends, (Y) (U) (V) or white border voltage Vc (Vb) (Vb) output from the clamping means by the switching signal Sa supplied from the RG B matrix And a switching unit that is connected to the switching unit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a configuration according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, the present invention comprises a clamp circuit 11 for adjusting the level of an input video signal Vin by a clamp voltage Va, and a clamp circuit 11 for demodulating the input video signal to generate a luminance signal Y, A clamp circuit 21 for adjusting the level of the demodulated luminance signal Y and the color difference signal U (V), a demodulator 19 for outputting the signal U (V) A synchronizing signal separating unit 13 for separating a horizontal synchronizing signal H.sync from the synchronizing signal H.sync and outputting it to the PLL and clock oscillating unit 15 and supplying a clamp pulse to the clamping circuit 11, A PLL for oscillating the clock pulse CLK while comparing phases of the horizontal synchronizing signal H.sync supplied from the inverter 13 and the reference horizontal synchronizing signal H.ref of the 1 / N frequency divider 17, And a 1 / N divider 17 for dividing the clock pulse CLK of the PLL and the clock oscillating unit 15 by 1 / N to feed back the reference horizontal synchronizing signal H. ref, The clock signal CLK supplied from the PLL and the clock oscillation section 15 is counted from the rising edge of the reference horizontal synchronizing signal H. ref supplied from the 1 / N divider 17, A switching signal generator 23 for outputting a high level switching signal Sa at the beginning and end of the clamping signal S, (Y) (U) (V) or the white borderer voltage Vc (Vb) (Vb) output from the switching circuit 21 and supplies the switching IC 25 supplied to the RG B matrix 27 .

FIG. 2 is a timing diagram of waveforms output from respective nodes of a circuit diagram according to the present invention, and FIG. 3 is an example of a screen according to an embodiment of the present invention.

The operation and effect according to the embodiment of the present invention will be described as follows.

The present invention can be applied to a broadcasting station (SBS, MBC, KBS, EBS, AFKN, etc.) or an external (laser disc player, video cassette recorder, compact disc recorder, etc.) When the signal Vin is inputted to the clamp circuit 11 and the synchronizing signal separating section 13, the synchronizing signal separating section 13 outputs the horizontal synchronizing signal Sd included in the video signal Vin, (H.synce) to the PLL and the clock oscillating unit 15 so that the PLL and the clock oscillating unit 15 oscillate the clock pulse CLK while generating the clamp pulse to supply the clamp pulse to the clamp circuit 11 do.

Then, the clamp circuit 11 adjusts the clamping voltage Va so that the fetal level of the input video signal Vin is adjusted to maintain the clamp voltage Va and supplied to the demodulating unit 19, and the demodulating unit 19 The clamp circuit 21 demodulates the input video signal into a luminance signal Y and a color difference signal V and supplies the resultant signal to the clamp circuit 21. The clamp circuit 21 generates the luminance signal Y and the color difference signal V, (U) to the input terminal L of each of the switches SW1, SW2, and SW3 of the switching IC 25.

At this time, when a 4: 3 video signal is displayed on a screen having a ratio of 16: 9 to the input terminal H of each of the switches SW1, SW2 and SW3 of the switching IC 25, A white border voltage Vc (Vb) (Vb) for displaying a white border is supplied to the left and right of the video signal.

The white border voltage Vc for adjusting the luminance signal Y among the white border voltages Vc (Vb) (Vb) is output at a level capable of processing the screen as white, but the color difference signal U (V The white border voltage Vb (Vb) for adjusting the white border voltage Vb is outputted at the pedestal level in order to prevent the color signal from being displayed on the screen.

The PLL 15 and the clock oscillating unit 15 to which the horizontal synchronizing signal HSync is supplied from the synchronizing signal separating unit 13 are supplied with the horizontal synchronizing signal HSync and the 1 / N frequency divider 17 The 1 / N frequency divider 17 and the switching signal generator 23 generate a clock pulse CLK corresponding to the horizontal synchronization signal H.sync while contrasting the phase of the fed reference horizontal synchronization signal H. ref, Respectively.

Here, the 1 / N divider 17 divides the PLL and the reference horizontal synchronizing signal H. ref which is obtained by dividing the clock pulse CLK generated by the clock oscillating unit 175 by 1 / N into a PLL and a clock oscillating unit 15 The PLL and the clock oscillating unit 15 compare the phases of the reference horizontal synchronizing signal H. ref and the horizontal synchronizing signal H.sync to generate a clock pulse CLK synchronized with the horizontal synchronizing signal H.sync It will oscillate.

The switching signal generator 23 to which the reference horizontal synchronizing signal H. ref is divided by the 1 / N divider 17 is applied to the rising edge of the reference horizontal synchronizing signal H. ref shown in FIG. 2 (e) The clock pulse CLK supplied from the PLL and the clock oscillation unit 15 from the edge is counted as the image signal of 1H, that is, the blanking portion NCLK (LCLK) and the effective screen MCLK.

The switching signal generator 23 generates a low level switching signal Sa in the blanking portion NCLK as shown in (f) of FIG. 2 and outputs the low level switching signal Sa to each of the switches SW1, SW2 and SW3 of the switching IC 31, While supplying a high level switching signal Sa to the switches SW1, SW2 and SW3 of the switching IC 31 at the starting and ending points of the effective screen MCLK. Of course, during the counting of the effective screen MCLK in which the high level switching signal Sa is not generated and while counting the blanking portion KCLK, the low-level switching signal Sa is generated, And supplies it to the switches SW1, SW2, and SW3.

That is, the switching signal generator 23 counts the clock pulses supplied from the PLL and the clock oscillating unit 15 at the rising edge of the reference horizontal synchronizing signal H. ref as shown in (f) of FIG. 2, Level switching signal Sa at the instant of counting the start portion and the end portion of the switching IC 31 (in this example, the time can be adjusted according to the width of the white border, The switches SW1 and SW2 of the switching IC 31 are supplied with the output terminal of the clamp circuit 21 or the white border voltage (Vc) (Vb) (Vb).

(G) of synthesizing the video signal outputted to the clamp circuit 21 and the white border voltage Vc (Vb) (Vb) to the RG B matrix 27 for supplying the RG B signal to the cinch tube, (h) (i) is supplied, the video signal and the white border (D) are displayed together on the screen of the television receiver having the ratio of 16: 9, It is possible to view the video signal while distinguishing the blanking portion more easily.

As described above, according to the present invention, when a 4: 3 video signal is displayed on a screen of a wide television receiver having a 16: 9 screen, a blanking portion formed on the right and left sides of the screen, It is possible to view the television receiver while easily distinguishing the blanking portion from the effective screen by displaying the white border on the left and right sides of the effective screen so as to easily distinguish between the blanking portion and the effective screen.

While the present invention has been described with reference to the exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, and that various modifications and changes may be made by those skilled in the art.

Claims (1)

A clamp circuit for adjusting the level of the input video signal Vin by a clamp voltage Va and a demodulator for demodulating the input video signal to output a luminance signal Y and a color difference signal U (V) A clamp circuit for adjusting the level of the demodulated luminance signal Y and the color difference signal U; and a clamp circuit for separating the horizontal synchronization signal H.sync from the input video signal and outputting the separated horizontal synchronization signal H.sync to the PLL and the clock oscillation unit, A synchronizing signal separator for supplying a clamp pulse to the circuit; and a comparator for comparing the horizontal synchronizing signal H.sync supplied from the synchronizing signal separator and the reference horizontal synchronizing signal H. ref of 1 / A PLL and a clock oscillating unit for oscillating a clock pulse CLK while comparing phases of the clock pulses CLK and CLK and a 1 / N (1 / N) for feeding back a reference horizontal synchronizing signal H.ref by dividing the clock pulse CLK of the PLL and the clock oscillating unit by 1 / A television receiver configured with a frequency divider, wherein the reference horizontal The clock pulse CLK supplied from the PLL and the clock oscillation section is counted from the rising edge of the synchronizing signal H. ref to output the switching signal Sa at the high level at the portion where the valid screen S starts and ends, A switching signal generator; The luminance / color difference signal Y (U) (V) or the white border voltage Vc (Vb) (Vb) output from the clamp circuit is selected by the switching signal Sa supplied from the switching signal generator, And a switching IC for supplying the white signal to the matrix.