KR910007193Y1 - Start point variable circuit - Google Patents

Abstract

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Description

Display start point variable circuit of own screen

1 is a circuit diagram of the present invention.

2 is an operating waveform diagram for each part of FIG.

* Explanation of symbols for main parts of the drawings

10: multivibrator 20: clock generator

30: Register 40-42: 1-3 Logical Element

I1-I4: inverting element R1: resistance

C1: condenser

The present invention relates to a magnetic screen generating circuit in an image processing apparatus having a picture in picture (PIP) function, and particularly to a circuit capable of vertically moving the position of the magnetic screen to a desired position. It is about.

In general, the PIP function collectively refers to a technology of displaying a child screen on a single screen to represent one or a plurality of different screens by occupying some sections on one mother screen in an image processing system. However, in the conventional image processing system having the PIP function, the number of horizontal synchronization signals of the mother screen is counted by the value of a counter set to a constant value in the mother screen generation controller. Was determined. Therefore, since the occurrence position of the child screen is fixed at a certain position on the main screen, there is a problem that the external viewer cannot change the vertical position of the child screen displayed on the screen together with the main screen.

In addition, even if the vertical position is controlled from the outside, this is because the delay time (Delay Time) by the RC time constant is adjusted so that the change is large according to the ambient temperature, the position change of the sub picture cannot be changed exactly.

Accordingly, an object of the present invention is to provide a display start point variable circuit of a child screen in which an external viewer can vertically change a generation position of a child screen existing on a mother screen of an image processing system having a PIP function.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

A delay circuit comprising a plurality of inverting elements (I1-I2) for delaying and outputting the horizontal synchronization signal of the mother screen applied from the synchronization separator of the system for a first predetermined time, and the synchronization main unit applied to the clear terminal (CLR). Cleared by the vertical synchronization signal, the horizontal synchronization signal applied to the first input terminal B and the horizontal synchronization signal delayed input to the second input terminal A operate between the vertical synchronization signals of the mother screen. The multi-vibrator 10 and the horizontal synchronous signal having a resistor R1 and a capacitor C1 for generating a first pulse train having a pulse width of a second logical state which is less than the horizontal synchronization signal of the horizontal mother screen than the interval. Clock generator 20 for generating a clock pulse train of a frequency having a faster period, and the vertical synchronization signal is initialized by inputting to the reset terminal (R), and then applied by the viewer from the second predetermined number of control terminals The first pulse string input from the output terminal Q1 of the multivibrator to the input terminal D for the time specified by the fish signal to the clock pulse of the clock generator 20 applied to the clock terminal CLK. Inverted output terminal by shifting Detects an arbitrary delay time by inputting and logically multiplying the output of the register 30 and the output of the multivibrator 10 as a second input terminal and the output of the register 30 as a first input terminal. The first logical unit 40 for synthesizing the delay pulse of the second logical state corresponding to the delay time, and the output of the first logical unit 40 to the first input terminal and the clock generator 20 A second logical element 41 for inverting a clock pulse string to a second input terminal through an inverting element I3 and synthesizing a second pulse in which at least one clock pulse is applied to a delay pulse period; Vertical synchronization signal of the mother screen by performing logical AND operation by inverting the horizontal synchronization signal of the mother screen outputted from the synchronization separator to the second input terminal and inverting the output of the second logical element 41 through the inversion element I4. Next horizontal sync signal and next horizontal At least one or more in the horizontal scanning period between gisinho clock pulse occurs, the addition of the second horizontal synchronizing signal and is composed of a third logical product element (42) for outputting a PIP system controller.

FIG. 2 is an output waveform diagram for each part of FIG. 1, and in FIG. 2, VSYN is a vertical synchronization signal of the mother screen, HSYN is a horizontal synchronization signal of the mother screen, and CP is a clock pulse string of the clock generator 20. The period varies depending on the extent to which the position of the PIP screen is changed, and the period is faster than the horizontal synchronization signal corresponding to one of the number (242.5) of horizontal synchronization signals generated in one vertical synchronization signal section.

FP is the first pulse, ROS is the output of the register 30, FADS is the delay pulse of the first logical element 40, SADS is the second pulse string of the second logical element 41, IDS is The output of the inverting element I4, and FHSYN is a second horizontal synchronizing signal that is the output of the third logical element 42.

Therefore, the present invention will be described in detail with reference to FIGS. 1 and 2.

First of all, the basic concept of the present invention is to control the number of horizontal synchronization signals generated in one vertical synchronization signal section, and inserts as many clock signals as necessary for position control of the PIP into the initial part of the vertical synchronization signal. These clocks cause the PIP controller to recognize that more horizontal sync signal has occurred.

The multivibrator 10 and the register 30 in the first diagram are general circuits that are commercially available as single chip integrated circuits, and the clock generator 20 can be configured by anyone having ordinary skill in the art.

The vertical synchronization signal of the mother screen such as VSYN of FIG. 2 is applied on the line 1 from the synchronization separator of the system (not shown), and the horizontal synchronization signal of the mother screen such as HSYN of FIG. 2 is applied on the line 2. When the multivibrator 10 is cleared by the vertical synchronization signal of the low logical state mother screen applied to the clear terminal CLR through the line 1, the multivibrator 10 first outputs the horizontal synchronization signal of the mother screen on the line 2. The first pulse string is output by inputting the horizontal synchronization signal of the mother screen on the line 2 and the second input terminal A through the two inverting elements I1 and I2. Here, the delay circuit delays the first predetermined time such that the rising time of the horizontal synchronization signal input to the first input terminal B does not overlap with the horizontal synchronization signal of the second input terminal A. FIG. Therefore, when the horizontal synchronization signal of the second input terminal A maintains a low logic state, the multivibrator 10 moves the horizontal synchronization signal of the first input terminal B from a low logic state to a high logic state. At the instant of conversion, the output terminal Q1 transitions to a low logic state corresponding to the time due to the time constant of the resistor R1 and the condenser C1, that is, a time greater than 63.5 μsec, which is a period between the horizontal synchronization signals on the parent screen. A first pulse string having a second logic state, that is, a high logic state, is generated on the line 3 during the period between the horizontal synchronization signal following the vertical synchronization signal of the screen and the next vertical synchronization signal.

Here, it should be understood that the multivibrator 10 synthesizes the horizontal synchronization signal and outputs a first pulse string, so that the multivibrator 10 is used in the same manner as the term pulse synthesizing means.

On the other hand, after being initialized by the vertical synchronization signal in a low logic state applied to the reset terminal R through the line 1, the first pulse string of the multivibrator 10 is input through the line 3 to the input terminal D. Register 30 to be input to the second predetermined input (which is used as a 6-bit control terminal here) through the bus line 5 to move the viewer up and down as desired. Signal) the inverting terminal of the first pulse by the clock pulse of the clock generator 20 applied to the clock terminal CLX during the time specified by the control signal of the bit Shift output to. At this time, the clock pulse of the clock terminal CLK is the same as the CP of FIG. The signal shown in FIG. 2 is the same signal as the ROS of FIG. The ROS is applied to the first input terminal of the first logical element 40.

Accordingly, the first logical multiplier 40 logically multiplies the output of the multivibrator 10 and the output of the register 30 through the line 3 by the second input terminal, such as FADS of FIG. 2. Outputs Therefore, the FADS, which is a delay pulse having a high logic pulse corresponding to an arbitrary time delayed by the register 30, that is, a predetermined time designated by a control signal, is used as a first input terminal of the second logical element 41. Is approved.

Then, the second logical element 41 which inputs the clock pulse string on the line 4 through the inverting element I3 to the second input terminal performs logical AND operation with the delay pulse applied to the first input terminal. Generate a second pulse comprising one or more multiple clock pulses inverted during the delay pulse period, such as SADS of FIG. The second pulse is inverted through the inversion element I4 to appear as shown in FIG. 2 as an IDS, which is applied to the first input terminal of the third logical element 42.

In this case, the third logical element 42 for inputting the horizontal synchronization signal of the mother screen on the line 2 is logically multiplied with the second pulse inputted to the first input terminal through the inversion element I4. A second horizontal synchronizing signal such as 2 degrees FHSYN is generated and output to the counter of the PIP system controller.

Here, it is to be understood that the 1-3 logical AND elements I3 and I4 are used in the same manner as the second horizontal synchronizing signal synthesizing means because they are used as means for generating the second horizontal synchronizing signal. Accordingly, the PIP system controller generates a magnetic screen on the horizontal scan line vertically moved upward by the number of clock pulses added from the existing generation position by the second horizontal synchronization signal.

As described above, the present invention has an advantage that the viewer can stably adjust the vertical position of the user screen using a digital circuit.

Claims (2)

A PIP image processing apparatus having a synchronization separator for outputting vertical and horizontal synchronization signals of a mother screen and a PIP system controller, wherein the vertical synchronization signal and the horizontal synchronization signal of the mother screen are inputted and the interval between the vertical synchronization signals of the mother screen is input. A pulse synthesizing means for outputting a first pulse string in a second logical state which is smaller than the horizontal synchronizing signal period of the mother screen, a clock generator 20 for generating a clock pulse having a frequency faster than the horizontal synchronizing signal; After the initialization is initiated by the vertical synchronization signal, the first pulse train is shifted by the clock pulse applied to the clock terminal CLK and inverted for a time designated by the control signal applied by the viewer from the second predetermined constant control terminal. Output terminal The vertical synchronization by inputting the register 30, the horizontal synchronization signal of the mother screen of the synchronization separator, the first pulse of the pulse synthesizing means and the clock pulse of the output of the register 30 and the clock generator 20 through And a second horizontal synchronizing signal synthesizing means for outputting a second horizontal synchronizing signal to which the at least one clock pulse is added between the horizontal synchronizing signal following the signal and the next horizontal synchronizing signal to the P1P system controller. Display start point variable circuit. The first logical unit (40) according to claim 1, wherein the second horizontal synchronizing signal synthesizing means performs a logical multiplication on the first pulse string of the pulse synthesizing means and the output of the register (30), and the first logical product. A second logical element 42 for performing an AND operation on the output of the element 40 and the clock pulse sequence inverted by the inverting element I3, and the second inverted by the horizontal synchronous signal and the inverting element I4. And a third logical element (42) for outputting the second horizontal synchronization signal by logically multiplying the output of the two logical element (41).