JPH11275383A - Synchronizing signal separation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a circuit which separates, extracts and outputs a vertical synchronizing signal with a precise voltage level output timing by providing an up/down counter that stops up-counting or down-counting after reaching predetermined values of upper or lower limits and obtaining the vertical synchronizing signal separated owing to an output of a carry signal. SOLUTION: A synchronizing signal separation circuit is provided with an up/down counter 2 which outputs a carry signal as a counter output when its counted value reaches a predetermined upper limit, and does not count up or count down thereafter. The counter 2 executes down-count when the value of a binarized composite synchronizing signal is high and executes up-count when it is low. A binarizing means 1 is provided with a clamp 101 and a comparator 102 which compares the signal voltage level with a prescribed threshold.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronizing signal separating circuit for separating a synchronizing signal from a signal having disturbance such as noise.

[0002]

2. Description of the Related Art A vertical synchronizing signal is separated and extracted from a video composite signal used for a television or the like and detected. Based on the detection of the vertical synchronizing signal, for example, a television video signal is synchronized or a TV tuner is used. A synchronization signal separation circuit is used to search for an optimal diversity antenna when detuning and to take timing of switching.

As a conventional technique for separating and extracting such a vertical synchronizing signal, for example, as shown in FIG. 6, a received or input video composite signal is first clamped by a clamp 901 and then a limiter or the like is used. The video signal is deleted from the signal (not shown), and a binarized composite synchronization signal is obtained. The composite synchronization signal is a digital signal in a state where the horizontal synchronization signal and the vertical synchronization signal are mixed (that is, a composite state).

After the composite synchronizing signal is inverted through an inverter (inverting circuit) 902, a low-pass filter for vertical synchronizing signal (hereinafter referred to as V-LPF) V-
By passing through the LPF 903, the frequency difference is replaced with the level difference. At this time, although the voltage of the signal input to the V-LPF 903 changes stepwise,
The level of the output (Vout) at 903 changes exponentially as shown in an example in FIG.

Since the rate of this rise varies due to the variation in the time constant of the V-LPF 903 as shown in FIGS. 7 (a), 7 (b) and 7 (c), it is connected to the subsequent stage of the V-LPF 903 and finally becomes vertical. Comparator 904 that outputs a synchronization signal
Is significantly affected by the variation (change) of the time constant in consideration of the threshold value of the comparator 904 itself.

For example, in the case shown in FIG. 7, when the threshold value of the comparator 904 is low (V1), V-LP
Assuming that the variation of the time constant of F903 is as shown by a to c in the figure, the output of the comparator 904 at that time is in the range shown by a in FIG. Similarly, when the threshold value is high (V2), it becomes the range indicated by b in FIG.

Therefore, when the threshold value is set to a high value (for example, V2), the output timing of the comparator 904 may be largely shifted due to the variation (change) of the time constant of the V-LPF 903. There's a problem. On the other hand, when the threshold value is set to a low value (for example, V1), the small random noise having such a narrow width is also picked up because it reacts to small random noise having a small width. As a result, there is a problem that accurate separation and extraction of only the vertical synchronization signal are prevented.

Also, instead of lowering the threshold value, V-L
If the time constant of PF903 is increased (d in FIG. 7),
Although the cutoff is reduced, noise is enhanced, but on the other hand, there is a problem in that it is disadvantageous in terms of variation in time constant. In FIG. 6, reference numeral 905 denotes a phase comparison circuit; 906, a low-pass filter (LPF);
It is needless to say that VCO 908 is a frequency dividing circuit, and these form a horizontal synchronizing signal separating circuit.

As a method of synchronizing signal separation, there is another method using a pure digital method as shown in FIG. 8, for example. That is, after the input composite signal is clamped by the clamp circuit 1101 and the output of the result compared with the predetermined threshold value by the comparator 1102 enters the counter 1103 at the subsequent stage, a delay D as shown in FIG. Let it. Then, based on the timing, the composite synchronization signal is sampled to detect the vertical synchronization. Generally, by using such a pure digital method, the configuration of the circuit system is changed to the analog system as described above. This is advantageous in that it can be simplified as compared with the case.

However, in such a pure digital vertical synchronization signal separation technique, the S / S
It works as expected when the N ratio is good, but has the disadvantage that malfunctions are likely to occur due to random noise at the time of weak input etc. For example, mobile communication and in-vehicle TV receivers
When used in applications where the reception environment is liable to change, there is a tendency that out-of-synchronism tends to occur, and there is a problem that practicality is practically difficult.

In terms of the occurrence of a malfunction due to such random noise, the above-described analog system is more resistant to noise.

[0012]

As described above, the V-LPF 903 and the comparator 904 are different from those of the prior art.
In the synchronization signal separation circuit formed by combining the above, it is impossible to accurately separate and extract the synchronization signal due to noise, and a large deviation in output timing occurs due to a variation in time constant. There was a problem.

Since the problem of noise and the problem of output timing shift are in a trade-off relationship with each other, it is extremely difficult and practically impossible to solve the problem so that they are compatible with each other. It was possible. Further, even if the threshold value of the comparator 904 can be set to a value that can be compromised in terms of the balance between the time constant variation and the output timing shift, the voltage level of the composite synchronization signal input to the V-LPF 903 is not For example, it is clear from FIG. 7 that when the output timing changes due to a weak input or the like, the output timing also changes due to the influence.

That is, according to the conventional technique, even if the voltage level of the composite synchronization signal changes, the output timing at that time shifts, and it becomes impossible to separate and extract the vertical synchronization signal at accurate timing. There was a problem. Further, in the case of a pure digital system as shown in FIG. 8, the circuit system as a whole can be simplified, but there is a problem that it has a decisive disadvantage that it is weak against noise.

The present invention has been made to solve such a problem. SUMMARY OF THE INVENTION It is an object of the present invention to provide a synchronizing signal separating circuit capable of separating and extracting a vertical synchronizing signal having an accurate voltage level and an accurate output timing and outputting the same.

[0016]

According to a first aspect of the present invention, there is provided a synchronizing signal separating circuit for separating a vertical synchronizing signal from a composite synchronizing signal. Means for counting up and down by associating an up-count with one of the values of the binarized composite synchronization signal and a down-count with the other.
A counter that outputs a carry signal as a counter output when the count value counted by the count reaches a specified upper limit value, and increases the count value after the count reaches the specified upper limit value or the specified lower limit value. An up / down counter that does not perform counting or down counting is provided, and the vertical synchronization signal separated by the output of the carry signal is obtained.

Secondly, in a synchronizing signal separating circuit for separating a vertical synchronizing signal from a composite synchronizing signal, a binarizing means for binarizing the composite synchronizing signal, and a value of the binarized composite synchronizing signal An up / down counter for executing a count by associating one with an up-count and the other with a down-count, wherein when the count value counted by the count reaches a lower limit specified value, a borrow is output as a counter output. A signal, and an up / down counter that does not perform the up-count or the down-count after the count reaches the specified value of the lower limit or the specified value of the upper limit, and is separated by the output of the carry signal. The method is characterized in that the vertical synchronization signal is obtained.

Thirdly, in the synchronization signal separating circuit according to the first or second aspect, the prescribed value of the upper limit is a count value at which the count-up of the up / down counter overflows, and the prescribed value of the lower limit is defined. The value is a count value at which the count up of the up / down counter underflows.

Fourthly, in the synchronization signal separating circuit according to the first or third aspect, the up / down counter counts down when the value of the binarized composite synchronization signal is High. It is characterized by an up / down counter that executes, and in the case of Low, executes an up-count.

Fifth, in the synchronization signal separating circuit according to the second or third aspect, the up / down counter counts up when the value of the binarized composite synchronization signal is High. It is characterized by an up / down counter that executes and counts down when it is low.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a synchronizing signal separating circuit according to the present invention. As shown in FIG. 1, the synchronizing signal separating circuit is a synchronizing signal separating circuit for separating a vertical synchronizing signal from a composite synchronizing signal, and includes a binarizing means 1 for binarizing the composite synchronizing signal, An up / down counter 2 for executing a count by associating an up-count with one of the values of the digitized composite synchronization signal and a down-count with the other, wherein the count value counted by the count is an upper limit. An up / down counter 2 that outputs a carry signal as a counter output when the count reaches a specified value and does not perform the up-count or the down-count after the count reaches the specified upper limit or the specified lower limit.
And a synchronizing signal separating circuit for obtaining the vertical synchronizing signal separated by the output of the carry signal.

Further, the prescribed value of the upper limit is a count value at which the count-up of the up / down counter 2 overflows, and the prescribed value of the lower limit is a value at which the count-up of the up / down counter 2 underflows. Count value.

Still further, the up / down counter 2 is configured to determine whether the value of the binarized composite synchronization signal is Hig.
The up / down counter 2 executes a down count in the case of h and performs an up count in the case of low. More specifically, the binarizing means 1 includes a clamp 101 and a comparator 102 to clamp a composite signal input from outside (not shown) to the clamp 10.
After clamping at 1, the signal voltage level is compared with a predetermined threshold by the comparator 102 to determine whether to output. The output of the comparator 102 is supplied to the UP / DOWN input terminal 20 of the up / down counter 2.
1 is input.

Here, C of the up / down counter 2
A reference clock signal is input to the LK terminal 203 from outside (not shown), and operates as a time counter inside the up / down counter 2. That is, the reference clock signal is used as a reference clock for the following count operation.

When the signal input to the UP / DOWN input terminal 201 is High, the up / down counter 2 performs down counting. Also UP
When the signal input to the / DOWN input terminal is Low, the up / down counter 2 performs up-counting.

On the other hand, a control signal for loading a preset value and controlling whether or not to perform a count operation is input to the LD terminal 202 of the up / down counter 2 from outside (not shown). Here is Low
Load is performed by (L), and counting is performed by High (H).

When the counter reaches the upper limit specified value (ie, overflow, in other words, the state of all bits High), a carry signal (or borrow terminal; this borrow terminal will be described later) 204 and a carry signal (hereinafter, referred to as a borrow terminal). Carry) is output.

This carry corresponds to the output of the comparator in the conventional analog type synchronizing signal separation circuit (that is, the output of the comparator 904 in the conventional synchronizing signal separation circuit as shown in FIG. 6). That is, by outputting this carry, the vertical synchronization is detected.

In the conventional general up / down counter, when an up-count is further applied after all the bits become H, the count value at that time returns to 0. Further, after the count value becomes 0, when the down count is further applied, the count value at that time becomes the count value of all the bits H. This is shown in FIG.

Therefore, when the characteristics of the conventional up / down counter are used, if noise such as the example shown in FIG. The count value deviates from the correct value due to noise, and in particular, the time at which all the bits become H deviates, making it impossible to carry out the correct time counting, so that accurate detection of vertical synchronization becomes impossible.

Therefore, in the up / down counter 2 according to the present invention, overflow, that is, all bits H
After that, even if an up-count is applied, it is not executed, and the count value of all the bits H is maintained, and when a down-count is applied, it is executed. If an underflow occurs, that is, all bits L have been reached, even if a down-count is applied, this is not executed even if the count value of all the bits L is maintained while the down-count is applied. Therefore, by employing such a counting method, it is possible to perform counting without resetting the count in the middle as schematically shown in FIG.

Up / down counter 2 as described above
FIG. 2 shows an example of the operation of FIG. In FIG. 2, (a) schematically shows the output signal of the comparator 102 obtained by binarizing the composite signal, and (b) schematically shows the count value up / down and carry output in the form of a timing chart. I have.

FIG. 2 shows an example of a signal waveform in the vicinity of the vertical blanking period. In the case of a genuine waveform having no random noise or the like mixed therein, the composite signal is represented by 2 signals.
At the stage where three pulses of the short duty H pulse in the output signal of the comparator 102 are inputted, a carry is output.

That is, as clearly shown in FIG. 2, the signal is inputted to the LD terminal 202 about 2H or 3H before a predetermined time (for example, 525H in the case of the NTSC system) elapses from the previous detection of the vertical synchronization. The load is set to H based on the control signal, and counting is started. When the load is started, the counter is set to the preset value (preset value)
From the start, the up-count is executed one count at a time when the signal is L, and the down-count is executed one count at a time when the signal is H.

The time t until the carry is output
Is t = (UD) · T · (M−, where U is the up-count number, D is the down-count number, T is the clock cycle, M is the maximum count value of the counter, and P is the preset value.
P), the detection time t can be set by changing the setting of the preset value.

Here, if the S / N ratio of the composite signal is lowered due to, for example, deterioration of the reception environment, and noise is mixed into the output signal of the comparator 102 due to its adverse effect, the noise Is mixed as a digital H or L level signal in the digital signal, the noise is counted by a conventional general up / down counter. Was to cause disengagement.

However, in the up / down counter 2 according to the present invention, for example, as shown in FIG. 4, even if random noise is mixed in the output of the comparator 102, the time for continuing counting is increased. By setting, the adverse effect of the noise can be reduced. That is, in the conventional analog type synchronizing signal separation circuit, there is a restriction in setting a long integration time, but in the synchronizing signal separation circuit according to the present invention, there is substantially no such restriction because it is a pure digital type. In other words, as described above, the output of the carry or borrow is used as the detection of vertical synchronization,
Since there is no direct adverse effect on the detection accuracy due to the variation of the threshold value itself or the variation of the time constant of the comparator 904 as in the analog system, more accurate detection accuracy can be obtained.

That is, when there is no disturbance, the up-count period is 29.5 in the period where the Sync of the vertical blank is wide (such as the period indicated by the symbol A in FIG. 4).
μs and the down-count period is 2.3 μs (NTS
C). During the period of the total of 31.8 μs, if the total period during which the count is disturbed by the disturbance becomes 13.6 μs or more, which is half of the total of 31.8 μs, the total time of the down-count becomes more than the total time of the up-count. Therefore, the count value goes in the negative direction, and the count becomes substantially impossible. S corresponding to 13.6 μs which is the critical value of such a state
The / N ratio is S / N = 7.4 dB.

Actually, the condition that the carry is output within the period in which the count is permitted must be satisfied, so that the S / N ratio must be slightly higher than this.
If the count time is set long (2 to 3H; H is the horizontal synchronization time), the S / N ratio can be detected up to about 8 dB, and the vertical synchronization can be detected.

In the analog system, it is possible to detect up to about 12 dB in video S / N ratio, but below that, it becomes impractical. However, according to the present invention, it is possible to detect up to about 8 dB as described above, so that it is resistant to noise.
However, the S / N ratio in this case is on the time axis, and the value of the S / N ratio in the video composite is calculated by the amplitude ratio. Although it is not possible to do so, it is needless to say that comparisons may be made on the basis of the same reference in practice.

Further, according to the present invention, as described above, even if random noise is mixed, it is possible to set the time to continue counting as described above to reduce the adverse effect of the noise. ADVANTAGE OF THE INVENTION According to the technique which concerns on this invention, the simplification of the circuit structure can be implement | achieved by employ | adopting a pure digital system, and more accurate detection accuracy can be obtained.

In the above, as the most typical embodiment of the technology according to the present invention, the up / down counter 2 outputs a carry signal as a counter output when the count value reaches a specified upper limit value, The case of the synchronization signal separation circuit for obtaining the vertical synchronization signal separated by the output of the carry signal has been described. That is, in the above embodiment, the case where the count to output rule that a carry signal is output as the counter output when the count value reaches the upper limit specified value as a result of the count value increasing in the upward direction is described. The applicable rules of the up / down counter 2 to output rules include:
In addition to the above, it is also possible to use a count-output rule in which a borrow signal is output as a counter output when the count value reaches a lower limit specified value as a result of the count value increasing in the down direction. Since the borrow signal is output from the carry terminal 204, it goes without saying that in this case, the carry terminal 204 should rather be called the borrow terminal 204. Further, in this case, in the timing charts shown in FIGS. 2B, 3, and 4B, the vertical relationship of the vertical axis is not changed, and the shape of the graph of the timing chart of the count value is changed in the vertical relationship. It is needless to say that the device operates as if it were reversed.

That is, the preset value is set to the highest value. Starting from this preset value, FIG.
And when the value of the binarized composite synchronization signal is Low as shown in FIG.
In the case of gh, it counts up. When the count value gradually increases in the down direction and reaches the lower limit specified value, a borrow signal is output from the borrow terminal 204 as a counter output. Then, by outputting this borrow signal, vertical synchronization is detected. As described above, even when the borrow signal is used, the same operation and effect as described above can be realized.

[0044]

As described above in detail, according to the present invention, first, in the synchronization signal separation circuit for separating the vertical synchronization signal from the composite synchronization signal, the composite synchronization signal is binarized. And an up / down unit that performs counting by associating one of the values of the binarized composite synchronization signal with an up-count and the other with a down-count.
A down counter, and outputs a carry signal as a counter output when the count value counted by the count reaches a specified upper limit, and after the count reaches the specified upper limit or the specified lower limit, Providing an up / down counter that does not perform the up-counting or the down-counting causes a problem that accurate synchronization signals cannot be separated and extracted due to noise and an output timing due to a variation in time constant. Can be solved.

Further, it is possible to solve the problem that even if the voltage level of the composite synchronizing signal changes only, the output timing at that time shifts, and the vertical synchronizing signal cannot be separated and extracted at accurate timing. Can be. Further, it is possible to simplify the entire circuit system by using a purely digital method, and to solve the problem that such a purely digital method has a decisive disadvantage of being susceptible to noise. be able to.

Secondly, in a synchronizing signal separating circuit for separating a vertical synchronizing signal from a composite synchronizing signal, a binarizing means for binarizing the composite synchronizing signal; An up / down counter for executing a count by associating one of the values with an up-count and the other with a down-count, wherein when the count value counted by the count reaches a lower limit specified value,
A borrow signal as a counter output, and an up / down counter that does not perform the up-count or the down-count after the count reaches the lower limit or the upper limit. Thus, it is possible to solve the problem that accurate separation and extraction of the synchronization signal cannot be performed, and that the output timing is largely shifted due to the variation of the time constant.

Further, it is possible to solve the problem that even if the voltage level of the composite synchronizing signal changes only, the output timing at that time shifts, and it becomes impossible to separate and extract the vertical synchronizing signal at accurate timing. Can be. Thirdly, in the synchronization signal separating circuit according to the first or second aspect, the prescribed value of the upper limit is the up /
The count value at which the count-up of the down counter overflows is a count value at which the count-up of the up / down counter underflows, and the prescribed value of the lower limit is a count value at which the count-up of the up / down counter underflows, as shown in FIG. Such a disadvantage of the conventional counter can be solved to solve the problem of the loss of synchronization.

Fourthly, in the synchronization signal separation circuit according to the first or third aspect, the up / down counter counts down when the value of the binarized composite synchronization signal is High. It is characterized by an up / down counter that executes and counts up when it is low, thereby eliminating the drawbacks of the conventional counter as shown in FIG. 5 and solving the problem of loss of synchronization. can do.

Fifth, in the synchronization signal separation circuit according to the second or third aspect, the up / down counter counts up when the value of the binarized composite synchronization signal is High. It is an up / down counter that executes and counts down when it is low, thereby eliminating the drawbacks of the conventional counter as shown in FIG. 5 and solving the problem of loss of synchronization. can do.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a main part of a synchronization signal separation circuit according to the present invention.

FIG. 2 is a diagram showing an example of the operation of the main part of the synchronization signal separation circuit according to the present invention, particularly from the count operation to the carry output operation.

FIG. 3 is a diagram schematically showing characteristics of an up / down counter according to the present invention.

FIG. 4 is a diagram illustrating an example of a case where noise is mixed in a comparator output in the synchronization signal separation circuit according to the present invention.

FIG. 5 is a diagram schematically showing characteristics of a conventional up / down counter.

FIG. 6 is a diagram illustrating an output of a comparator 904 in a synchronization signal separation circuit according to the related art.

FIG. 7 is a diagram showing an example of an output after clamping in a conventional analog synchronization signal separating circuit and a problem thereof.

FIG. 8 is a diagram showing an example of a configuration of a main part of a conventional pure digital type synchronization signal separation circuit.

FIG. 9 is a timing chart showing an example of a signal waveform used in a main part of a conventional pure digital synchronization signal separation circuit.

[Description of Signs] 1 ... Binarization means 2 ... Up / Down counter 101 ... Clamp 102 ... Comparator 201 ... UP / DOWN input terminal 202 ... LD terminal 203 ... CLK terminal 204 ... Carry / borrow terminal

Claims (5)

[Claims] 1. A synchronizing signal separating circuit for separating a vertical synchronizing signal from a composite synchronizing signal, wherein: a binarizing means for binarizing the composite synchronizing signal; An up / down counter for executing a count by associating an up-count with a down-count, and outputs a carry signal as a counter output when the count value counted by the count reaches an upper limit prescribed value. And an up / down counter that does not perform the up-count or the down-count after the count reaches the specified value of the upper limit or the specified value of the lower limit, and the vertical synchronization signal separated by the output of the carry signal. A synchronization signal separation circuit. 2. A synchronizing signal separating circuit for separating a vertical synchronizing signal from a composite synchronizing signal, wherein: a binarizing means for binarizing the composite synchronizing signal; An up / down counter for executing a count by associating an up count with a down count, and outputs a borrow signal as a counter output when a count value counted by the count reaches a lower limit specified value. And an up / down counter that does not perform the up-counting or down-counting after the count reaches the specified value of the lower limit or the specified value of the upper limit, and the vertical synchronization separated by the output of the borrow signal. A synchronizing signal separating circuit for obtaining a signal. 3. The synchronization signal separating circuit according to claim 1, wherein the prescribed value of the upper limit is a count value at which a count-up of the up / down counter overflows, and the prescribed value of the lower limit is the prescribed value of the lower limit. A synchronization signal separating circuit, wherein the count-up of the up / down counter is a count value underflowing. 4. The synchronization signal separation circuit according to claim 1, wherein the up / down counter executes a down count when the value of the binarized composite synchronization signal is High, and is low. A synchronous signal separating circuit, which is an up / down counter for executing an up count in the case of (1). 5. The synchronization signal separating circuit according to claim 2, wherein the up / down counter executes an up-count when the value of the binarized composite synchronization signal is High, and the Up / Down counter performs Low. A synchronous signal separating circuit, which is an up / down counter for performing a down count in the case of (1).