JP2016163334A - Synchronous signal generation device, synchronous signal generation method, video processing apparatus and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time required for discriminating pull-in completion of an input/output synchronous signal.SOLUTION: A synchronous signal generation device is capable of changing a positional relation between timing of an input synchronous signal and timing of an output synchronous signal by correcting a period of the output synchronous signal. The synchronous signal generation device discriminates whether the timing of the input synchronous signal can be pulled into an interval of a predetermined phase that is determined by the period of the output synchronous signal and corrects the period of the output synchronous signal. If it is discriminated that the timing of the input synchronous signal can be pulled into the interval of the predetermined phase, it is discriminated whether the timing of the input synchronous signal is pulled into the interval of the predetermined phase after the period of the output synchronous signal is corrected.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a synchronization signal generation technique, and more particularly to a technique for supplying a synchronization signal to a video processing apparatus that displays and processes moving images.

  Video processing apparatuses represented by monitor displays are widespread. Some of these devices are devised so as to reduce the delay time from input to output. For example, when these devices are used as a display device for a game or the like, a screen on which an operation input is fed back is displayed on the display device. Since the user feels uncomfortable when the time until feedback is long, the display is configured to reduce delay due to internal processing. For example, in a display device, the number of frame buffers and the number of stages of line buffers for temporarily storing a screen are minimal.

  Some of these devices have a mechanism for synchronizing input and output frame frequencies. Since a display panel that outputs video has a timing specification required for each device, these devices are driven at a frame frequency in accordance with the timing specification. On the other hand, since the input video has various image formats such as VGA and XGA, it can have different frame frequencies. When the input and output frame frequencies are different, screen disturbances such as frame skipping and tearing occur in the displayed video. Tearing is a phenomenon in which a plurality of frames are displayed on one screen, so that the top and bottom of the screen are shifted in the horizontal direction or flicker.

  In order to prevent tearing, a mechanism (frame lock mechanism) that synchronizes the input / output frame frequencies, that is, pulls in the input / output synchronization signals is necessary. There is also a method of displaying an image after frame buffering, but the delay between input and output becomes large. Therefore, a process is performed in which the frame buffered image is displayed during pull-in, and the display mode is switched to a display mode in which frame buffering is not performed when pull-in is completed.

  As a method for pulling in an input / output synchronization signal, for example, a method described in Patent Document 1 has been devised. In the method of Patent Document 1, when an input is generated within the correction range of the frame lock mechanism, the period of the input synchronization signal and the phase difference between the input and output synchronization signals are detected, and the output synchronization signal This is a method for controlling the cycle. According to this method, the pull-in is completed when the input / output phase difference becomes small.

Japanese Patent No. 5284304

  However, in the method described in Patent Document 1 described above, complicated control is required when an input outside the correction range is assumed, and there is a problem that it takes a long time to determine completion of pull-in. . In the case of an input outside the correction range, the phase difference between the input and output synchronization signals cannot be stabilized, so that control different from the input within the correction range is required. In addition, in order to determine that it is outside the correction range, complicated control such as collecting a long history is required. For this reason, it takes time to cancel the display mode (frame buffering mode) for preventing tearing.

  The present invention has been made in view of the above-described problems, and an object thereof is to shorten the time for determining completion of input / output synchronization signal pull-in.

  As a means for achieving the above object, a synchronization signal generating apparatus of the present invention has the following configuration. That is, a synchronization signal generating device capable of changing the positional relationship between the timing of the input synchronization signal and the output synchronization signal by correcting the cycle of the output synchronization signal, wherein the timing of the input synchronization signal is changed to the cycle of the output synchronization signal The first determination means for determining whether or not it is possible to pull in the section of the predetermined phase determined by the correction, the correction means for correcting the period of the output synchronization signal, and the input synchronization signal by the first determination means When it is determined that the timing of the output synchronization signal can be drawn into the predetermined phase interval, the timing of the input synchronization signal is set to the predetermined phase interval after the correction means corrects the cycle of the output synchronization signal. And second determination means for determining whether or not it has been retracted.

  According to the present invention, it is possible to shorten the time for determining completion of input / output synchronization signal pull-in.

FIG. 3 is a diagram illustrating a functional block configuration of a synchronization signal generation unit according to the first embodiment. 2 is a diagram illustrating an example of a hardware configuration of a video processing apparatus according to Embodiment 1. FIG. 1 is a diagram illustrating a functional block configuration of a video processing apparatus according to a first embodiment. FIG. 3 is a timing diagram of frame lock of the video processing apparatus according to the first embodiment. FIG. 3 is a timing chart of input switching processing of the video processing apparatus according to the first embodiment. FIG. 6 is a diagram illustrating an operation example of pull-in determination of the synchronization signal generation unit according to the first embodiment. 5 is a flowchart showing control of pull-in determination of the synchronization signal generation unit according to the first embodiment. The figure which shows the functional block structure of the synchronizing signal generation part of Embodiment 2. FIG. The figure which shows the operation example of the lead-in determination of the synchronous signal generation part of Embodiment 2.

  Hereinafter, the present invention will be described in detail based on preferred embodiments with reference to the accompanying drawings. The configurations shown in the following embodiments are merely examples, and the present invention is not limited to the illustrated configurations.

[Embodiment 1]
In this embodiment, when the movement amount of the input synchronization signal with respect to the output synchronization signal (the output synchronization signal and the input synchronization signal are generated independently and periodically) is equal to or less than the frame lock control correction amount, An example will be described in which it is determined that “pull-in is completed” when the pull-in is possible and the position of the input synchronization signal is within the lock window. In the present embodiment, “pull-in” represents processing for generating the timing of the input synchronization signal in a section of a predetermined phase based on the output synchronization signal, and this processing is realized by correcting the period of the output synchronization signal. The By completing the “drawing”, it is possible to display the image data of the same frame in the first half and the second half of the effective image area where the video data is displayed (output).

<Configuration of Video Processing Device (FIGS. 2 and 3)>
FIG. 2 is a diagram illustrating an example of a hardware configuration of the video processing apparatus according to the present embodiment. The video processing apparatus in the present embodiment is a monitor display that displays an image on a display panel (display unit 25). The control unit 21 is a CPU, for example, and controls the operation of each component. The ROM 22 stores control instructions, that is, programs. The RAM 23 is used for temporary storage of work memory and data when executing the program. The communication unit 24 performs control for communicating with an external device. The display unit 25 performs various displays. The display unit 25 includes a display panel that displays image data. The display panel may be configured by an LCD, plasma, CRT, organic EL, or the like, or may be a projection type display device that projects onto a wall surface. A user I / F (interface) 26 receives user operations.

  FIG. 3 is a diagram illustrating an example of a functional block configuration of the video processing apparatus according to the present embodiment. The video input unit 31 receives input of video content from the outside. The video input unit 31 is provided with three ports “input 1”, “input 2”, and “input 3” as input interfaces, and input is performed from one selected input port. The input interface accepts video content of various standards such as HDMI, DVI, DisplayPort, analog video, and the like. The video input unit 31 converts the input video content into a format of uncompressed digital data to which a synchronization signal is attached and outputs the converted data to the frame buffer 32, the video switch 33, and the synchronization signal generation unit 35.

  The frame buffer 32 buffers image data in units of frames. For example, the frame buffer 32 includes a buffer capable of storing frames for two screens, and input image data is alternately written. The image processing apparatus 1 can perform display without tearing by reading out the image data of the screen on which writing has not been performed and using it for display.

  The video switch 33 receives both the image data that does not pass through the frame buffer 32 and the image data that passes through the frame buffer 32, and selects one of the image data based on the signal input from the switching control unit 36. Output. The display unit 34 includes a display panel that displays image data, and corresponds to the display unit 25 of FIG. The synchronization signal generation unit 35 generates a synchronization signal for driving the display unit 34. As shown below, the synchronization signal includes a vertical synchronization signal, a horizontal synchronization signal, an effective image area signal, a lock window signal, and the like.

  According to the state of the signal generated by the synchronization signal generation unit 35, the switching control unit 36 should select either the image data that the video switch 33 does not pass through the frame buffer 32 or the image data that passes through the frame buffer 32. Generates and outputs a signal indicating whether or not Specifically, when the input frequency is a frequency that cannot be frame-locked, the switching control unit 36 generates a signal instructing to select an image via the frame buffering 3. On the other hand, when the input frequency is a frame lockable frequency but the input / output frequency is not frame locked, the switching control unit 36 generates a signal instructing to select an image via the frame buffering 3. To do. When the input frequency is a frequency that can be frame-locked but the input / output frequency is frame-locked, the switching control unit 36 generates a signal indicating that an image that does not pass through the frame buffer 32 is selected. The switching control unit 36 outputs the generated signal to the video switch 33.

<Frame lock operation (FIG. 4)>
Next, frame lock control in the synchronization signal generator 35 will be described. FIG. 4 is a timing chart showing a state of frame lock. The output vertical synchronization signal 40 (output Vsync), the effective image area signal 41, and the lock window signal 42 are signals generated by the synchronization signal generation unit 35. Among these, the output vertical synchronization signal 40 (output Vsync) indicates the start timing of the output image frame. The valid image area signal 41 indicates the timing at which valid image data is sent. A section 46 having a logic H represents an effective timing. The lock window signal 42 indicates a predetermined phase to be pulled in by the frame lock function. A section 47 having a logic H represents a lock phase. This lock phase is determined by the period of the output vertical synchronization signal 40. Input vertical synchronization signals 43 to 44 (input Vsync) indicate the start timing of the image frame input in each case (1) to (2).

  In the case of the input vertical synchronization signal 43 which is the first case, the pulse 48 of the input Vsync is at a position away from the lock phase 47. This means that the frame lock is released and the state is “retracting”. On the other hand, the pulse 48 of the input Vsync is at a position where it interferes with the section 46 where the effective image area signal 41 is logic H. In the case of a configuration in which video data is output without going through the frame buffer 32, images of different frames are displayed in the first half and the second half of the effective image area. As a result, the display unit 34 displays an image in which tearing has occurred at the top and bottom of the display screen.

  In the case of the input vertical synchronization signal 44 which is the second case, the pulse 49 of the input Vsync is at the position of the lock phase 47. This means that it is in the “retraction complete” state where the frame lock has been completed. The pulse 49 of the input Vsync does not interfere with the section 46 in which the effective image area signal 41 is logic H. Since the same frame image can be displayed in the entire effective image area, tearing does not occur on the display screen. As in the second case, the video processing apparatus according to the present embodiment performs display by drawing the input Vsync into a predetermined lock phase 47.

<Configuration of Sync Signal Generation Unit (FIG. 1)>
FIG. 1 is a block diagram illustrating a configuration of the synchronization signal generation unit 35. The synchronization signal generation unit 35 of the present embodiment determines “can be pulled in” when the movement amount of the input Vsync (input vertical synchronization signal) with respect to the output Vsync (output vertical synchronization signal) is equal to or less than the correction amount of the frame lock control. . The synchronization signal generation unit 35 determines that “pull-in is completed” when pull-in is possible and the position of the input Vsync is within the lock window (that is, the lock phase section). Hereinafter, specific processing of the synchronization signal generator 35 will be described.

  The input synchronization signal input unit 11 receives the input Vsync from the video input unit 31. The output synchronization signal generator 12 generates a display synchronization signal for driving the display unit 34. The frame lock control unit 13 performs the above-described frame lock control together with the output synchronization signal generation unit 12. The frame lock control unit 13 detects the timing of the input Vsync and the output Vsync, measures the phase difference between the two timings, generates an adjustment signal based on the phase difference, and outputs the adjustment signal to the output synchronization signal generation unit 12 . The output synchronization signal generation unit 12 changes the cycle of the output-side synchronization signal (display synchronization signal) based on the input adjustment signal. By changing the cycle, it becomes possible to draw the input Vsync into the lock phase. The output synchronization signal generator 12 changes the cycle by increasing or decreasing the number of lines per frame on the output side by a predetermined correction amount. The frame lock control unit 13 can determine that the frame lock is complete based on the measured phase difference or based on the pull-in state signal 19 output from the pull-in completion determination unit 18.

  The position detector 14 detects the position of the input Vsync with respect to the output Vsync. The movement amount detection unit 15 detects the movement amount of the input Vsync with respect to the output Vsync using the position detected by the position detection unit 14. The movement amount detection unit 15 detects the movement amount by calculating a difference between the position of the input Vsync in the previous frame and the position of the input Vsync in the current frame. The pullability determination unit 16 determines whether the input signal can be pulled from the result of the movement amount detection unit 15. The availability determining unit 16 determines “retractable” when the movement amount is smaller than the correction amount of the frame lock control unit 13, and determines “retractable” otherwise. When the input signal is “pullable”, the availability determination unit 16 outputs a signal having a level indicating that pulling is possible as the determination signal 17 to the switching control unit 36.

  The pull-in completion determination unit 18 determines whether or not the position of the input Vsync is within the lock window. The completion determination unit 18 determines “retracting completion” when the position of the input Vsync is within the lock window, and determines “retracting” otherwise. When the position of the input Vsync is within the lock window, the completion determination unit 18 outputs a signal having a level indicating “retraction complete” to the switching control unit 36 as the pull-in state signal 19. In addition, when the position of the input Vsync is not in the lock window, the completion determination unit 18 outputs a signal having a level indicating “at the time of drawing” to the switching control unit 36 as the drawing state signal 19.

<Example of pull-in determination operation (FIG. 6)>
Next, an operation example of the pull-in determination performed by the availability determination unit 16 will be described with reference to FIG. FIG. 6 is a timing chart showing how the position of the input Vsyn is detected and the amount of movement is detected. Assume that input Vsync occurs at timing 60 in frame # 1. In this case, the position detection unit 14 measures the position 61 as the position of the input Vsync with respect to the output Vsync. Assume that input Vsync occurs at timing 62 in the subsequent frame # 2. In this case, the position detector 14 measures the position 63 as the position of the input Vsync with respect to the output Vsync. The movement amount detection unit 15 calculates a movement amount 64 as a difference between the position 61 of the frame # 1 that is the previous frame and the position 63 of the frame # 2 that is the current frame. The availability determination unit 16 compares the correction amount 65 and the movement amount 64 to determine whether the pull-in is possible. For example, when the movement amount is 5 lines and the correction amount is 8 lines, since the movement amount <the correction amount, the availability determination unit 16 determines that “retraction is possible”.

  Next, the completion determination unit 18 determines the pull-in state by comparing the positional relationship between the input Vsync and the lock window. When the position of the input Vsync is between the left end 66 and the right end 67 of the lock window, the completion determination unit 18 determines “retraction complete”, and otherwise determines “retracting”. In the example of FIG. 6, the input Vsync position 63 is to the left of the lock window left end 66, so the completion determination unit 18 determines that “retracting”. In this case, the completion determination unit 18 outputs a signal having a level indicating “drawing” to the switching control unit 36. In response to this, the switching control unit 36 outputs to the video switch 33 a signal instructing to select an image via the frame buffering 3. The video switch 33 selects and outputs video data via the frame buffer 32 based on the input signal. By this control, the display unit 34 performs display in the “frame buffering mode”, that is, displays video data via the frame buffer 32.

  On the other hand, when the completion determination unit 18 determines that the input Vsync is “pullable” and is in the “pull-in completion” phase, a signal having a level indicating “pull-in completion” is output to the switching control unit 36. In response to this, the switching control unit 36 outputs to the video switch 33 a signal instructing to select an image that does not pass through the frame buffering 3. The video switch selects and outputs video data not passing through the frame buffer 32 based on the input signal. By this control, the display unit 34 performs display in the “low delay mode”, that is, displays video data without using the frame buffer 32.

<Timing when input switching processing is performed (FIG. 5)>
FIG. 5 is a timing diagram showing a state when the input switching process is performed by the user. The input switching process is started, for example, when the user operates an input port switching menu on the UI. Moreover, it is activated when the user replaces the cable connected to the input port. The output vertical synchronization signal 50 (output Vsync) is generated by the synchronization signal generation unit 35, the determination signal 51 is generated by the availability determination unit 16, and the pull-in state signal 52 is generated by the completion determination unit 18. The delay mode 53 indicates a display mode (frame delay mode (that is, frame buffering mode) or low delay mode) of video data displayed on the display unit 34.

  First, at timing 54, an input switching instruction is generated by a user operation. The pull-in process is started in the synchronization signal generation unit 35, and the pull-in state signal 52 becomes a status of “pulling in”. During this time, display is performed in the “frame buffering mode” using the frame buffer 32.

  At the same time, the availability determination unit 16 determines whether or not it can be pulled in, and at timing 55, the determination signal 51 has a status of “pullable”. Thereafter, the pull-in is completed at timing 57 as a result of the frame lock control. In the section 58, the delay mode is switched to the “low delay mode” in which the frame buffer is not used, and the display is performed without going through the frame buffer 32.

<Flow of input switching control (FIG. 7)>
Next, with reference to FIG. 7, the flow of control when performing input switching will be described. FIG. 7 is a flowchart showing the control of the video processing apparatus according to the present embodiment when input switching is instructed. In step S100, the video processing apparatus sets the frame buffer mode to “frame buffering mode”. Since the video processing device does not know where the initial phase of the input Vsync is, it is set to the frame buffering mode uniformly so that tearing does not occur. In step S101, the video processing device drives the movement amount detection unit 15 to detect the movement amount of the input Vsync. In step S102, the video processing apparatus determines whether or not the pull-in is possible using the detection result of the movement amount of the input Vsync. If possible, the process proceeds to step S103, and if not possible, the process ends. The video processing apparatus determines that the pull-in is possible when the movement amount is smaller than the correction amount of the frame lock mechanism.

  In step S103, the video processing device drives the position detector 14 to detect the position of the input Vsync. In step S104, the video processing apparatus determines whether the pull-in is completed using the detection result of the position of the input Vsync. If it is completed, the process proceeds to step S105, and if not completed, the process of step S103 is performed. Try again. The video processing apparatus determines that the pull-in is complete when the position of the input Vsync is within the lock window. In step S105, the video processing apparatus sets the frame buffer mode to the “low delay mode” and ends the process. By the above processing, the video processing apparatus can be switched to the “low delay mode” only when the input Vsync can be pulled in and the pulling-in is completed.

  As a result, when the pull-in is impossible, the video processing apparatus prevents tearing by setting the frame buffer mode to “frame buffering mode”. When the pull-in is possible but the pull-in is not completed, the video processing apparatus prevents tearing by operating in the frame buffering mode. When the pull-in is possible and the pull-in is completed, the video processing apparatus sets “low delay mode” because tearing does not occur.

  As described above, according to the present embodiment, it is possible to make a faster determination that the lock has been made to the pull-in phase. As a result, the display mode (frame buffering mode) for preventing tearing can be released more quickly.

[Embodiment 2]
In the present embodiment, an example will be described in which “withdrawal is possible” is determined when the period of the input synchronization signal is within the correction range of the frame lock control. Since the configuration of the video processing apparatus according to the present embodiment is the same as that of the above-described embodiment, description thereof is omitted.

<Configuration of Sync Signal Generation Unit (FIG. 8)>
FIG. 8 is a block diagram illustrating a configuration of the synchronization signal generation unit 35 of the present embodiment. The same elements as those of the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted. Compared to FIG. 1 described in the first embodiment, the synchronization signal generation unit 35 of the present embodiment does not include the movement amount detection unit 15 and the availability determination unit 16 but includes a cycle detection unit 81 and a availability determination unit 82.

  The period detector 81 measures the period of the input Vsync. Measurement starts each time an input Vsync arrives, and the most recent measurement result is held. The availability determination unit 82 determines whether or not the input Vsync can be pulled in using the measurement result of the cycle of the input Vsync. In the frame lock control of the present embodiment, pull-in is possible only when the cycle of the input Vsync is within the range of the cycle of the output Vsync ± the correction amount. Therefore, here, when the cycle of the input Vsync is within the range of the cycle of the output Vsync−the correction amount and the cycle of the output Vsync + the correction amount, the availability determination unit 82 determines “can be pulled in”.

<Example of pull-in determination operation (FIG. 9)>
Next, an operation example of the pull-in determination by the availability determination unit 82 will be described with reference to FIG. FIG. 9 is a timing chart showing how the input Vsync is detected and the amount of movement is detected. Assume that input Vsync occurs at timing 60 in frame # 1. In this case, the position detector 14 measures the position 61 as the position of the input Vsync with respect to the output Vsync, and the cycle detector 81 starts measuring the cycle 90 of the input Vsync. Assume that input Vsync occurs at timing 62 in frame # 2. In this case, the position detection unit 14 measures the position 63, and the cycle detection unit 81 ends the measurement of the cycle 90 of the input Vsync. The availability determining unit 82 compares the output Vsync cycle ± correction amount with the input Vsync cycle 90 to determine whether or not the pull-in is possible.

  Next, the completion determination unit 18 determines the pull-in state by comparing the positional relationship between the input Vsync and the lock window. The completion determination unit 18 determines that “retraction is complete” when the position of the input Vsync is between the left end 66 and the right end 67 of the lock window, and “retracting” otherwise. In the example of FIG. 9, the input Vsync position 63 is to the left of the lock window left end 66, so the completion determination unit 18 determines that “retracting”. Thus, according to the present embodiment, the same effects as those of the first embodiment can be obtained.

  The video processing apparatus according to the present embodiment is not limited to the above-described embodiment, and can be widely applied. For example, it is possible to provide a video processing device that releases the buffering mode faster. That is, when the input Vsync is in the “pull-in” phase, noise due to tearing does not occur if it is outside the effective image area. In this case, the video processing apparatus can cancel the buffering mode. In the above-described embodiment, the video processing apparatus has been described as an example. However, an apparatus that processes and outputs an image may be used. For example, an apparatus such as an image editor or a scan converter may be used.

[Other Embodiments]
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

11 input synchronization signal input unit, 12 output synchronization signal generation unit, 13 frame lock control unit, 14 position detection unit, 15 movement amount detection unit, 16 availability determination unit, 17 determination signal, 18 completion determination unit, 19 pull-in state signal, 31 video input unit, 32 frame buffer, 33 video switch, 34 display unit, 35 synchronization signal generation unit, 36 switching control unit

Claims (11)

A synchronization signal generating device capable of changing the positional relationship between the timing of the input synchronization signal and the output synchronization signal by correcting the cycle of the output synchronization signal,
First determination means for determining whether or not the timing of the input synchronization signal can be drawn into a predetermined phase interval determined by a period of the output synchronization signal;
Correction means for correcting the period of the output synchronization signal;
When it is determined by the first determination means that the timing of the input synchronization signal can be drawn into the predetermined phase interval, the input synchronization signal is corrected after the period of the output synchronization signal is corrected by the correction means. Second determination means for determining whether or not the timing of the signal is drawn into the predetermined phase section;
A synchronization signal generating device comprising: A movement amount detecting means for detecting a movement amount of the timing of the input synchronization signal with respect to the timing of the output synchronization signal;
2. The synchronization signal according to claim 1, wherein the first determination unit determines whether or not the timing of the input synchronization signal can be pulled into the predetermined phase section based on the movement amount. Generator.   The first determination unit may draw the timing of the input synchronization signal into the predetermined phase section when the movement amount is smaller than the correction amount of the period of the output synchronization signal that can be corrected by the correction unit. The synchronization signal generation device according to claim 2, wherein the synchronization signal generation device is determined to be possible. It further has period detection means for detecting the period of the input synchronization signal,
The said 1st determination means determines whether it is possible to pull in the timing of the said input synchronizing signal in the area of the said predetermined phase based on the period of the said input synchronizing signal. The synchronization signal generation device described.   When the difference between the cycle of the output synchronization signal and the cycle of the input synchronization signal is smaller than the correction amount of the cycle of the output synchronization signal that can be corrected by the correction unit, the first determination unit 5. The synchronization signal generating apparatus according to claim 4, wherein the timing is determined to be able to be pulled into the predetermined phase section.   The second determination means outputs a signal indicating that it is being pulled when it is determined that the timing of the input synchronization signal is not pulled into the predetermined phase interval. Item 6. The synchronization signal generation device according to any one of Items 1 to 5.   The second determination means outputs a signal indicating that pull-in is complete when it is determined that the timing of the input synchronization signal is pulled into the predetermined phase interval. The synchronization signal generation device according to any one of 1 to 5. The synchronization signal generating device according to claim 6 or 7,
A buffer for buffering video data input at the timing of the input synchronization signal;
Selection means for selecting video data via the buffer or video data not via the buffer based on a signal received from the synchronization signal generating device;
Display means for displaying the video data selected by the selection means at the timing of the output synchronization signal,
The video processing apparatus, wherein the selection unit selects video data via the buffer when receiving a signal indicating that the pull-in is being performed from the synchronization signal generation apparatus. The synchronization signal generating device according to claim 6 or 7,
A buffer for buffering video data input at the timing of the input synchronization signal;
Selection means for selecting video data via the buffer or video data not via the buffer based on a signal received from the synchronization signal generating device;
Display means for displaying the video data selected by the selection means at the timing of the output synchronization signal,
The video processing apparatus, wherein the selection means selects video data not through the buffer when receiving a signal indicating that the pull-in is completed from the synchronization signal generation apparatus. A synchronization signal generation method for changing a positional relationship between timings of an input synchronization signal and the output synchronization signal by correcting a cycle of the output synchronization signal,
A first determination step of determining whether or not the timing of the input synchronization signal can be drawn into a predetermined phase interval determined by a period of the output synchronization signal;
A correction step of correcting the period of the output synchronization signal;
When it is determined in the first determination step that the timing of the input synchronization signal can be drawn into the predetermined phase interval, the input synchronization signal is corrected after the period of the output synchronization signal is corrected in the correction step. A second determination step of determining whether the timing of the signal is drawn into the predetermined phase interval;
A method for generating a synchronization signal, comprising:   A program that causes a computer to function as each unit of the synchronization signal generation device according to any one of claims 1 to 9.

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