JP3409844B2 - Clock phase automatic adjustment system and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase automatic adjustment system for automatically adjusting the phase of a dot clock, which is a sampling clock for sampling an analog video signal, generated in a digital display device. Regarding the method.

[0002]

2. Description of the Related Art Generally, a display device such as a display monitor for a computer which uses a latticed device such as a liquid crystal panel or a PDP (plasma display) panel is used to convert an analog video input signal output from a computer body into an analog / digital signal. (After A / D) conversion,
A digital signal is led to each pixel on the screen. The above-mentioned analog video input signal is obtained by sequentially reading out image data stored in the image memory in the computer in synchronism with the dot clock of the computer, and performing digital-analog (hereinafter D / A) conversion. It is a signal.

Usually, when the analog image input signal is A / D converted in the display device, a dot clock having the same frequency as the dot clock of the computer is generated in the display device and synchronized with the generated dot clock. A
/ D conversion is performed. Therefore, the display device multiplies the frequency of the horizontal synchronizing signal synchronized with the analog video input signal by using a PLL (Phase Locked loop) circuit phase-locked with the horizontal synchronizing signal to generate a dot clock.

However, when the phase of the dot clock of the computer and the phase of the dot clock of the display device are deviated, the analog video input signal is sampled according to the value of the image data stored in the image memory of the computer. Since it is not possible, 1 is added to the image displayed on the display device.
Pixel level horizontal screen flicker and flicker occur. Therefore, the dot clock of the computer and the dot clock of the display device must have the same phase.

The phase of the dot clock as described above may change depending on the surrounding environment such as temperature, and requires readjustment. Therefore, various clock phase automatic adjustment systems for automatically adjusting the phase of the dot clock have been devised.

FIG. 4 is a block diagram showing the configuration of a conventional clock phase automatic adjustment system. The conventional clock phase automatic adjustment system of FIG. 4 includes an A / D converter 1, a phase detector 16, a CPU 17, and a PLL circuit 14.

The A / D converter 1 inputs the analog video input signal and the dot clock output from the PLL circuit 14, and converts the analog video input signal into a digital signal at the rising edge of the dot clock. Phase detector 16
Is composed of a D flip-flop 8, a difference circuit 9, an absolute value detection circuit 10, a cyclic addition circuit 11, and a holding circuit 12. The D flip-flop 8 stores the digital signal output from the A / D converter 1. The difference circuit 9 outputs the difference between the digital signal input this time and the previous digital signal stored in the D flip-flop circuit 8. The absolute value detection circuit 10 outputs the absolute value of the difference between the digital signals output from the difference circuit 9.
The holding circuit 12 continues to hold the output value of the cyclic addition circuit 12 as the phase detection result until the next measurement instruction is given from the CPU 17. The cyclic addition circuit 11 includes an absolute value detection circuit 10
From the time when there is a measurement instruction from the CPU 17 until the time when there is a next measurement instruction, and the added value is output to the CPU 17 as the phase detection result.

The PLL circuit 14 locks the phase of the horizontal synchronizing signal of the analog video input signal, multiplies the frequency of the horizontal synchronizing signal, and generates a dot clock. The PLL circuit 14 can perform N-stage (N = 1, 2, ..., N) phase setting. The CPU 17 outputs a measurement instruction to the absolute value detection circuit 10 and the holding circuit 12 each time the phase of the PLL circuit 14 is set. The CPU 17 uses the PLL circuit 14
By setting the phase in the register of step by step,
The phase detection result output from the phase detection unit 16 is stored for each phase of each stage, and the phase having the maximum phase detection result among the phases of each stage is finally set in the PLL circuit 14, and P
The phase of the LL circuit 14 is adjusted.

Next, the operation of the conventional clock phase automatic adjustment system will be described in detail. FIG. 5 shows a time chart showing the relationship between the analog video input signal and the dot clock of the display device. FIG. 5 shows the PLL circuit 14 when the waveform of the analog video input signal input to the display device from the top and the phase of the PLL circuit 14 are set at a certain stage.
The waveform of the dot clock 0 output from the PLL circuit 14 and the waveform of the dot clock 1 output from the PLL circuit 14 when the phase of the PLL circuit 14 is set to a stage different from that of the dot clock 0 are shown.

When the dot clock is automatically adjusted, a test signal having a simple test pattern is used as an analog video input signal. The analog video input signal of FIG. 5 is a test signal for dot clock phase adjustment in which a white level and a black level are repeated pixel by pixel.

The A / D converter 1 samples the analog video input signal at the rising edge of the dot clock. When the analog video input signal is sampled using the dot clock 0, the A / D converter 1 outputs the analog video input signal during the transition period when the white level changes to the black level and the transition period when the black level changes to the white level. Since the sampling is performed, the display device cannot display the image according to the alternating black and white test pattern on the screen.
On the other hand, when the analog video input signal is sampled using the dot clock 1, the A / D converter 1 receives the analog video input when the analog video input signal is stable at the white level and when it is stable at the black level. Since the signal is sampled, the display device can display an image according to the alternating black and white test pattern on the screen.

That is, the transition period of the analog video input signal is a phase inadequate period, sampling of the analog video input signal should not be performed during this period, and the stable period of the analog video input signal is the phase optimum period. During this period, sampling of the analog video input signal should be performed. Therefore, the phase of the dot clock 1 is more suitable as the phase of the dot clock output from the PLL circuit 14 than the phase of the dot clock 0.

When the dot clock output from the PLL circuit 14 has the phase of the dot clock 0, the absolute value of the difference between the digital signal sampled last time and the digital signal sampled this time is the white level. It is smaller than the absolute value of the difference between the value and the black level value. As a result, the phase detection result output by the phase detection unit 16 is also smaller than the cumulative addition value of the absolute values of the differences between the white level value and the black level value, which are the maximum values of the phase detection result.

On the other hand, when the phase of the dot clock output from the PLL circuit 14 is the phase of the dot clock 1, the absolute value of the difference between the value sampled last time and the value sampled this time is the white level. The value becomes equal to the absolute value of the difference between the value and the black level value, and the phase detection result output from the phase detection unit 16 becomes maximum. That is, the phase when the value of the phase detection result output from the phase detector 16 is the maximum is the optimum phase.

The CPU 17 shifts the phase of the dot clock of the PLL circuit step by step while the phase detector 1
The phase detection result of No. 6 is obtained for each phase, and the phase when the phase detection result is maximum is determined to be the optimum phase, and the phase adjustment of the dot clock is performed.

Actually, the analog video signal contains a noise component, and the lower bit of the A / D converted digital signal always contains a noise component. In the above-described conventional clock phase automatic adjustment system, when the phase detector 16 has the difference circuit 9, and the difference circuit 9 directly subtracts the digital signal containing the noise component, the phase detection of the dot clock is performed. There is a possibility that the result may be incorrect and the optimum phase adjustment may be difficult.

[0017]

In the above-described conventional clock phase automatic adjustment system, the optimum phase is stabilized by the noise component contained in the analog video signal and the power supply noise generated during A / D conversion. There was a problem that it could not be detected by.

Therefore, an object of the present invention is to provide an automatic clock phase adjustment system which can perform automatic phase adjustment of a dot clock in a stable state without being affected by noise components contained in an analog video signal. is there.

[0019]

In order to solve the above problems, a clock phase automatic adjustment system of the present invention uses a horizontal synchronizing signal and a vertical synchronizing signal of an analog video signal as input, and scans lines of the analog video signal. Among these, during the horizontal blanking period of the scanning lines included in the phase measurement range preset by the control means, a blanking pulse indicating that the horizontal blanking period is in progress is preset by the control means. A blanking pulse generating means for generating a noise signal, a gate means for passing a digital signal output from the analog / digital converting means as a noise signal while the blanking pulse is generated, and the noise signal. Value is compared with the stored value of the noise signal, and the larger one is the new noise signal. While storing as a maximum value, the maximum value detecting means for outputting the maximum value of the new noise signal, and from the time when the measurement instruction is input by the control means to the time when the next measurement instruction is input, A maximum value holding unit that holds the maximum value of the noise signal output from the maximum value detection unit as a noise level value, and a mask value that determines a value equal to or higher than the noise level value as a mask signal value and outputs the mask signal. Noise masking means comprising: determining means; and masking means for masking the digital signal output from the analog / digital converting means by the masking signal and outputting the masked digital signal to the phase detecting means. Further prepare.

In the automatic clock phase adjustment system of the present invention, the fluctuation of the digital signal in the horizontal blanking period is measured, the noise mask means for masking the noise component from the digital signal is provided, and the dot is generated by the digital signal masking the noise component. Since the clock phase is detected, the automatic phase adjustment of the dot clock can be performed in a stable state.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a clock phase automatic adjustment system according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a screen image diagram of a signal for one field of an analog video input signal input to the clock phase automatic adjustment system of the present embodiment. FIG. 2 is a block diagram showing the configuration of the clock phase automatic adjustment system of this embodiment. FIG. 3 is a time chart showing the operation of the clock phase automatic adjustment system of this embodiment. In FIG. 2, the components designated by the same reference numerals as those in FIG. 4 are all the same components.

First, an analog video input signal input to the clock phase automatic adjustment system according to the embodiment of the present invention will be described. FIG. 1 shows a screen image of an analog image input signal of one field when scanning on the screen is performed from the upper left to the lower right of the screen, and one row represents one scanning line. The analog video input signal for one field is roughly classified into a video period signal and a blanking period signal. The signal in the video period is a video signal actually displayed on the screen, and the signal in the blanking period is a control signal for controlling the screen display. Blanking period is 1
There is a vertical blanking period (V blanking) at the beginning of the field and a horizontal blanking period (H blanking) at the beginning of one scanning line, and the signal level during this period is a black level. The vertical synchronizing signal is turned on during the vertical blanking period, and the horizontal synchronizing signal is turned on during the horizontal blanking period. A period in which the vertical synchronizing signal and the horizontal synchronizing signal are on during the blanking period is particularly called a synchronizing period.

Further, in the clock phase automatic adjustment system of this embodiment, an analog video signal having a video pattern in which a high value and a low value are repeated pixel by pixel during a video period is used as a test signal as in the conventional case. Phase detection is
It is performed within the specified phase measurement range during the video period. An arbitrary range during the video period can be designated as the phase measurement range.

Further, the horizontal blanking period of the scanning lines included in the phase measurement range is set as the blanking level detection range. As described above, the signal level during the blanking period is the black level (minimum level), and the fluctuation of the signal during the blanking period can be regarded as fluctuation due to noise. Therefore, the noise level can be detected from the fluctuation value of the digital signal during the blanking period. In the present embodiment, the noise level is detected in this blanking level detection range.

Next, the configuration of the clock phase automatic adjustment system of this embodiment will be described. The clock phase automatic adjustment system of the present embodiment of FIG. 2 includes an A / D converter 1, a noise mask section 15, a phase detection section 16, and a CPU 13.
And a PLL circuit 14. A / D converter 1
The phase detector 16 and the PLL circuit 14 have the same structure as the conventional clock phase adjusting system shown in FIG. The noise mask unit 15 includes a blanking pulse generator 2 and
A gate circuit 3, a maximum value detection circuit 4, a holding circuit 5,
It is composed of an encoder 6 and a mask circuit 7.

The blanking pulse generator 2 inputs the horizontal synchronizing signal (HSYNC) and the vertical synchronizing signal (VSYNC) of the analog video input signal and turns on the blanking pulse within the blanking level detection range.

The gate circuit 3 includes a blanking pulse,
The digital signal output from the A / D converter 1 is input, and only while the blanking pulse is on,
The digital signal output from the A / D converter 1 is passed. The maximum value detection circuit 4 inputs the digital signal that has passed through the gate circuit 3 and, if the value of the digital signal input this time is larger than the value of the stored digital signal, stores the signal input this time and , That value is output as the maximum value of the noise signal. Further, when the value of the digital signal input this time is equal to or less than the value of the stored digital signal, the maximum value detection circuit 4 stores the value of the stored digital signal anew, and Output as the maximum value of the signal.

The holding circuit 5 holds the maximum value of the noise signal output from the maximum value detection circuit 4 as a noise level value. The encoder 6 receives the noise level value held by the holding circuit 5, determines a value equal to or higher than the noise level value as a mask signal for masking the digital signal output from the A / D converter 1, and outputs the mask signal. To do.

The mask circuit 7 receives the digital signal output from the A / D converter 1 and the mask signal output from the encoder 6 as inputs, masks the digital signal with the mask signal, and masks the phase detector 16. Output a digital signal.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG. FIG. 2 is a time chart showing the operation of the clock phase automatic adjustment system of this embodiment. In FIG. 2, the horizontal synchronization signal (HSY
NC), the blanking pulse generated by the blanking pulse generator 2, the analog video input signal input to the A / D converter 1, the noise level value held by the holding circuit 5, and the phase detector. The waveform of the phase detection source data input to 16 is illustrated.

The CPU 13 blanks the scanning line number and the pulse generation time included in the phase measurement range so that the blanking pulse is turned on for the set time in the blanking level detection range of FIG. It is set in the register of the ranking pulse generator 2. Then, the blanking pulse generator 2 counts the number of horizontal synchronizing signals (HSYNC) with the vertical synchronizing signal (VSYNC) as a reference, and if the count number matches the scanning line number set in the register, the scanning is performed. In the horizontal blanking period of the line, the blanking pulse is turned on for the set pulse generation time. While the blanking pulse is on, the gate circuit 3 allows the digital signal output from the A / D converter 1 to pass through, and the maximum value of the digital signal during that time is detected by the maximum value detection circuit 4 and detected. The maximum value of the generated digital signal is held in the holding circuit 5 as a noise level value.

At time t0, when the value of the detected digital signal is MAX0 and MAX0 is the maximum value of the digital signal during the period when the blanking pulse is on, the holding circuit 5 outputs Output is MA
It becomes X0.

Thereafter, while the blanking pulse is next turned on, the value of the digital signal is MAX1 at time t1, MAX1 is larger than MAX0, and M
When AX1 is the maximum value of the digital signal during the period when the blanking pulse is on, the output of the maximum value detection circuit 4 is MAX1 and the holding circuit 5 is M
AX1 is held as a noise level value. Encoder 6
Is A / D from MAX1 held in the holding circuit 5.
A mask signal for masking the digital signal output from the converter 1 is created. For example, the encoder 6
The noise level value held by the holding circuit 5 is 0000110.
If it is 1, the mask signal value is set to 00001111 and the mask signal is output to the mask circuit 7.

The mask circuit 7 outputs 0 when the value of the digital signal output from the A / D converter 1 is smaller than the mask signal value, and the value of the digital signal output from the A / D converter 1 is If it is equal to or larger than the mask signal value, the digital signal from the A / D converter 1 is output as it is. For example,
The mask circuit 7 has a digital signal of 8 bits and 0000.
1010 and the mask signal value is 00001111, 00000000 is output, and if the digital signal is 8 bits 01001010, and the mask signal value is 00001111, it is 0100 as it is.
1010 is output.

In the automatic clock phase adjustment system as described above, the noise component contained in the analog image input signal is removed from the digital signal output from the A / D converter 1, and the noise component is supplied to the phase detection unit 16. It is possible to input a digital signal from which is removed.

The noise mask section 15 can also remove the black level offset component contained in the analog image input signal.

[0037]

As described above, according to the clock phase automatic adjustment system of the present invention, the noise component is detected from the digital signal output after A / D conversion by utilizing the blanking period of the analog video signal. Then, a mask signal value is determined from the noise component, and a noise mask means for masking the digital signal with the mask signal is provided, so that the noise component contained in the analog video signal and the offset component of about black level are removed from the digital signal. Since the phase of the dot clock is detected from the signal, the automatic phase adjustment of the dot clock can be performed in a stable state.

In this embodiment, the mask circuit 7 has an A / D
When the value of the digital signal output from the converter 1 is equal to the mask signal value, the output from the A / D converter 1 is output as it is, but in such a case, 0 may be output. Good.

[Brief description of drawings]

FIG. 1 is an image image diagram of a signal of one field of an analog video input signal input to a clock phase automatic adjustment system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a clock phase automatic adjustment system according to an embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the clock phase automatic adjustment system according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional clock phase automatic adjustment system.

FIG. 5 is a time chart of an analog video input signal and a dot clock input at the time of automatic dot clock phase adjustment.

[Explanation of symbols]

1 A / D converter 2 Blanking pulse generator 3 gate circuit 4 Maximum value detection circuit 5, 12 holding circuit 6 encoder 7 Mask circuit 8 D flip-flop 9 Difference circuit 10 Absolute value detection circuit 11 Cyclic adder 13, 17 CPU 14 PLL circuit 15 Noise mask part 16 Phase detector

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Claims (8)

(57) [Claims] 1. A phase lock is applied to a horizontal synchronizing signal of an analog video signal, a frequency of the horizontal synchronizing signal is multiplied to generate a dot clock for sampling the analog video signal, and a phase of the dot clock is set. Phase-locked loop means for adjusting and outputting the adjusted phase, analog / digital converting means for sampling the analog video signal and converting it into a digital signal using the dot clock as a sampling clock, and the digital signal The phase detection means for calculating the absolute value of the difference from the digital signal of the dot clock one cycle before and outputting the cumulative addition value of the absolute values as the phase detection result of the dot clock; , The phase of the dot clock is set in stages, Each time the phase of the clock is set, a measurement instruction for measuring the phase detection result is output to the phase detection unit, the phase detection result is stored, and the phase of the dot clock at each stage is In a clock phase automatic adjustment system composed of a control means for finally setting the phase having the maximum phase detection result in the phase locked loop means, the horizontal synchronization signal and the vertical synchronization signal of the analog video signal are combined. Of the scanning lines of the analog video signal as an input,
During the horizontal blanking period of the scanning lines included in the phase measurement range preset by the control unit, a blanking pulse indicating that the horizontal blanking period is in progress is preset by the control unit. Blanking pulse generation means for generating only time, gate means for passing a digital signal output from the analog / digital conversion means as a noise signal while the blanking pulse is generated, A maximum value detecting means for comparing the value with the stored value of the noise signal, storing the larger value as the maximum value of the new noise signal, and outputting the maximum value of the new noise signal; From the time when the measurement instruction is input by the control means to the time when the next measurement instruction is input, the maximum value detection Maximum value holding means for holding the maximum value of the noise signal output from the stage as a noise level value, and mask value determination means for determining a value greater than or equal to the noise level value as a mask signal value and outputting the mask signal. ,
A noise masking unit configured to mask the digital signal output from the analog / digital converting unit with the masking signal and output the masked digital signal to the phase detecting unit. Characteristic clock phase automatic adjustment system. 2. The mask value determining means detects, when the noise level value is represented by a binary number, the most significant bit among the bits that are 1 in each bit of the noise level value. 2. The clock phase automatic adjustment system according to claim 1, further comprising means for outputting, as the mask signal value, a value in which all the bits below the most significant bit are 1. 3. The mask means outputs 0 when the value of the digital signal output from the analog / digital converting means is smaller than the mask signal value, and the digital signal output from the analog / digital converting means. 3. The automatic clock phase adjustment system according to claim 1 or 2, which is a means for directly outputting the digital signal output from the analog / digital conversion means when the value of is greater than or equal to the mask signal value. 4. The mask means outputs 0 when the value of the digital signal output from the analog / digital conversion means is less than or equal to the mask signal value, and the digital output from the analog / digital conversion means. 3. The clock phase automatic adjustment system according to claim 1, wherein when the signal value is larger than the mask signal value, the digital signal output from the analog / digital conversion means is output as it is. 5. In order to automatically adjust the phase of a dot clock which is a sampling clock for converting an analog video signal into a digital signal, the phase of the dot clock is divided into several steps within one cycle of the dot clock. The absolute value of the difference between a digital signal converted from an analog video signal having a signal pattern in which a high value and a low value are repeated for each pixel while shifting and a digital signal converted from the analog video signal one cycle before the dot clock. A value obtained by cumulatively adding the values is obtained as a phase detection result for each phase of each stage of the dot clock, and the phase having the maximum phase detection result is set as an optimum phase in the clock phase automatic adjusting method, Specify the phase measurement range of the signal,
During the horizontal blanking period of the scanning lines included in the phase measurement range among the scanning lines included in the analog video signal,
The fluctuation of the digital signal converted from the analog video signal is measured at a preset time, the maximum value of the digital signal is detected as a noise level value, and a value above the noise level value is determined as a mask signal value. Then, the digital signal converted from the analog video signal is masked by the mask signal, and the phase detection result is obtained from the masked digital signal. 6. The step of determining the mask signal value, when the noise level value is represented by a binary number, of the bits of the noise level value, the most significant bit among the bits that are 1 6. The automatic clock phase adjusting method according to claim 5, wherein the mask signal value is a value in which all the bits below the most significant bit are 1 as a mask signal value. 7. The step of masking a digital signal converted from the analog video signal, wherein 0 is obtained for the phase detection result when the digital signal converted from the analog video signal is smaller than the mask signal value. When the digital signal converted from the analog video signal is equal to or more than the mask signal value, the digital signal converted from the analog video signal is used as a digital signal for obtaining the phase detection result. 7. The automatic clock phase adjustment method according to claim 5, which is a step of performing. 8. The step of masking the digital signal converted from the analog video signal, when the digital signal converted from the analog video signal is less than or equal to the mask signal value, 0 is obtained as the phase detection result. If the digital signal converted from the analog video signal is larger than the mask signal value, the digital signal converted from the analog video signal is used as a digital signal for obtaining the phase detection result. 7. The automatic clock phase adjustment method according to claim 5, which is a step of performing.