JP3639946B2 - Digital display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital display , and more particularly to a digital display using a lattice-like device having a clock phase automatic adjustment circuit that automatically adjusts the phase of a dot clock.
[0002]
[Prior art]
When an image is displayed on a digital display using a lattice device such as a liquid crystal or a PDP (plasma display), it is necessary to sample an analog video signal with a dot clock in an A / D converter. In this case, the display side generally reproduces a dot clock obtained by multiplying the horizontal synchronizing signal by a phase locked loop (PLL) circuit that is phase-locked to the horizontal synchronizing signal in the analog video signal to be displayed. Yes.
[0003]
However, even if the frequency of the dot clock of the analog video signal supplied to the A / D converter matches the frequency of the playback dot clock, if the phase is shifted, the screen shakes in the horizontal direction on the display screen (at 1 dot level). Therefore, it is necessary to adjust the phase of the dot clock. In order for the user to manually adjust the dot clock phase, the dot clock phase changes depending on the environmental temperature, etc., so the phase must always be readjusted even if the video input signals are the same. There is a problem that the operation is complicated and troublesome.
[0004]
Therefore, conventionally, the clock phase automatic adjustment circuit as shown in the circuit diagram of FIG. 4 is used to automatically adjust the phase of the dot clock. That is, in the figure, an analog video signal for adjustment, in which the white level and the black level are alternately repeated at a dot cycle as shown in FIG. 5A, is supplied to the A / D converter 11, where the PLL circuit After sampling at the rising edge (leading edge) of the dot clock from 20 and converting to a digital signal, the D-type flip-flop 12 delays one dot cycle, and the subtractor 13 subtracts the signal that has not been delayed.
[0005]
As a result, a difference value between two adjacent dots is taken out from the subtracter 13, and after this absolute value is obtained by the absolute value circuit 14, it is a phase comprising the adder 15 and the D flip-flop 16. The detection unit 17 performs cyclic addition. The added value for one line obtained in this way is held in the holding circuit 18 and then supplied to the central processing unit (CPU) 19.
[0006]
The CPU 19 controls the PLL circuit 20 to generate a dot clock having the same dot clock frequency and a step (phase angle) whose phase is different from the previous time, and performs the same operation as described above. In this way, it is determined that the dot clock of the step when the cyclic addition value having the largest value among the dot clocks of a plurality of steps set in advance is the optimum phase. This is because the cyclic addition value is larger when the phase is correct than when it is not correct.
[0007]
Thereby, for the analog video signal shown in FIG. 5A, the level change period of the analog video signal as shown in FIG. 5B (change portion from white to black, change portion from black to white). It is adjusted so that a dot clock with no leading edge is output during the level change period, as shown in FIG.
[0008]
Further, as a conventional clock phase automatic adjustment circuit, conversion means for converting the same video signal having a limited number of levels into a predetermined digital video signal with a plurality of clocks having different phases, and a histogram of the digital video signal There is also known an automatic adjustment circuit that includes a means for calculating the frequency and a calculation means for calculating a statistical parameter indicating the degree of concentration of the histogram on the level, and that optimizes the phase of the clock by comparing the parameters. (Kaihei 5-14731).
[0009]
[Problems to be solved by the invention]
However, in the conventional circuit shown in FIG. 4, since the actual analog video signal includes noise components and waveform distortion such as ringing, the dot difference value of the A / D converted video signal is cyclically added. When the maximum value is obtained, there is a problem that, due to the nature of the dot difference, if the difference value is cyclically added while including noise, the calculation result is not stabilized and erroneous detection is performed. The same is true when there is waveform distortion such as ringing. Ringing occurs at the contour part (edge part) of the video, and when there is a rising edge of the dot clock at this point, it is erroneous compared to the stable part of the video waveform. Since the maximum value and the minimum value are sampled, the phase detection result is incorrect.
[0010]
Further, in the conventional circuit described in Japanese Patent Laid-Open No. 5-14731, it is necessary to detect a histogram and calculate entropy for each step, so that the load on the arithmetic circuit is heavy and it is easy to calculate entropy. In addition, the input analog video signal has a problem that the video changes in stages and is limited to a gray scale having a certain level for each stage.
[0011]
The present invention has been made in view of the above points, and is a grid having an automatic clock phase adjustment circuit that can always stably adjust the clock to the optimum phase without being affected by noise and waveform distortion of the digital video input signal. An object is to provide a digital display using a device .
[0012]
Another object of the present invention is that the analog video signal used for phase adjustment is not limited to a specific video signal, and is a grid having a clock phase automatic adjustment circuit that can use many video signals. It is to provide a digital display using a device .
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a digital display that uses a lattice device having a clock phase automatic adjustment circuit, and the clock phase automatic adjustment circuit has a white level and a black level for each dot as an input signal. An A / D converter that inputs an analog signal that alternately changes , samples the input signal with a clock having a period of one dot and converts it to a digital signal, and divides one period of the clock into n (n is 2 or more) A clock generation circuit that generates one time-division pulse selected from the outside among n time-division pulses set in advance) and outputs it as a clock to the A / D converter, and each is managed with a unique ID After sequentially switching the n memories and the n memories and writing the digital signal from the A / D converter to each memory for each first predetermined period, A storage signal in parallel from number of memory compared with the memory controller for reading at a second predetermined period unit, the storage signals read out in parallel from n memory every second predetermined time period, the center therein The memory ID holding unit that repeats storing the ID of the memory from which the memory signal that is the value is read for all the memory signals of the n memories, and the IDs from the memory ID holding unit are received, and the largest ID among them a detector for detecting a n number of time-division pulse by controlling a clock generating circuit, causes sequentially selects outputted switched every first predetermined period, of the n memory by controlling the memory controller A digital signal is written in the memory of the ID corresponding to the time division pulse output from the clock generation circuit, and one time division pulse corresponding to the ID from the detection unit is used as a clock to the A / D converter. Constant and is obtained by a configuration and a processing unit that controls to output the divided pulse time from the clock generating circuit.
[0014]
Here, the analog signal is an analog video signal, the n memories are line memories, the clock is a dot clock, the first predetermined period is a predetermined line period, and the second predetermined period is a dot clock. It is characterized by a period.
[0015]
In the present invention, when there is waveform distortion such as ringing in the analog signal, or when noise is superimposed, the analog signal level changes sharply even during a period of a constant level, and the period is short. On the other hand, the period of a certain level in which waveform distortion and noise are not superimposed is relatively long, so that the clock value when the median value obtained by sampling the analog signal can be held in the line memory most often is stored. Since it can be determined that the phase is a phase in which a period of a certain level where the above waveform distortion and noise are not superimposed can be sampled, one time-division pulse corresponding to the ID having the largest median value from the detection unit is represented by A / It is automatically determined as a clock to the D converter.
[0016]
Further, since the present invention is to achieve the above object, a memory control unit, to each of the n memory, the writing of digital video signal from the A / D converter in the central portion of the screen by a first predetermined time period Features. According to the present invention, a digital signal during a period when an image in one screen is stable can be written in the line memory.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit diagram of an embodiment of an automatic clock phase adjusting circuit in a digital display according to the present invention. In the figure, an analog video signal for adjustment, in which a white level and a black level are alternately repeated in a dot cycle, is supplied to an A / D converter 1, where it is sampled by a dot clock from a PLL circuit 9 and digitally After being converted into a video signal, it is supplied to the memory 2.
Here, based on the count value generated by the line counter 6 that receives the horizontal synchronizing signal and the vertical synchronizing signal of the input analog video signal as input, a stable portion of the video in one screen is sent from the central processing unit (CPU) 8. The digital video signal of the line (center of the screen) is selected and written into the memory 2 based on the memory control signal from the memory control unit 7.
[0018]
Here, the CPU 8 has n dot clocks having the same frequency as the dot clock frequency but different phase angles as the dot clock output from the PLL circuit 9 (hereinafter also referred to as a dot clock having n steps). And the step value is notified to the memory control unit 7 in accordance with the selected phase of the output dot clock of the PLL circuit 9.
[0019]
The memory 2 has the same number n of line memories as the number of steps n, and these n line memories are assigned unique IDs, so that the ID of which line memory is accessed can be known. Is managed. That is, the memory control unit 7 writes the digital video signal from the A / D converter 1 for one line into the line memory having the ID corresponding to the step value notified from the CPU 9.
[0020]
When one line is stored for one clock phase, the CPU 8 instructs the PLL circuit 9 to shift the dot clock phase by one step and notifies the memory controller 7 of the step value shifted. As a result, a dot clock of the next selected phase is generated from the PLL circuit 9 and supplied to the A / D converter 1 to sample the input analog video signal and output the digital video signal, and the previous ID of the memory 2 is output. The value is written in the line memory that becomes the next ID of the. This is repeated for all the dot clocks with n steps.
[0021]
Here, when the number of steps is n = 64, 64 time-division phase pulses obtained by equally dividing the dot period into 64 in 64 line memories from ID = 0 to ID = n−1 = 63 in the memory 2. Digital video signals for a total of 64 lines, each sampled by 64 types of dot clocks, are stored separately.
[0022]
Subsequently, the stored digital video signals are read out in parallel in units of dots from the 64 line memories in the memory 2 and supplied to the median value detection circuit 3, where the same pixels in each line memory are read out for each dot. The values are compared and the median value is detected. The memory ID holding circuit 4 holds the ID of the line memory that stores the median value detected by the median value detection circuit 3 as the number of times the median value is detected. Similarly, this operation is repeated for one line for each dot. Note that the detection period may not be one line, and by setting several lines as the detection period, the memory capacity of the memory 2 increases, but the accuracy can be further improved.
[0023]
Next, the ID of the line memory held by the memory ID holding circuit 4 for a predetermined memory capacity is input to the maximum / minimum holding number ID detection unit 5, where the line memory having the largest median value is stored. The ID and the ID of the line memory having the smallest median value are detected. Since the ID of the line memory is one-to-one with the step of the dot clock, the maximum / minimum holding number ID detection unit 5 performs the phase (step) of the dot clock corresponding to the ID of the line memory storing the largest median value. Are determined to be in the most stable phase, and conversely, it is determined that the dot clock phase (step) corresponding to the ID of the line memory indicating the minimum number of holding times is out of phase.
[0024]
When the input analog video signal has little noise and the waveform is clean, the stable period is long with a period of 1 dot, and therefore there may be a plurality of line memory IDs indicating the maximum number of holding times instead of one. In this case, the dot clock phase corresponding to the line memory ID indicating the maximum number of holdings around 1/2 of the total number of steps is selected from the dot clock phase (step position) corresponding to the line memory ID indicating the minimum holding number. As a result, the most stable clock phase can be determined.
[0025]
【Example】
Next, an embodiment of the clock phase automatic adjustment circuit of FIG. 1 will be described with reference to the timing charts of FIGS. An existing test signal is used as the input analog video signal. For example, when the waveform is viewed on one line such as a cross hatch, a video signal in which the white level and the black level change alternately for each dot is most effective for detection. FIG. 2A shows an analog video signal in which the white level and the black level are alternately changed for each dot, and waveform distortion and noise are superimposed. This analog video signal will be described below as an example.
[0026]
FIG. 2B shows the gradation of the analog video signal shown in FIG. 2A, and FIG. 2C shows the dot clock output from the PLL circuit 9 shown in FIG. Here, since the number n of steps in which the dot clock phase can be varied is set to “16”, as shown in FIG. 2C, the dot clock is 16 time-division pulses obtained by dividing the dot period into 16 equal parts, The phase of each dot clock is indicated by IDs from ID0 to ID15.
[0027]
First, the digital video signal A / D converted by the A / D converter 1 of FIG. 1 using the dot clock when ID = 0 is stored in the line memory ID 0 of the memory 2. The memory value of the ID0 line memory is indicated by ID = 0 in FIG. In the example of FIG. 3, the values 118, 134,... Are stored in the line memory of ID0, and a digital video signal for one line is stored.
[0028]
After storing the digital video signal for one line in the ID0 line memory, the dot clock phase of the PLL circuit 9 is shifted by one step, and the same operation as when ID = 0 is performed with the dot clock when ID = 1. A digital video signal for one line is stored in the line memory when ID = 1 in the memory 2 of FIG. The stored memory value of the line memory when ID = 1 is stored for one line as 178, 70,... As the memory value when ID = 1 in FIG. Thereafter, by performing this operation for all the steps, the digital video signals sampled at the respective dot clock phases are stored in the line memories of ID = 0 to 15 one line at a time.
[0029]
Next, the stored digital video signals are read out in parallel in units of one dot from the 16 line memories with ID = 0 to 15, and the median value is detected by comparing the dot values of the respective line memories in the median value detection circuit 3. . In the example of FIG. 3D, as shown in FIG. 3E, the value 200 is selected as the median value for the first dot, and the value 56 is selected as the median value for the second dot. The median is a value located at the center when n quantities are arranged in the order of size. Here, n is 16 and an even number, so strictly speaking, the average value of the eighth and ninth values. However, one of the ID of the eighth value and the ID of the ninth value is the median ID. The memory ID holding circuit 4 in FIG. 1 holds the number of times of the median value of the line memory ID that has held the median value detected by the median value detection circuit 3.
[0030]
In the example of FIGS. 2 and 3, ID = 10 is held for both the first dot and the second dot, as shown in FIG. At this time, the median retention count of the memory with ID = 10 is “2”. The median retention count of the other ID memories remains “0”. After the detection of the median value for each dot and the retention of the memory ID are completed for the dot for one line, the line memory ID and the most frequent number of detections of the median value detected by the maximum / minimum retention number ID detection unit 5 in FIG. A line memory ID having a small number is detected.
[0031]
Here, in the maximum / minimum holding number ID detection unit 5, assuming that ID = 10 indicates the maximum value and ID = 0 indicates the minimum value, the CPU 9 shown in FIG. The phase is determined to be a dot clock with the best phase suitable for sampling, and the dot clock phase when ID = 0 indicating the minimum value is determined to be a dot clock with a phase that is not suitable for sampling. . By selecting the dot clock when ID = 10, it is possible to automatically detect the phase of the dot clock stably and in phase even if the analog video signal contains waveform distortion and noise.
[0032]
The present invention is not limited to the above-described embodiment. For example, the PLL circuit 9 has been described so as to selectively output one time-division pulse among time-division pulses obtained by dividing the dot period into n equal parts. However, it is only necessary to be divided into n, and it is not necessarily required to be equally divided. The present invention can also be applied to analog signals other than analog video signals.
[0033]
【The invention's effect】
As described above, according to the present invention, one time-division pulse corresponding to the ID having the largest median value from the detection unit is automatically determined as a clock to the A / D converter. Even if waveform distortion or noise is included in the A / D converted video signal as the clock to the / D converter, the clock is automatically set to a stable phase with respect to the video signal without erroneously detecting the phase detection result. Adjustment can be performed, and thus flickering of the image can be prevented.
[0034]
Also, according to the present invention, since the clock phase is not adjusted using a histogram or entropy, the input analog video signal is not limited to the gray scale, and any test can be performed as long as there are one or more edges. Signals can also be used for determination. When a signal having a large level difference is used for each pixel, such as a cross hatch, the number of determinations increases, so that the clock phase can be automatically adjusted with higher accuracy.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment of an automatic clock phase adjusting circuit in a digital display according to the present invention.
FIG. 2 is a timing chart (part 1) of the embodiment of the circuit of FIG. 1;
FIG. 3 is a timing chart (part 2) of the embodiment of the circuit of FIG. 1;
FIG. 4 is a circuit diagram of an example of a conventional clock phase automatic adjustment circuit.
FIG. 5 is a timing chart for explaining the operation of FIG. 4;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 A / D converter 2 Memory 3 Median value detection circuit 4 Memory ID holding circuit 5 Maximum / minimum holding frequency ID detection unit 6 Line counter 7 Memory control unit 8 Central processing unit (CPU)
9 Phase-locked loop (PLL) circuit

Claims (5)

A digital display using a lattice device having a clock phase automatic adjustment circuit, the clock phase automatic adjustment circuit,
An A / D converter for inputting an analog signal in which a white level and a black level are alternately changed for each dot as an input signal, sampling the input signal with a clock having the cycle of the one dot, and converting the input signal into a digital signal; ,
Out of n time division pulses obtained by dividing one period of the clock into n (n is a preset number of 2 or more), one time division pulse selected from the outside is generated and sent to the A / D converter. A clock generation circuit that outputs the clock;
N memories each managed by a unique ID;
The n memories are sequentially switched, and the digital signal from the A / D converter is written into each memory for each of a first predetermined period, and then a storage signal is parallelly supplied from the n memories. a memory controller for reading out the period units,
Comparing the storage signals read in parallel from the n memories for each second predetermined period, and storing the ID of the memory from which the storage signal that is the median value thereof is read out A memory ID holding unit that repeats for all stored signals of the memory of
Receiving the ID from the memory ID holding unit, a detecting unit for detecting the largest ID therein,
The clock generator circuit is controlled to switch the n time-division pulses at every first predetermined period and sequentially select and output, and the memory control unit is controlled to control the clock among the n memories. was written the digital signal to the memory of the ID corresponding to the time-division pulse output from the generator, the clock of the divided pulse when one corresponding to the ID from the detecting unit to the a / D converter determined as a digital display, characterized in that it comprises a processing unit that controls to output the time-division pulse from the clock generation circuit. The analog signal is an analog video signal, said n memory Ri line memory der, the first predetermined time period is a predetermined line period, the second predetermined period and being a dot cycle The digital display according to claim 1. 3. The memory control unit writes the digital video signal from the A / D converter in the central portion of the screen into each of the n line memories for each of the first predetermined periods. Digital display . 3. The digital display according to claim 1, wherein the detection unit receives an ID from the memory ID holding unit and detects the smallest ID among them. When a plurality of IDs are input as the largest number of IDs from the detection unit, the processing unit corresponds to the largest ID in the vicinity of n / 2th from one time-division pulse corresponding to the smallest number of IDs. 3. A digital display according to claim 1, wherein a time division pulse is determined as a clock to the A / D converter.

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