JP2000156795A - Sampling clock automatic adjustment device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device that automates adjustment of the frequency and the phase of a sampling clock, when a digital video signal is employed. SOLUTION: This automatic adjustment device is provided with an A/D converter section 101, that receives and samples a video signal for converting the signal into digital video signal data, a storage section 102 that stores the video signal data, an arithmetic processing section 107 that reads the video signal data for adjusting the frequency and phase of a sampling clock, a sampling clock generating section 105 that generates and outputs the sampling clock, a frequency control section 106 that controls the setting a frequency of the sampling clock from the sampling clock generating section 105 by receiving frequency control data from the arithmetic processing section 107, a delay section 103 that supplies a signal delaying the sampling clock to the A/D converter section 101, and a phase control means 104 that applies setting control of the delay in the sampling clock in the delay section 103 to the control data from the arithmetic processing section 107.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an automatic sampling clock adjusting apparatus, and more particularly to an apparatus for automatically adjusting the frequency and phase of a sampling clock used when sampling a video signal.

[0002]

2. Description of the Related Art In order to adjust a sampling clock in an A / D (analog / digital) converter when converting an analog video signal into a digital signal, conventionally, data of a plurality of types of signals are preset in advance. A technique of performing signal discrimination and calling out data of a specific signal is used. In addition, when the input video signal is an unknown signal, the operator in charge of both frequency adjustment and phase adjustment visually adjusts the monitor screen.

For automatically adjusting a sampling frequency when converting a video signal into a digital signal, for example, Japanese Patent Application Laid-Open No. 5-347768 discloses a digital signal which is converted into a digital signal by an A / D converter and written into an image memory. The video signal is read out, the number of moire generated in the video signal is counted by the moiré counting unit, and the sampling number output by the clock control unit is adjusted to the number of pixels for one horizontal scanning line of the input video signal based on the moiré number. Such a configuration has been proposed.

[0004]

However, in this conventional automatic adjustment method, the frequency of the sampling clock can be automatically adjusted, but only when the phase of the sampling clock is correctly matched with the input video signal.
The automatic adjustment function works effectively.

At the time of normal adjustment, the phase of the sampling clock does not always match the input video signal correctly, and even if the above-mentioned conventional automatic adjustment method without the function of adjusting the phase of the sampling clock is applied, The phase cannot be adjusted automatically, and after all, there is no other way than to adjust it manually.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide an apparatus for automatically adjusting the frequency and phase of a sampling clock when a video signal is converted into a digital signal. It is in.

[0007]

According to the present invention, there is provided an A / D converter for inputting a video signal, sampling the video signal with a sampling clock, and converting the sampled video signal into digital signal video signal data. Holding means for storing and holding the video signal data sampled by the means, arithmetic processing means for reading the video signal data stored in the holding means and performing arithmetic processing for adjusting the frequency and phase of the sampling clock; Frequency-variable sampling clock generating means for inputting a horizontal synchronizing signal and generating and outputting the sampling clock; receiving frequency control data from the arithmetic processing means; and controlling the frequency of the sampling clock in the sampling clock generating means according to the control data. Frequency control means for setting and controlling the delay time; It said input signal delayed this sampling clock from ring clock generator A
Delay means for supplying a sampling clock to the / D conversion means, phase control means for receiving the phase control data from the arithmetic processing means, and setting and controlling the delay amount of the sampling clock in the delay means according to the control data; , Is provided.

[0008]

Embodiments of the present invention will be described. The embodiment of the present invention includes an A / D conversion unit (101 in FIG. 1) that inputs a video signal, samples the video signal with a sampling clock, and converts it into video signal data of a digital signal.
A holding unit (102 in FIG. 1) for storing and holding the video signal data sampled by the D conversion unit (101 in FIG. 1), and a sampling clock for reading out the video signal data stored in the holding unit (102 in FIG. 1). An arithmetic processing unit (107 in FIG. 1) that performs arithmetic processing for adjusting the frequency and phase of the signal, and a variable frequency sampling clock generation unit (1 in FIG. 1) that receives a horizontal synchronization signal and generates and outputs a sampling clock.
05) and a frequency control unit (107) that receives the control data of the frequency from the arithmetic processing unit (107 in FIG. 1) and sets and controls the frequency of the sampling clock in the sampling clock generation unit (105 in FIG. 1) according to the control data. 1 in FIG.
06), the delay time is variable, and a signal delayed by inputting the sampling clock from the sampling clock generator (105 in FIG. 1) is converted into an A / D converter (10 in FIG. 1).
1) which receives the phase control data from the arithmetic processing unit (107 in FIG. 1) as a sampling clock and supplies the phase control data to the delay unit (103 in FIG. 1) according to the control data. A phase control unit (104 in FIG. 1) for setting and controlling the delay amount of the sampling clock.

In the embodiment of the present invention, an arithmetic processing unit (107 in FIG. 1) samples an adjustment video signal of a predetermined pattern by an A / D conversion unit (101 in FIG. 1) using a sampling clock of a certain frequency. One line of the sampled data is read from the holding unit (102 in FIG. 1), and the number of minimum points of the sampling data distribution is calculated. When the number N of minimum points is non-zero, N is added to or subtracted from the frequency. The sampling clock of the frequency
The frequency of the sampling clock generator (105 in FIG. 1) is set via a frequency controller (106 in FIG. 1), and the adjustment video signal is sampled by the A / D converter (101 in FIG. 1). When the number N is zero, control is performed so as to end the frequency adjustment.

In the embodiment of the present invention, the arithmetic processing unit (107 in FIG. 1) converts the predetermined adjustment video signal into an A / D converter (101 in FIG. 1) using a sampling clock having an adjusted frequency. ), The delay amount of the delay unit (104 in FIG. 1) is sampled by the phase control unit (104 in FIG. 1) with the delay amount increased by a unit step from the time of the previous sampling. The sampling data is larger than the previous sampling data, and the delay amount of the delay unit (103 in FIG. 1) is set to be larger than that in the current sampling by the phase control unit (1 in FIG. 1).
If the delay time is larger than the next sampling data to be sampled with the delay amount increased by the unit step via step 04), the adjustment process is terminated assuming that the delay amount has been adjusted.
Note that the delay amount in the delay unit may be reduced from the maximum delay amount for each unit step.

According to another embodiment of the present invention, a delay unit having a variable delay time, receiving a horizontal synchronization signal and outputting a delayed signal, and receiving a horizontal synchronization signal delayed from the delay unit is input. A sampling clock is generated and output.
A sampling clock generation unit for supplying to the / D conversion unit;
The frequency control unit receives the control data of the frequency from the arithmetic processing unit, sets and controls the frequency of the sampling clock in the sampling clock generating unit according to the control data, and the phase control unit controls the phase from the arithmetic processing unit. It may be configured to receive control data and set and control a delay amount of a horizontal synchronization signal in the delay unit in accordance with the control data. Hereinafter, the present invention will be described in detail with reference to examples.

[0012]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Referring to FIG. 1, the present embodiment employs an A / D
It includes a conversion unit 101, a sampling data holding unit 102, a delay unit 103, a phase control unit 104, a sampling clock generation unit 105, a frequency control unit 106, and an arithmetic processing unit 107.

The A / D converter 101 receives, as an adjustment signal, a video signal in which a character string or a vertical stripe having no intermediate color is displayed over the entire screen. The video signal input to the A / D converter 101 is supplied to the sampling clock generator 1
The data is sampled by the sampling clock generated in step S <b> 05 and held in the sampling data holding unit 102.

The arithmetic processing unit 107 receives the data held in the sampling data holding unit 102 and controls the frequency control unit 106 and the phase control unit 104 so that the data becomes appropriate data.

The sampling clock generator 105 generates a sampling clock based on the control data output from the frequency controller 106. Delay unit 10
3 varies the delay time according to the control data from the phase control unit 104. The sampling clock from the sampling clock generation unit 106 is input to the delay unit 103 and is delayed and supplied as a sampling clock of the A / D conversion unit 101.

The operation of one embodiment of the present invention will be described.

As an input video signal for adjustment, a video signal in which a character string without intermediate colors or vertical stripes (for example, a black background and white vertical stripes) are displayed over the entire screen is input to the A / D converter 101.

The A / D converter 101 comprises an A / D converter, and samples an input video signal with a sampling clock. At this time, a case is considered where the input video signal is a character string of white alphabet “H” characters (background is black). As shown in FIG. 2A, it can be said that the uppermost row (line) of the “H” character is properly sampled when it is sampled by the sampling clock 1.

On the other hand, as shown in FIG. 2B, in the case of the sampling clock 2, since the frequency is shifted,
It matches at one sampling point (the sample value is 255) but does not match at another sampling point (the value of the sample point that should originally be 255 is 2
00).

As shown in FIG. 2C, in the case of the sampling clock 3, since the phase is shifted, the sampling points do not coincide with each other.

The adjustment video signal data sampled by the A / D conversion unit 101 is supplied to a sampling data holding unit 102.
Is held.

The sampling data holding unit 102 is composed of a memory, and the adjustment video signal data sampled by the A / D conversion unit 101 is written in, and read out by the arithmetic processing unit 107. The amount of data held in the memory is one horizontal scanning period (referred to as "one line").

The arithmetic processing unit 107 reads out the video signal data held by the sampling data holding unit 102 and determines whether the data sampled by the current sampling clock is appropriate for the video signal. . This determination method will be described.

Here, the A / D converter 101 is an 8-bit A / D converter (digital output code is 0 to 2).
55) will be described. A / D converter 1
As an output of 01, data of 256 gradations is obtained. It is assumed that the data of the lowest brightness value is “0” and the data of the highest brightness value is “255”.

As shown in FIG. 2A, when sampling is performed at the sampling clock 1, the data of the character portion is "2".
55, and the portion without a character (background) is "0", that is, the video signal data correctly sampled by the A / D converter 101 can originally take only "0" or "255". And if other data is obtained,
This means that the frequency or phase of the sampling clock is not set correctly.

First, the arithmetic processing unit 107 controls the frequency control unit 106 so as to match the frequency.
If the frequencies do not match, as shown in FIG.
The sample value of the character part data is "200",
It does not become “255”. The arithmetic processing unit 107 controls the frequency control unit 107 so that, for example, the sample value with the value “200” becomes “255”.

When the phases are not matched, FIG.
As shown in (c), the sample value does not become “255”. At this time, the number of sampling clocks (frequency)
If is set correctly, the sample value of the character part is
Everything becomes uniform. That is, the frequency control unit 106 may be controlled so that the sample values of the character portion are all uniform.

As an example, consider a case where a signal whose sampling clock number is 800 per line is input.

First, it is assumed that 795 sampling clocks are input per line, and sampling data is obtained.

When the value of the sampling data is "0",
Since this part is not a character part but a background part, this part is ignored in order to speed up the arithmetic processing.

As shown in FIG. 3, five minimum points of the sampling data of the character portion appear. That is, by controlling the frequency control unit 106 as in the following equation (1), the frequency of the sampling clock is set correctly.

PIXELCLK = PIXELCLK0 + N (1)

Here, PIXELCLK is the optimum number of sampling clocks of the input signal, PIXELCLK0 is the current number of sampling clocks, and N is the minimum number of sampling data.

On the other hand, also at the frequency 805 of the sampling clock per line, five minimum points appear. In this case, when the above equation (1) is applied, the sampling clock is 810, and the difference is further increased. When the difference is larger than the last time, the difference is matched by setting N from the previous state to -N with a minus sign.

FIG. 4 is a flowchart showing the processing of the arithmetic processing unit 107.

Any sampling clock (= PIXE)
LCLK) is input (step S1), sampling data is obtained (step S2), the number (N) of the minimum points of the data distribution is calculated (step S3), and if N is not 0 (step S4), the sampling clock PIXEL
As CLK + N or PIXELCLK-N (step S5), the process proceeds to step S2 for acquiring sampling data, and if N is 0, the frequency adjustment ends.

If the frequencies match, the phases are adjusted next. The phase may be controlled by controlling the phase control unit 104 such that the sampling data values of the character portion of the sampling data holding unit 102 are all “255”.
Considering the error of the signal level, the value of the sampling data of the character portion is not always "255", so it is assumed that the phase coincides where the value of the sampling data becomes maximum.

Since the data to be compared are the same for the character portions, the comparison processing is performed on only a few character portions, so that the processing in the arithmetic processing section 107 can be simplified.

The phase control unit 104 includes the delay unit 10
3 controls the delay time. Phase control unit 104
The sampling clock is delayed by one step in accordance with the control signal from the CPU, and the sampling data is compared for each step.

The sampling data at a certain step is
When the sampling data is larger than the sampling data before one step and larger than the sampling data after one step, the value of the sampling data at the step is the maximum value, and thus, the phases match at the step. . This is shown in the following equation (2).

D _STEPN-1 <D _STEPN D _{STEPN + 1} <D _STEPN ... (2)

Where D _STEPN-1 is the data of the previous step, D _STEPN is the data when the phases match, and D _{STEPN + 1}
Is the data after one step.

In one embodiment of the present invention, the sampling clock generator 105 is a programmable PLL capable of selecting and outputting a plurality of frequencies by appropriately selecting a frequency division value.
(Phase Locked Loop) circuit is used.

The frequency control section 106 variably sets the frequency by controlling the frequency dividing ratio of the frequency dividing circuit in the PLL circuit.

Next, a second embodiment of the present invention will be described. In the above embodiment, processing is performed for one line (one horizontal scanning period). However, since there is no video signal in the vertical blanking period (referred to as “V blanking period”), the amount exceeding the V blanking period is used. When the processing is performed using the sampling data of (1), more accurate processing can be performed.

In the embodiment shown in FIG.
Numeral 3 is provided at a stage subsequent to the sampling clock generation unit 105 and performs phase adjustment by delaying the sampling clock. The delay unit receives the horizontal synchronization signal and delays the horizontal synchronization signal to generate the sampling clock. It may be configured to supply to the unit 105.

In consideration of errors and noises at the time of frequency adjustment and phase adjustment, video signals, and sampling, the arithmetic processing unit 107 may perform arithmetic processing with a margin for recognizing data values.

[0048]

As described above, according to the present invention,
This has the effect that frequency adjustment and phase adjustment of the sampling clock can be automated.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining an embodiment of the present invention.

FIG. 3 is a diagram for explaining one embodiment of the present invention.

FIG. 4 is a flowchart illustrating a frequency adjustment process according to an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 101 A / D conversion unit 102 Sampling data holding unit 103 Delay unit 104 Phase control unit 105 Sampling clock generation unit 106 Frequency control unit 107 Operation processing unit

Claims (8)

[Claims] 1. A method for inputting a video signal, sampling the video signal with a sampling clock, and converting the input video signal into video signal data of a digital signal.
/ D conversion means; holding means for storing and holding the video signal data sampled by the A / D conversion means; reading out the video signal data stored in the holding means to determine the frequency and phase of the sampling clock. Arithmetic processing means for performing arithmetic processing for optimal adjustment; variable frequency sampling clock generating means for generating and outputting the sampling clock; receiving frequency control data from the arithmetic processing means in accordance with the control data Frequency control means for setting and controlling the frequency of the sampling clock in the sampling clock generating means; and a delay time variable, a sampling clock from the sampling clock generating means being input, and a signal obtained by delaying the signal being input to the A / D converter. Delay means for supplying the conversion means with a sampling clock; A phase control means for receiving control data of the phase from the arithmetic processing means and for setting and controlling the amount of delay of the sampling clock in the delay means in accordance with the control data; . 2. The apparatus according to claim 1, wherein said sampling clock generating means inputs a horizontal synchronizing signal, and generates and outputs a sampling clock of said frequency based on said horizontal synchronizing signal and a frequency setting from said frequency control means. The automatic sampling clock adjusting device according to claim 1. 3. A method for inputting a video signal, sampling the video signal with a sampling clock, and converting it into video signal data of a digital signal.
/ D conversion means; holding means for storing and holding the video signal data sampled by the A / D conversion means; reading out the video signal data stored in the holding means to determine the frequency and phase of the sampling clock. Arithmetic processing means for performing arithmetic processing for optimal adjustment; delay means having a variable delay time, receiving the horizontal synchronizing signal and outputting a signal obtained by delaying the horizontal synchronizing signal; , And generates and outputs the sampling clock.
A variable frequency sampling clock generating means for supplying to the / D converting means; receiving the frequency control data from the arithmetic processing means, and setting and controlling the frequency of the sampling clock in the sampling clock generating means according to the control data. Frequency control means, and phase control means for receiving control data of the phase from the arithmetic processing means and setting and controlling the amount of delay of the horizontal synchronization signal in the delay means in accordance with the control data. Automatic sampling clock adjustment device. 4. The arithmetic processing unit reads out from the holding unit a predetermined number of sampled data obtained by sampling the adjustment video signal of a predetermined pattern by the A / D conversion unit with a sampling clock of a certain frequency. The number of the minimum points of the sampling data distribution is calculated, and when the number N of the minimum points is non-zero, the value of the frequency obtained by adding or subtracting the N from the frequency is used as a new sampling clock frequency, and When the adjustment video signal is sampled by the A / D converter with the sampling clock of the newly set frequency set in the sampling clock generator through the controller, and the number N is zero. And controlling the automatic adjustment process to end assuming that the frequency adjustment has been completed. Sampling clock automatic adjustment device according to any one of. 5. The method according to claim 1, wherein the arithmetic processing means performs an N-th (where N is positive) sampling data obtained by sampling the adjustment video signal of the predetermined pattern with the sampling clock having the adjusted frequency by the A / D conversion means. A), the delay amount of the delay means is increased or decreased by a unit step as compared with the sampling clock of the integer A).
The value of the (N + 1) th sampling data sampled by the / D conversion means is larger than the value of the Nth sampling data, and the delay amount of the delay means is increased or decreased by a unit step as compared with the time of the (N + 1) th sampling data. If the delay amount is larger than the (N + 2) -th sampling data sampled by the A / D conversion means with the sampling clock, the delay amount is adjusted and the automatic phase adjustment process is terminated. The sampling clock automatic adjustment device according to claim 1. 6. The sampling clock according to claim 3, wherein the adjustment video signal comprises a maximum value and a minimum value of lightness and a predetermined character pattern or vertical stripe pattern not including an intermediate color. Automatic adjustment device. 7. The arithmetic processing means according to claim 1, wherein said adjusting video signal of a predetermined pattern is sampled by said A / D converting means at a sampling clock of a certain frequency by a predetermined number of sampling data corresponding to background image data. 7. The automatic sampling clock adjusting device according to claim 6, wherein the process is skipped. 8. The storage device according to claim 1, wherein said arithmetic processing means is configured to execute one line of sampling data of a predetermined number of sampled data sampled by said A / D conversion means at a sampling clock of a certain frequency. 5. The frequency and phase adjustment processing is performed by reading data for a period of time that exceeds the vertical blanking period.
8. The automatic sampling clock adjustment apparatus according to any one of claims 1 to 7.