JP3306020B2 - Video clock automatic setting device and automatic setting method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video apparatus for automatically setting a frequency dividing ratio of a PLL (Phase-Lock Loop) frequency dividing circuit used for a circuit for generating a video clock. The present invention relates to an automatic clock setting device and an automatic clock setting method.

[0002]

2. Description of the Related Art In digital video equipment, a fixed frequency used when digitizing a video signal is controlled by a PLL.
Often generated by a frequency divider.

[0003] The frequency division ratio of the PLL frequency divider circuit varies depending on the input image. The frequency division ratio of the PLL frequency dividing circuit is determined by the following H from the falling or rising of H-SYNC.
-Set by the number of clocks until SYNC falls or rises.

[0004] Incidentally, when the input video signal is converted into a digital signal by an A / D converter or the like in a state where the frequency does not match the input video, jitter occurs and the image quality deteriorates. Therefore, the frequency division ratio corresponding to the input video signal is indispensable.

[0005]

By the way, in the above-mentioned conventional digital video equipment, a waveform is observed by an oscilloscope, and a value obtained by the waveform observation is calculated. Then, by using software having a set value program, the number of clocks from the falling or rising edge of H-SYNC to the falling or rising edge of the next H-SYNC is searched, whereby the dividing ratio of the PLL divider circuit is obtained. Has been set.

However, with such a method, it is difficult to obtain an accurate value of the frequency division ratio of the PLL. This is because the set values are limited to preset values (not all).

Therefore, in order to obtain an accurate value, a manual setting is performed while checking a video signal. In this case, there is a problem that many years of experience and intuition are required.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and an image clock automatic setting device and an automatic setting method capable of easily and reliably setting a frequency dividing ratio of a PLL frequency dividing circuit. That can be provided.

[0009]

According to the present invention, there is provided an automatic video clock setting device comprising: a PLL frequency dividing means for generating a constant frequency when an analog video signal is digitized;
A / D conversion means for converting an analog video signal into a digital signal based on a frequency, binarization means for performing a binarization process on a signal converted into digital by the A / D conversion means, and binarization The signal binarized by the means is
Serial / parallel conversion means for distributing each pixel ,
One pixel assigned by real / parallel conversion means
First and second counting the number of clocks in each video display period
A second video period count circuit, and the first and second
1V-SYNC period corresponding to video period count circuit
The maximum value of the horizontal image display period during
And first and second maximum value detection circuits for detecting
The video display period for each pixel is detected based on the counting result.
And the video display period is not constant for each horizontal
The horizontal video display period from the maximum value of the horizontal video display period
A video period detecting means for detecting the first and second detected
2 and the first and second maximums
The first and second images are compared with the output from the value detection circuit.
When the output of the period count circuit is the first and second maximum value detection times
If the output from the road is smaller than the
In the opposite case, decrease the frequency division ratio of the PLL frequency dividing means.
PLL frequency division ratio determining means for determining the frequency division ratio as described above. The first and second video period counting circuits include a counter for counting the number of clocks in a video display period of the video signal converted into a digital signal by the A / D converter, and an output from the binarization unit. H
A latch circuit for latching the output from the counter during the level may be provided. The first and second maximum value detection circuits include first and second maximum value detection circuits.
And a maximum value latch register for latching the maximum value and a comparator for comparing the number output for each horizontal period from the video period counting means with the current number of horizontal pixels. Can be. Further, the video display period from the fall or rise of H-SYNC to the fall or rise of the next H-SYNC can be automatically adjusted by the automatic position adjusting means. Further, the automatic position adjusting means includes a video memory for storing one frame of the signal converted into a digital signal by the A / D converter, and a falling edge of H-SYNC of the video signal for one frame stored in the video memory. Counter for counting the number of clocks corresponding to the period from to the video display period, a comparator for comparing the output of the counter with the number of clocks determined by the PLL dividing ratio determining means, and a comparison result by the comparator And a video period setting value determining circuit for determining a setting value for adjusting a position of a video display period between the falling or rising of H-SYNC and the falling or rising of the next H-SYNC based on Can be 7. The automatic setting method of the video clock automatic setting device according to claim 6, wherein a step of generating a constant frequency when digitizing the analog video signal and a step of converting the analog video signal into a digital signal based on the frequency.
If, with respect to the signal which has been converted to digital form by A / D converter, and performing binarization processing, and the signal binarized by the binarizing means, allocates for each pixel step,
The number of clocks during the video display period for each pixel
When the video display period for each pixel is detected from the count result,
If the video display period is not constant for each horizontal, 1V
-The maximum value of the horizontal video display period during the SYNC period is
A step of detecting a flat image display period, and for each detected pixel
Video display period and horizontal video display period detected from the maximum value
And the video display period for each pixel is horizontal video display
If it is smaller than the period, increase the frequency division ratio, and vice versa.
Determines the frequency division ratio to reduce the frequency division ratio
And a step . Further, a step of latching the counted output while the binarized output is at the H level may be included. Further, it is possible to be included and the step of latching and comparing the number of counts is outputted every horizontal period and the number of horizontal pixels in the current, the maximum value. Also, H-SYN
Automatically adjusts the video display period from the fall or rise of C to the fall or rise of the next H-SYNC
Steps may be included. A step of storing the digitally converted signal for one frame;
A step of counting the number of clocks corresponding to a period from the fall of H-SYNC of the stored one-frame video signal to the video display period, the output of the count, and the number of clocks for which the division ratio is determined the step of determining and comparing, comparison based on the result, the setting values for adjusting the position of the image display period between the falling or rising of the next H-SYNC falling or the rising of the H-SYNC bets And can be included. In the video clock automatic setting device and the automatic setting method according to the present invention, the video signal converted into digital by the A / D conversion unit based on the frequency from the PLL frequency dividing unit is set to 2 bits.
The binarization processing is performed by the binarization unit, the signal binarized by the serial / parallel conversion unit is assigned to each pixel, and then the 1 signal assigned by the video period detection unit is assigned.
The video display period for each pixel is detected, and the output of the video period detection unit is output by the PLL frequency division ratio determining unit.
The frequency division ratio of the L frequency dividing means is compared, and the frequency dividing ratio is determined so as to match the output of the video period detecting means.

[0010]

Embodiments of the present invention will be described below.

FIG. 1 is a block diagram showing an embodiment of an automatic video clock setting device according to the present invention. FIG. 2 is a diagram for explaining the principle of operation of the automatic video clock setting device of FIG. 3 is a block diagram for explaining the video period count circuit of FIG. 1, FIG. 4 is a diagram for explaining the operation principle of the video period count circuit of FIG. 3, and FIG. 5 is a maximum value detection circuit of FIG. FIG. 6 is a block diagram for explaining FIG.
Block diagram for explaining the video period counting circuit of
FIG. 7 is a diagram for explaining the operation of the video clock automatic setting device of FIG.

An automatic video clock setting device shown in FIG. 1 includes an A / D conversion circuit 1, a binarization circuit 2, an S / P (serial / parallel) conversion circuit 3, a PLL frequency division ratio determination circuit 6,
HD generating circuit 7, PLL frequency dividing circuit 8, delay circuit 9, 1 /
The circuit includes a divide-by-2 circuit 10, input terminals 11a to 11c, a video period detection circuit 17A, and an automatic position adjustment circuit 17B.

The A / D conversion circuit 1 converts an analog video signal input from the input terminal 11a into a digital signal. The binarization circuit 2 outputs H to the signal converted to digital by the A / D conversion circuit 1 when the signal is larger than a certain value.
The level is output. If the level is low, the L level is output.

S / P (serial / parallel) conversion circuit 3
Distributes the output from the binarization circuit 2 to the video period count circuits 4A and 4B for each pixel. The PLL frequency dividing ratio determining circuit 6 determines the frequency dividing ratio of the PLL frequency dividing circuit 8 and the delay amount of the delay circuit 9 based on the data output from the video period counting circuits 4A and 4B described later.

HD generation circuit 7 generates an H-level pulse only during one clock period of the falling edge of input H-SYNC. The PLL frequency dividing circuit 8 oscillates a frequency of input H-SYNC × frequency dividing ratio.

The delay circuit 9 delays the frequency oscillated from the PLL frequency divider 8 to a value smaller than the period of the oscillation frequency. The 分 frequency dividing circuit 10 divides the frequency oscillated from the PLL frequency dividing circuit 8 by 、, and generates counters (A, B) 13 a and 13 b and a counter 2 described later.
Give to 1. A video signal,
H-SYNC and V-SYNC are input.

The image period detecting circuit 17A includes image period counting circuits 4A and 4B and maximum value detecting circuits 5A and 5B.

The image period counting circuits 4A and 4B are composed of flip-flop circuits 12a and 12b and counters (A and
B) 13a, 13b and latch circuits (A, B) 14a,
14b.

The counters (A, B) 13a, 13b
PLL frequency-divided by 1/2 by 1/2 frequency dividing circuit 10
The frequency of the frequency divider 8 is counted. Latch circuit (A,
B) 14a and 14b are SRFF (set / reset /
A counter (A,
B) Latch the outputs from 13a and 13b.

The maximum value detection circuits 5A and 5B include comparators (A and B) 15a and 15b and maximum value latch registers (A and B) 16a and 16b. The maximum value latch registers (A, B) 16a, 16b are provided with comparators (A,
B) Latch the maximum value from the outputs from 15a and 15b.

The automatic position adjustment circuit 17B automatically adjusts the video signal to a target position by delaying the video signal in clock units. The flip-flop circuit 18, the video period set value determination circuit 19, The apparatus includes a device 20, a counter 21, and a video memory 22. Here, the target position is a position that matches the number of clocks of the frequency division ratio by the PLL frequency dividing circuit 8 determined by the PLL frequency dividing ratio determining circuit 6.

When the flip-flop circuit 18 automatically adjusts a video signal to a target position, a counter (A,
B) Send an SRFF (set / reset / flip / flop) signal to 13a and 13b.

The video period setting value determination circuit 19 determines a value for automatically adjusting a video signal to a target position.
Comparator 20 detects SR from the falling edge of H-SYNC in FIG.
The number of clocks corresponding to the time until the FF-Q rises is compared with the number of clocks corresponding to the target position determined by the PLL frequency division ratio determining circuit 6.

The counter 21 is a 1/2 frequency dividing circuit 1 for dividing the frequency oscillated from the PLL frequency dividing circuit 8 into 1/2.
Based on the frequency from 0, the number of clocks corresponding to a period from the falling edge of H-SYNC to the rising edge of SRFF-Q of the video signal for one frame stored in the video memory 22 is counted. The video memory 22 stores a video signal for one frame.

Next, the operation of the video clock automatic setting device having such a configuration will be described with reference to FIGS.

First, the operation principle of the video clock automatic setting device will be described with reference to FIG.

As shown in FIG. 2, a general video signal is V-
Synchronization is achieved by SYNC and H-SYNC.
Also, there is a video signal inside these synchronization signals.

The voltage of the video signal generally indicates a higher voltage than the blanking period. Generally, the H-SY
The reference of the image is determined by a clamp circuit utilizing the time from the NC to the start of the image (back porch).

In the present embodiment, it is noted that the voltage during the video display period is higher than the voltage during the backporch period. That is, the video display period is determined from the input video signal, control is performed so that the video display period matches the number of video DOTs, and the frequency division ratio of the PLL frequency dividing circuit 8 is determined. As a result, it has been found that almost 90% or more of the problems do not occur even if a special image at the beginning and end of the image display period is removed.

First, the video signal converted into a digital signal by the A / D conversion circuit 1 of FIG. 1 is binarized by the binarization circuit 2, and then the video period count circuit 4A (4B) of FIG. Thus, the video display period is counted.

That is, as shown in FIG. 4, the input video signal is binarized at a voltage slightly higher than the reference level of the video. When the binary signal is used, the black level is
W. Therefore, the image period counting circuit 4A of FIG.
By (4B), the correction that the location of the black level becomes LOW is performed.

That is, the SRFF (set / reset / reset) of the flip-flop circuits 12a and 12b is controlled by H-SYNC.
When the Q of the (flip flop) signal becomes L level, the counter 13a (13b) is cleared. Then
When the SRFF signal is set to the H level at the first rising of the binarization level, the counter 13a (13b) starts counting.

As the clock in the counter 13a (13b), the frequency generated by the PLL frequency divider 8 is used. Then, the count value of the counter 13a (13b) is latched by the latch circuit 14a (14b) during the binarized H level.

Here, the latch output of the latch circuit 14a (14b) read out at the timing of FIG. 4A is equal to the video display period (the number of horizontal display DOTs) if the frequency division ratio of the PLL frequency divider 8 is correct. Have the same value. Actually, Counter 1
Since 3a (13b) starts counting from 0, the horizontal display DOT number is -1 at the start of counting.

Incidentally, when the video display period is not constant for each horizontal line (there is black at the right and left ends), an accurate result cannot be obtained only with the value of one line.

Therefore, as shown in FIG. 5, the horizontal image display period is determined based on the maximum value of the horizontal image display period detected by the maximum value detection circuit 5A (5B). At this time, the horizontal video display period during the 1V-SYNC period is
Several or all lines are detected.

Here, the maximum value latch register 1 shown in FIG.
The content of 6a (16b) is cleared by V-SYNC. Then, the comparator 15a (15b) compares the number output for each horizontal from the video period counting circuit 4A (4B) of FIG. 3 with the number of horizontal pixels up to now. Value latch register 16a (16b)
Can be changed.

When this operation is performed up to the point just before the next V-SYNC, the value of the horizontal maximum pixel number becomes the maximum value latch register 16.
a (16b). Based on this latched value, the PLL dividing ratio determining circuit 6 of FIG. 1 determines the next dividing ratio of the PLL dividing circuit 8.

That is, the PLL frequency division ratio determining circuit 6 compares the value latched by the maximum value latch register 16a (16b) with the number of horizontal display DOTs. At this time, if the number is smaller than the horizontal display DOT number, the frequency dividing ratio of the PLL frequency dividing circuit 8 is increased, and if it is larger, the frequency dividing ratio is decreased.

At this time, the video period counting circuit 4 shown in FIG.
As shown in FIG. 6, two A (4B) are provided, so that a deviation due to a phase difference between the video signal and the clock generated by the PLL frequency dividing circuit 8 can be detected.

That is, S / P (serial / parallel)
The video display period of the output from the conversion circuit 3 is counted by the counters 13a and 13b of the video period counting circuits 4A and 4B.

At this time, if at least one of the following four conditions is satisfied, the frequency division ratio of the PLL frequency divider 8 is returned to the state before ± 2 under each condition. Further, the clock generated by the PLL frequency dividing circuit 8 is delayed (delayed) by the delay circuit 9 so that the counters 13a and 13b are in the vicinity of the horizontal display. This eliminates the clock shift.

(Condition 1) The counter (A) 13a becomes the same as the horizontal display period 1/2, and the counter (B) 13b
Is the horizontal display period-1, the frequency division ratio of the PLL frequency divider 8 is set to +2. When the lock of the PLL frequency divider 8 is confirmed and the counters (A, B) 13a and 13b are read,
The counter (A) 13a has a horizontal display period of +1 and the counter (B) 13b has a horizontal display period.

(Condition 2) When the counter (B) 13b becomes the same as the horizontal display period and the counter (A) 13a is in the horizontal display period -1, the division ratio of the PLL frequency divider 8 is set to +
Let it be 2. When the counters (A, B) 13a and 13b are read out after confirming the lock of the PLL frequency dividing circuit 8, the counter (B) 13b is in the horizontal display period +1 and the counter (A) 13a is in the horizontal display period.

(Condition 3) When the counter (A) 13a is the same as the horizontal display period and the counter (B) 13b is in the horizontal display period -1, the frequency division ratio of the PLL frequency divider 8 is set to-
Let it be 2. When the counters (A, B) 13a and 13b are read out after confirming the lock of the PLL frequency dividing circuit 8, the counter (A) 13a is in the horizontal display period +1 and the counter (B) 13b is in the horizontal display period.

(Condition 4) When the counter (B) 13b becomes the same as the horizontal display period and the counter (A) 13a is in the horizontal display period -1, the frequency division ratio of the PLL frequency divider 8 is set to-
Let it be 2. When the counters (A, B) 13a and 13b are read out after confirming the lock of the PLL frequency dividing circuit 8, the counter (B) 13b is in the horizontal display period +1 and the counter (A) 13a is in the horizontal display period.

Next, the operation of the automatic position adjusting circuit 17B of FIG. 1 will be described.

As described above, the total number of pixels per H-SYNC is detected from the number of video display pixels per H-SYNC. In this process, as shown in FIG. 7, the number of clocks oscillated by the PLL frequency dividing circuit 8 from the point A to the point B can be determined.

This corresponds to the period from the fall of H-SYNC to the rise of SRFF-Q in FIG. By delaying the video signal in clock units from the number of clocks and the target position determined by the PLL frequency division ratio determining circuit 6, it is possible to automatically adjust the video signal to the target position.

That is, the PLL is controlled by the counter 21.
1 that divides the frequency oscillated from the frequency dividing circuit 8 by half
H-CYN of the video signal for one frame stored in the video memory 22 based on the frequency from the frequency divider 10
The number of clocks corresponding to the period from the fall of C to the rise of SRFF-Q is counted.

Next, the comparator 20 calculates the HS of FIG.
The number of clocks corresponding to the period from the falling of YNC to the rising of SRFF-Q is compared with the number of clocks corresponding to the target position determined by the PLL frequency division ratio determining circuit 6.

Then, based on the comparison output from the comparator 20, the video signal is automatically adjusted to a target position by delaying the video signal in clock units by the video period set value determination circuit 19.

As described above, in the present embodiment, the video signal converted into digital by the A / D converter 1 based on the frequency from the PLL frequency divider 8 is binarized by the binarization circuit 2. After performing the processing, the signal binarized by the S / P (serial / parallel) conversion circuit 3 is distributed for each pixel, and then the video display period for each pixel distributed by the video period detection circuit 17A is detected. At the same time, the output of the video period detecting circuit 17A is compared with the dividing ratio of the PLL frequency dividing circuit 8 by the PLL dividing ratio determining circuit 6 so that the dividing ratio matches the output of the video period detecting circuit 17A. Since the determination is made, the frequency division ratio of the PLL frequency divider 8 can be set easily and reliably.

The number of clocks corresponding to the period from the falling edge of H-SYNC to the rising edge of SRFF-Q in FIG. 4 and the PLL dividing ratio determining circuit 6 determine the number of clocks by the automatic position adjusting circuit 17B. Since the video signal is delayed in clock units from the target position, the video signal can be automatically adjusted to the target position.

In the present embodiment, the case where the number of the image period counting circuits 4A and 4B of the image period detecting circuit 17A is two has been described. However, the present invention is not limited to this, and may be four or more.

[0056]

As described above, according to the video clock automatic setting apparatus and the automatic setting method according to the present invention, the video signal converted into digital by the A / D conversion means based on the frequency from the PLL frequency dividing means. On the other hand, after the binarization processing is performed by the binarization means and the signal subjected to the binarization processing by the serial / parallel conversion means is distributed for each pixel,
In addition to detecting the video display period for each pixel allocated by the video period detection unit, the output of the video period detection unit is compared with the frequency division ratio of the PLL frequency division unit by the PLL frequency division ratio determination unit. Since the division ratio is determined so as to match the output of the video period detection means, the division ratio of the PLL divider circuit can be set easily and reliably.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an automatic video clock setting device of the present invention.

FIG. 2 is a diagram for explaining the operation principle of the video clock automatic setting device of FIG. 1;

FIG. 3 is a block diagram for explaining a video period counting circuit of FIG. 1;

FIG. 4 is a diagram for explaining the operation principle of the video period counting circuit of FIG. 3;

FIG. 5 is a block diagram for explaining a maximum value detection circuit in FIG. 1;

FIG. 6 is a block diagram for explaining the video period counting circuit of FIG. 3;

FIG. 7 is a diagram for explaining the operation of the video clock automatic setting device of FIG. 1;

[Description of Signs] 1 A / D conversion circuit 2 Binarization circuit 3 S / P (serial / parallel) conversion circuit 4A, 4B Video period count circuit 5A, 5B Maximum value detection circuit 6 PLL frequency division ratio determination circuit 7 HD Generator 8 PLL frequency divider 9 Delay circuit 10 1/2 frequency divider 11a to 11c Input terminals 12a, 12b Flip-flop circuits 13a, 13b Counters (A, B) 14a, 14b Latch circuits (A, B) 15a, 15b Comparator (A, B) 16a, 16b Maximum value latch register (A, B) 17A Video period detection circuit 17B Automatic position adjustment circuit 18 Flip-flop circuit 19 Video period setting value determination circuit 20 Comparator 21 Counter 22 Video memory

Continuation of front page (72) Inventor Kazuo Sato 4-2-8 Sakuradai, Nerima-ku, Tokyo Iida Building 2F Electro System Co., Ltd. In-house (56) References JP-A-3-97376 (JP, A) JP-A Heihei 9-297555 (JP, A) JP-A-5-27736 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/14-5/217 G09G 1/16

Claims (10)

(57) [Claims] 1. A PLL frequency dividing means for generating a constant frequency when digitizing an analog video signal; A / D converting means for converting the analog video signal into a digital signal based on the frequency; A binarizing unit for performing a binarizing process on the signal converted into a digital signal by the / D converting unit; a serial / parallel for distributing the signal binarized by the binarizing unit for each pixel Conversion means and the serial / parallel conversion means
Count the number of clocks in the video display period for each pixel
First and second video period counting circuits;
1V-SYNC corresponding to the second video period count circuit
The maximum value of the horizontal video display period during the period of
First and second maximum value detection times detected over all lines
And an image for each pixel from the result of the counting.
While detecting the image display period, the image display period
The maximum of the horizontal video display period when it is not constant for each horizontal
A video period detecting means for detecting the horizontal video display period from the value, and a first and a second video period counting circuit.
Output and output from the first and second maximum value detection circuits.
And comparing the first and second video period count circuits.
The output is different from the output from the first and second maximum value detection circuits.
If it is smaller, the frequency division ratio of the PLL frequency dividing means is increased,
In this case, the frequency division ratio of the PLL frequency dividing means should be reduced.
And a PLL frequency dividing ratio determining means for determining the frequency dividing ratio. 2. The image processing apparatus according to claim 1, wherein the first and second video period counting circuits include a counter for counting the number of clocks in a video display period of the video signal converted into a digital signal by the A / D converter. 2. An automatic video clock setting device according to claim 1 , further comprising a latch circuit for latching an output from said counter while an output from said converting means is at H level. 3. The first and second maximum value detection circuits include a number output from the first and second video period counting means for each horizontal period and a current number of horizontal pixels. The video clock automatic setting device according to claim 1 , further comprising a comparator for comparing, and a maximum value latch register for latching the maximum value. The image display period between the fall or rise of 4. H-SYNC following the H-SYNC falling or the rising of the claims, characterized in that it is automatically adjusted by the automatic position adjustment means The video clock automatic setting device according to any one of claims 1 to 3 . 5. The automatic position adjusting means comprises: a video memory for storing one frame of a signal converted into a digital signal by the A / D conversion means; and a video signal for one frame stored in the video memory. A counter for counting the number of clocks corresponding to a period from the fall of H-SYNC to the video display period; and comparing the output of the counter with the number of clocks determined by the PLL frequency division ratio determining means. A comparator, and based on the comparison result by the comparator, the H-SYNC
And a video period set value determining circuit for determining a set value for adjusting the position of the video display period between the fall or the rise of the H-SYNC and the fall or the rise of the next H-SYNC. The video clock automatic setting device according to claim 4 . 6. A step of generating a constant frequency when digitizing an analog video signal, a step of converting the analog video signal into a digital signal based on the frequency, and converting the analog video signal into a digital signal by the A / D conversion means. to converted signals, and performing binarization processing, the binarization signal by binarizing means, the steps of allocating to each pixel, the image display period of each pixel, which is the distribution Number of clocks
The video display period of each pixel is detected from the count result of
And the video display period is not constant for each horizontal
The horizontal video display period during the 1V-SYNC period
Detecting the horizontal image display period from a maximum value; and determining the detected image display period for each pixel and the maximum value.
Is compared with the horizontal image display period detected from the
Each video display period is shorter than the horizontal video display period
If the frequency division ratio of the frequency is increased,
Determining the frequency division ratio so as to reduce the frequency division ratio
And an automatic setting method for the video clock automatic setting device. 7. During the binarized output is at the H level, the automatic video clock automatic setting device according to claim 6, characterized in that includes the step of latching the count output Setting method. 8. claims, characterized the number of counts is output to each of the horizontal period, and comparing the number of horizontal pixels in the current, to include a step of latching the maximum value 6 3. The automatic setting method of the video clock automatic setting device according to 1. 9. The method according to claim 6, further comprising the step of automatically adjusting the video display period from the fall or rise of H-SYNC to the fall or rise of the next H-SYNC . 9. The automatic setting method of the video clock automatic setting device according to 8 . 10. The digitally converted signal is
A step of storing frames, and an H-SYNC of the stored video signal of one frame.
A step of counting the number of corresponding clock period from the fall to the image display period, and the output of the count, a step of comparing the number of the division ratio determined clock, the comparison result the basis, to include determining a set value for adjusting the position of the image display period between the H-SYNC falling or the rising of the next the H-SYNC falling or rising of Special features
An automatic setting method for the video clock automatic setting device according to claim 9 .