EP0842579A1

EP0842579A1 - Method and apparatus for digitizing video signals especially for flat panel lcd displays

Info

Publication number: EP0842579A1
Application number: EP95926345A
Authority: EP
Inventors: Jerry Rytka; Ray Leerentveld
Original assignee: Litton Systems Canada Ltd
Current assignee: 1294339 Ontario Inc
Priority date: 1995-07-28
Filing date: 1995-07-28
Publication date: 1998-05-20
Also published as: WO1997005740A1

Abstract

A circuit for digitizing an analog video signal using a sample clock signal having an active sample edge, said analog video signal being characterized by a horizontal sync pulse followed by at least one pixel, comprising a phase-locked loop for receiving said horizontal sync pulse and in response generating said sample clock signal at a frequency N times greater than said horizontal sync pulse, said phase-locked loop including a feedback path having a divider for frequency dividing said sample clock signal by N; a first circuit for detecting said at least one pixel and in response generating at least one modified pixel representing an active region of said at least one pixel; a second circuit for receiving and comparing said sample clock signal and said modified pixel and in response generating a control signal representing a degree of phase difference between said sample clock signal and said modified pixel signal; a programmable delay line having a signal input connected to an output of said divider in said feedback path of the phase-locked loop and having a control input connected to said second circuit for receiving said control signal and in response phase shifting said sample clock signal so that said active sample edge is temporally aligned with said active region of said at least one pixel; and an analog-to-digital converter for receiving said sample clock signal and in response digitizing said analog video signal.

Description

Method and Apparatus for Digitizing Video Signals Especially for Flat Panel LCD Displays

Field of the Invention The present invention relates in general to sampling of video signals, and more particularly to a method and apparatus for generating a phase corrected sampling clock for analog-to-digital conversion and/or sampling of various kinds of video signals used to drive a flat panel LCD display.

Background of the Invention

Flat panel LCD displays are, by nature, sampling devices, and the resolution is determined by a fixed matrix of electrodes. In order to obtain a high quality image from a fixed-matrix display, the image must be perfectly aligned with the original video signal in order to avoid side effects such as noisy images, pixel jitter and so forth. The regeneration of an original pixel clock signal is a difficult problem which has been addressed by the prior art, as is the problem of signal synchronization (see Electronic Engineering Times, 19.10.1992, "Integrators Tackle Flat-Panel Displays", page 35, 37) . A number of prior art devices are known for sampling and processing of video signals, as described below.

The most simple known apparatus utilizes an asynchronous and independent clock for sampling a video signal. However, this prior art system is characterized by numerous problems. For example, where the system utilizes a buffer memory, time based fluctuations have been known to occur in the processed video signal due to quantizing errors in the time base resulting from asynchronism between clock pulses. Where the video signal is time-compressed and expanded, the quantizing errors are magnified so that the quality of the picture reproduced from the processed video signal is degraded. Furthermore, since the video signal is a broad band signal, it is necessary to provide a sufficiently high sampling clock frequency to avoid aliasing. However, limitations in the operating speed of the circuit often make generation of such a clock frequency difficult to attain. Therefore, as the sampling clock frequency approaches the video signal band, spurious components may be generated. Since these spurious components appear as noise in a reproduced picture, it is necessary to restrict the video signal band sufficiently and rapidly before processing the video signal. This rapid restriction of the band gives rise to a delay distortion and, as a result, to a waveform distortion, so that, for example, ringing (i.e. uncontrolled oscillation) may be generated.

A number of additional prior art systems of generating a sampling clock signal utilize the concept of a phase-locked loop (PLL) . In such a system, a phase comparator is used for comparing the phase of a horizontal sync signal and the phase of a further signal produced by a frequency divider, for generating an error signal. The error signal is smoothed by a low-pass filter whose output is connected to a voltage-controlled oscillator (VCO) which varies its oscillation frequency in response to the filtered error control voltage level. The sampling clock signal is generated at the output of the voltage-controlled oscillator, and is fed back to the programmable frequency divider which de-multiplies the sampling clock frequency at a preset dividing ratio (N) , for producing the aforementioned further signal applied to the phase comparator. The conventional phase-locked loop described above, relies largely for proper generation of a phase corrected sampling clock signal, on the phase drift between a video pixel and the externally-supplied horizontal sync signal. However, this phase drift can vary with time and temperature. Thus, the generated sampling clock signal can properly sample only video signals which have a fixed and stable phase relationship with the horizontal sync signal.

One variation of the above-discussed prior art phase-locked loop video signal sampling system, is described in U.S. Patent 5,168,360. According to this patent, a reference frequency oscillator provides a first input to the phase comparator of a phase-locked loop which functions as a frequency synthesizer for generating a variable-frequency master clock signal having a frequency which is Nm times the predetermined reference clock frequency. The master clock signal is divided by a further programmable frequency demultiplier by a dividing ratio Ns, to produce the sampling clock signal. The ratio Ns is set from outside the system and is reset by the horizontal sync signal, which is also provided from outside the system.

Another prior art system for sampling video signals is the subject of U.S. Patent 4,772,950. According to this patent, sampling clock pulses are produced by a voltage-controlled oscillator which is instantaneously phase-synchronized with the synchronizing information of the input video signal. During the vertical blanking period, the oscillating frequency of the oscillator is stabilized by a feedback loop comprising a phase comparator which phase compares the oscillating output signal (or a divided signal proportional thereto) , with a reference signal having a constant frequency (or a divided signal proportional thereto) . The oscillating frequency of the voltage-controlled oscillator is controlled in response to the phase error generated by the phase comparator. The oscillator is controlled to at least one of start and stop oscillation in accordance with the synchronizing information.

U.S. Patent 4,996,596 describes a phase synchronizing circuit in which a first phase-locked loop has a plurality of lock ranges, and a second phase-locked loop or automatic frequency control loop has an output characteristic with a single S curve and one wide lock range. The second PLL loop is supplied with a horizontal sync signal which has been separated in a synchronization separating circuit via a band pass filter. The first PLL loop is directly supplied with the horizontal sync signal extracted via the synchronization separating circuit.

The first PLL loop shares a voltage controlled oscillator and a frequency divider with the second PLL loop or AFC loop. The phase synchronizing circuit further includes a circuit for detecting synchronization/non-synchronization of an output of the frequency divider circuit with the horizontal sync signals separated/extracted and synchronization separating circuit, and a switching circuit for activating one of the first PLL loop and the second PLL or AFC loop in response to an output of the synchronization detector circuit.

According to the apparatus disclosed in U.S. Patent 4,751,565, a microprocessor is employed to control a digital genlock. An input analog signal, such as an NTSC video signal, having a signal element that repeats at a first, nominally fixed frequency (e.g. the first positive-going zero crossing of a burst, repeating at line rate) , is used to generate a signal at a second, higher frequency and having a predetermined phase relationship to the repetitive signal element of the input signal. This is accomplished by using a programmable oscillator to generate a clock signal at a frequency that depends on the value represented by a control word applied to the oscillator, and using the clock signal to establish the sample times for an analog- to-digital converter, whereby a succession of digital words representing the amplitude of the analog signal at the time of successive clock signals, is generated. The digital words are then analyzed to identify where, in the succession of digital words, the signal element occurs and to determine the phase angle of the clock cycle at which the signal element occurs. This phase information is used to generate the control word of the programmable oscillator and to establish the desired predetermined phase relationship between the clock signal and the signal element of the input signal. The digital phase- locked loop that is thus provided avoids the disadvantages of an analog phase-locked loop but requires the use of a repetitive signal such as a positive-going zero burst.

U.S. Patent 5,166,641 discloses a phase-locked loop which includes a VCO circuit for generating a recovered data signal and a charge pump circuit coupled to the phase detector for generating an error signal in response to the detected phase difference. The charge pump circuit includes first and second pump generators for respectively providing first and second sets of pump signals, with the pump generators preferably being interconnected to facilitate generation of the error signal. The PLL is designed to alternate between operation in phase correction and phase calibration cycles. During each intervening calibration cycle, a calibration network operates to adjust the second charge pump generator such that the first and second sets of pump signals are precisely balanced when the reference and recovered data signals have a predefined phase relationship. In one embodiment, the predefined phase relationship corresponds to that of the reference and recovered data signals being matched in phase. In this way, inconsistencies in the operating characteristics of the pump generators are precluded from engendering steady-state phase alignment errors between reference and recovery waveforms.

Another solution of a phase-locked loop system having an oscillator providing a phase adjustable output, is disclosed in U.S. Patent 5,153,530. A charge pump circuit is utilized for charging a capacitor in response to a phase difference between first and second input signals. The charge pump circuit comprises a constant current source for providing a first constant current, a constant current sync for absorbing a second constant current, a circuit for substantially equalizing the magnitudes of the first and second constant currents, and a switching circuit for providing the first constant current and the second constant current flowing in opposed directions to the capacitor through an output terminal of the charge pump circuit in responεe to the phase difference between the first and second input signals, to produce a voltage level across the capacitor corresponding to the phase difference. In a phase-locked loop system employing such a charge pump circuit, a phase comparator produces a phase difference signal for controlling the provision of the first and second constant currents by the switching circuit capacitor. The capacitor acts as loop filter for supplying the voltage thereacross as a control voltage to a voltage controlled oscillator of the phase-locked loop system.

The above described methods and apparatus for generating synchronous sampling video signals do not account for normal phase drift between video pixels in the composite RGB video signal and the horizontal sync signal as a function of time and temperature. Consequently, these prior art systems are incapable of recognizing rising and falling edges or individual pixels, thereby resulting in poor images due to sampling on the rising or trailing edges of the individual video pixels.

Summary of the Invention According to the present invention, a system is provided for precise sampling of a video pixel in its active region close to the centre of the pixel, thereby eliminating intensity errors caused by sampling during the rising and/or falling edges of the video pixel. The system of the present invention utilizes a phase-locked loop in combination with a digitally controlled delay line, a luminance transient detector, a pixel generator, a phase comparator and counter, for phase correcting the sample clock signal generated by the phase- locked loop to align with the active area of the modified pixel pulse. The modified pixel pulse omits the rising and trailing edges of a video pixel, and thereby represent only the active portion of the pixel for sampling.

Brief Description of the Drawings

A detailed description of the preferred embodiment is provided hereinbelow with reference to the following drawings, in which:

Figure 1 is a block diagram of the video signal sampling circuit according to the preferred embodiment; Figure 2 is a waveform diagram showing various waveforms generated by the circuitry of Figure 1;

Figure 3 comprisings parts 3A and 3B together, is a schematic diagram of a luminance transient detector and modified pixel generator in the preferred embodiment of Figure 1; Figure 4 co prsing parts 4A and 4B together is a schematic diagram showing error signal generating circuitry in the preferred embodiment of Figure 1; and

Figure 5 is a block diagram of a video signal sampling system according to an alternative embodiment of the invention.

Detailed Description of the Preferred Embodiment

Figure 1 is a block diagram depicting a system for digitizing video signals in accordance with a preferred embodiment of the present invention. The system comprises a phase-locked loop (PLL) implemented via phase detector 1, low pass filter 3, voltage-controlled oscillator (VCO) 5, frequency divider 7 and digitally controlled delay line 9. In operation, phase detector 1 detects any phase difference between the horizontal sync signal and a version of the sample clock signal which is output from voltage control oscillator 5, divided by N in divider 7 and delayed by a controllable amount in delay line 9. Thus, the generated sample clock is N times the frequency of the horizontal sync pulse. Low pass filter 3 smooths (i.e. filters out high frequency components from) the error signal output by phase detector 1, and the DC error signal is applied as a control voltage to VCO 5 which, as indicated above, generates the sample clock. The generated sample clock signal is applied to an A/D converter 11 for digitizing an input analog video signal, in a well known manner.

Phase correction of the sampling clock by the circuitry of Figure 1, will be understood with reference to Figure 2.

The input analog video signal (i.e. RGB waveform A in Figure 2) , is applied to a luminance transient detector 13. Detector 13 detects signal transients which exceed predefined levels on a pixel-by-pixel basis, and in response generates an output signal (i.e. waveform B in Figure 2) indicative of the detected signal transients (i.e. dV/dt) . The detector 13 may be implemented as a simple differentiator followed by an amplifier and comparator, or other type of programmable edge detector.

Modified pixel generator 15 receives the signal output from detector 13 and in response generates a "modified" pixel in the event that the signal output from luminance transient detector 13 (i.e. waveform B) exceeds a predetermined level. By triggering only on transients which exceed predefined levels, the modified pixel generator 15 avoids being triggered due to noise signals. Modified pixel generator 15 is thus triggered by each detected video pixel "start" and in response generates a pulse representing a single "modified" video pixel. The "modification" to each detected pixel comprises wave shaping to eliminate the leading and trailing edges of the video pixel (e.g. the leading edge shown in phantom with reference to waveform A in Figure 2) . Accordingly, the resultant modified pixel represents only the active portion of the pixel for sampling purposes. The modified pixel pulse output from pixel generator 15 is represented by waveform C in Figure 2.

Although a variety of circuits may be utilized to implement the luminance transient detector 13 and modified pixel generator 15, a successful implementation of this circuitry is illustrated in Figure 3.

A phase comparator 17 is provided for comparing the modified pixel pulse (waveform C) with the sample clock signal generated by VCO 5 (i.e. referred to herein as the initial sample clock signal with phase error, as represented by waveform Dl in Figure 2) . Phase comparator 17 generates an error pulse each time the sampling clock signal active edge is positioned outside the active region of the video pixel, as defined by the modified pixel pulse. Thus, with reference to Figure 2, phase comparator 17 generates an error pulse as a result of the positive-going edge (i) of waveform Dl (initial sampling clock signal), as shown in Figure 2. A preferred embodiment of phase comparator 17 is discussed greater detail below with reference to Figure 4.

The phase comparator 17 can be enabled once per video line, in the middle of a line, every few lines, once per frame, every few frames, etc., depending on system requirements, noise and stability. The selective enabling of phase comparator 17 is effected by lock detector 19.

Lock detector 19 receives a pulse signal from phase detector 1 which is proportional to the PLL error, and in response determines the "lock", "no-lock" condition of the phase locked loop. The signal output from lock detector 19 to phase comparator 17 enables the phase comparator 17 only when the PLL is in lock. The error pulse output from phase comparator 17 serves as a clock signal for an up/down counter 21. Counter 21 has a decoded output which is applied to a control input of delay line 9 for delaying the divided sample clock signal by a predetermined amount proportional to the phase error detected by comparator 17, thereby effectively correcting the phase of the sampling clock so that the active edge is approximately centred in the active region of the detected pixel pulse (i.e. active edge (ii) of waveform D2 in Figure 2).

Figure 3 represents blocks 13 and 15 of Figure 1. The capacitor C107 and resistors R91 and R92 represent the dv/dt circuit 13 of Figure 1. Amplifier U31 is a high gain amplifier and amplifier U32 is a comparator for slicing the differentiated signal pulse edges thereby producing a desired length of modified pixel output. A tapped delay line U101 provides different phases of the modified pixel where required for particular applications.

Figure 4 shows an embodiment of phase comparator 17 in which the modified pixel is clocked in with an inverted sample clock. The phase comparator 17 generates error pulses whenever the rising edge of the inverted sample clock is inside the modified pixel period. This ensures a sampling clock phase as per Figure 2. The LOCKDET and CBL- composite blanking inputs receive control signals for enabling the phase comparator 17 only during valid video signal times.

Alternative embodiments and modifications of the invention are possible. For example, in the alternative embodiment of Figure 5, the high frequency digitally programmable delay line 9 is shown connected between the output of VCO 5 and one of the inputs of the phase comparator 17. In this alternative embodiment, operation of the circuit is similar as described in connection with Figure 1, except that the phase comparator 17 and counter 21 generate an error signal for controlling the delay line 9 on a pixel-by-pixel basis, rather than on a line- by-line basis as in Figure 1. Other alternative embodiments are possible without departing from the sphere and scope of the invention as defined by the claims appended hereto.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OF PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A circuit for aligning phase of a clock signal having an active sample edge with an analog video signal, said analog video signal being characterized by a horizontal sync pulse followed by at least one pixel, comprising: a) a phase-locked loop for receiving said horizontal sync pulse and in response generating said clock signal at a frequency N times greater than said horizontal sync pulse, said phase-locked loop including a feedback path having a divider for frequency dividing said clock signal by N; b) a first circuit for detecting said at least one pixel and in responεe generating at least one modified pixel representing an active region of said at least one pixel; c) a second circuit for receiving and comparing said clock signal and said modified pixel and in response generating a control signal representing a degree of phase difference between said clock signal and said modified pixel signal; and d) a programmable delay line having a signal input connected to an output of said divider in said feedback path of the phase-locked loop and having a control input connected to said second circuit for receiving said control signal and in response phase shifting said clock signal so that said active sample edge is temporally aligned with said active region of said at least one pixel.

2. The circuit of claim 1, wherein said phase-locked loop further compriseε: e) a phase detector having two inputs and an output, a first one of said inputε for receiving said horizontal sync pulse and a second one of said inputs being connected to an output of said programmable delay line; f) a low pass filter having an input connected to the output of said phase detector; and g) a voltage controlled oscillator having an input connected to an output of said low pass filter and an output connected to a first input of said second circuit and to an input of said divider.

3. The circuit of claim 1, wherein said firεt circuit further comprises: e) a luminance transient detector for detecting onset of said at least one pixel and in responεe generating a derivative signal thereof; and f) a modified pixel generator for receiving said derivative signal and in responεe generating εaid at leaεt one modified pixel repreεenting said active region of said at least one pixel and in which leading and trailing edges of said at least one pixel are removed.

4. The circuit of claim 1, wherein said εecond circuit further compriεeε: e) a phaεe comparator for receiving and comparing said clock signal and said modified pixel and in response generating a further clock signal in the event said active εample edge iε not temporally coincident with εaid active region of said modified pixel; and f) a counter for receiving said further clock signal and in responεe generating εaid control εignal aε a running count value which iε εelectively incremented in the event said active sample edge precedeε εaid active region and εelectively decremented in the event εaid active εample edge followε said active region.

5. A circuit for digitizing an analog video signal uεing a sample clock signal having an active sample edge, said analog video signal being characterized by a horizontal sync pulse followed by at leaεt one pixel, compriεing: a) a phaεe-locked loop for receiving said horizontal sync pulse and in responεe generating εaid εample clock signal at a frequency N timeε greater than said horizontal sync pulse, said phase-locked loop including a feedback path having a divider for frequency dividing said sample clock signal by N; b) a first circuit for detecting said at least one pixel and in responεe generating at leaεt one modified pixel representing an active region of said at least one pixel; c) a second circuit for receiving and comparing εaid sample clock signal and said modified pixel and in responεe generating a control εignal representing a degree of phase difference between said sample clock signal and said modified pixel signal; d) a programmable delay line having a εignal input connected to an output of said divider in said feedback path of the phase-locked loop and having a control input connected to said second circuit for receiving said control signal and in response phase εhifting εaid εample clock εignal εo that said active sample edge iε temporally aligned with εaid active region of εaid at least one pixel; and e) an analog-to-digital converter for receiving said εample clock εignal and in response digitizing εaid analog video signal.

6. The circuit of claim 5, wherein said phase-locked loop further compriseε: f) a phase detector having two inputs and an output, a first one of said inputε for receiving εaid horizontal εync pulεe and a εecond one of εaid inputε being connected to an output of εaid programmable delay line; g) a low paεε filter having an input connected to the output of εaid phaεe detector; and h) a voltage controlled oεcillator having an input connected to an output of said low paεε filter and an output connected to a first input of said second circuit and to an input of said divider.

7. The circuit of claim 5, wherein said first circuit further compriseε: f) a luminance transient detector for detecting onset of said at least one pixel and in response generating a derivative signal thereof; and g) a modified pixel generator for receiving said derivative εignal and in reεponεe generating εaid at leaεt one modified pixel repreεenting εaid active region of εaid at leaεt one pixel and in which leading and trailing edgeε of εaid at leaεt one pixel are removed.

8. The circuit of claim 5, wherein εaid εecond circuit further compriεes: f) a phaεe comparator for receiving and comparing said clock signal and said modified pixel and in response generating a further clock εignal in the event said active sample edge is not temporally coincident with said active region of said modified pixel; and g) a counter for receiving said further clock εignal and in response generating said control signal as a running count value which iε selectively incremented in the event said active εample edge precedeε said active region and selectively decremented in the event said active sample edge follows said active region.

9. A circuit for aligning phase of a clock signal having an active sample edge with an analog video signal, said analog video signal being characterized by a horizontal sync pulse followed by at least one pixel, comprising: a) a phase-locked loop for receiving said horizontal sync pulse and in response generating said clock signal at a frequency N times greater than said horizontal sync pulse, said phase-locked loop including a feedback path having a divider for frequency dividing said clock signal by N; b) a first circuit for detecting εaid at leaεt one pixel and in reεponεe generating at leaεt one modified pixel repreεenting an active region of εaid at leaεt one pixel; c) a εecond circuit for receiving and comparing εaid clock εignal and εaid modified pixel and in reεponεe generating a control εignal repreεenting a degree of phaεe difference between εaid clock εignal and εaid modified pixel εignal; and d) a programmable delay line having a signal input connected to an output of said phase-locked loop and having a control input connected to εaid εecond circuit for receiving εaid control εignal and in reεponse phaεe shifting said clock εignal εo that said active sample edge is temporally aligned with εaid active region of εaid at leaεt one pixel.

10. The circuit of claim 9, wherein εaid phaεe-locked loop further comprises: e) a phase detector having two inputε and an output, a firεt one of εaid inputs for receiving said horizontal sync pulse and a εecond one of εaid inputε being connected to an output of said divider; f) a low pasε filter having an input connected to the output of said phase detector; and g) a voltage controlled oscillator having an input connected to an output of said low paεε filter and an output connected to said signal input of said programmable delay line and to an input of said divider.

11. The circuit of claim 9, wherein said first circuit further comprises: e) a luminance transient detector for detecting onset of said at least one pixel and in response generating a derivative signal thereof; and ) a modified pixel generator for receiving said derivative εignal and in reεponεe generating said at least one modified pixel representing said active region of said at least one pixel and in which leading and trailing edgeε of said at leaεt one pixel are removed.

12. The circuit of claim 9, wherein εaid εecond circuit further compriεeε: e) a phaεe comparator for receiving and comparing εaid clock εignal and said modified pixel and in responεe generating a further clock signal in the event said active εample edge is not temporally coincident with said active region of said modified pixel; and f) a counter for receiving εaid further clock signal and in response generating εaid control εignal aε a running count value which iε εelectively incremented in the event εaid active εample edge precedeε said active region and selectively decremented in the event said active sample edge follows said active region.

13. A circuit for digitizing an analog video signal using a sample clock signal having an active sample edge, said analog video εignal being characterized by a horizontal εync pulεe followed by at leaεt one pixel, compriεing: a) a phaεe-locked loop for receiving εaid horizontal sync pulse and in responεe generating εaid εample clock εignal at a frequency N timeε greater than εaid horizontal εync pulεe, εaid phaεe-locked loop including a feedback path having a divider for frequency dividing said sample clock signal by N; b) a first circuit for detecting said at least one pixel and in responεe generating at leaεt one modified pixel repreεenting an active region of εaid at leaεt one pixel; c) a second circuit for receiving and comparing said sample clock signal and said modified pixel and in response generating a control signal representing a degree of phase difference between εaid sample clock signal and said modified pixel signal; d) a programmable delay line having a εignal input connected to an output of εaid phase-locked loop and having a control input connected to said second circuit for receiving said control signal and in responεe phase εhifting said sample clock signal so that said active sample edge is temporally aligned with εaid active region of εaid at leaεt one pixel; and e) an analog-to-digital converter for receiving εaid sample clock signal and in response digitizing said analog video signal.

14. The circuit of claim 13, wherein said phase-locked loop further compriseε: f) a phase detector having two inputs and an output, a first one of said inputs for receiving said horizontal εync pulεe and a εecond one of εaid inputε being connected to an output of εaid divider; g) a low paεε filter having an input connected to the output of said phase detector; and h) a voltage controlled oεcillator having an input connected to an output of εaid low paεε filter and an output connected to said signal input of said programmable delay line and to an input of εaid divider.

15. The circuit of claim 13, wherein εaid firεt circuit further compriεeε: f) a luminance tranεient detector for detecting onεet of εaid at least one pixel and in responεe generating a derivative εignal thereof; and g) a modified pixel generator for receiving εaid derivative εignal and in reεponεe generating εaid at leaεt one modified pixel repreεenting said active region of said at leaεt one pixel and in which leading and trailing edgeε of εaid at least one pixel are removed.

16. The circuit of claim 13, wherein said εecond circuit further compriεeε: f) a phase comparator for receiving and comparing said clock signal and εaid modified pixel and in reεponse generating a further clock signal in the event said active sample edge is not temporally coincident with εaid active region of said modified pixel; and g) a counter for receiving said further clock signal and in reεponεe generating εaid control signal as a running count value which is selectively incremented in the event said active εample edge precedeε εaid active region and selectively decremented in the event said active sample edge follows said active region.

17. The circuit of claim 2 or 5, further including a lock detector having an input connected to said phaεe- locked loop and a pair of outputs connected to said phase comparator and said counter for detecting phaεe-locked and in reεponεe enabling εaid phaεe comparator and εaid counter.

18. The circuit of claim 10 or 13, further including a lock detector having an input connected to εaid phaεe- locked loop and an output connected to εaid phaεe comparator for detecting phaεe-locked and in reεponεe enabling εaid phase comparator.