Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
  • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
  • G09G5/006—Details of the interface to the display terminal
  • G09G5/008—Clock recovery
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/04—Synchronising
  • H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
  • H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator

Definitions

• the present invention relates in general to sampling of video signals, and more particularly to a method and apparatus for generating a phase corrected sampling clock for analog-to-digital conversion and/or sampling of various kinds of video signals used to drive a flat panel LCD display.
• Flat panel LCD displays are, by nature, sampling devices, and the resolution is determined by a fixed matrix of electrodes.
• the image In order to obtain a high quality image from a fixed-matrix display, the image must be perfectly aligned with the original video signal in order to avoid side effects such as noisy images, pixel jitter and so forth.
• the regeneration of an original pixel clock signal is a difficult problem which has been addressed by the prior art, as is the problem of signal synchronization (see Electronic Engineering Times, 19.10.1992, "Integrators Tackle Flat-Panel Displays", page 35, 37) .
• a number of prior art devices are known for sampling and processing of video signals, as described below.
• the most simple known apparatus utilizes an asynchronous and independent clock for sampling a video signal.
• this prior art system is characterized by numerous problems. For example, where the system utilizes a buffer memory, time based fluctuations have been known to occur in the processed video signal due to quantizing errors in the time base resulting from asynchronism between clock pulses. Where the video signal is time-compressed and expanded, the quantizing errors are magnified so that the quality of the picture reproduced from the processed video signal is degraded. Furthermore, since the video signal is a broad band signal, it is necessary to provide a sufficiently high sampling clock frequency to avoid aliasing. However, limitations in the operating speed of the circuit often make generation of such a clock frequency difficult to attain.
• spurious components may be generated. Since these spurious components appear as noise in a reproduced picture, it is necessary to restrict the video signal band sufficiently and rapidly before processing the video signal. This rapid restriction of the band gives rise to a delay distortion and, as a result, to a waveform distortion, so that, for example, ringing (i.e. uncontrolled oscillation) may be generated.
• a number of additional prior art systems of generating a sampling clock signal utilize the concept of a phase-locked loop (PLL) .
• a phase comparator is used for comparing the phase of a horizontal sync signal and the phase of a further signal produced by a frequency divider, for generating an error signal.
• the error signal is smoothed by a low-pass filter whose output is connected to a voltage-controlled oscillator (VCO) which varies its oscillation frequency in response to the filtered error control voltage level.
• VCO voltage-controlled oscillator
• the sampling clock signal is generated at the output of the voltage-controlled oscillator, and is fed back to the programmable frequency divider which de-multiplies the sampling clock frequency at a preset dividing ratio (N) , for producing the aforementioned further signal applied to the phase comparator.
• N preset dividing ratio
• the conventional phase-locked loop described above relies largely for proper generation of a phase corrected sampling clock signal, on the phase drift between a video pixel and the externally-supplied horizontal sync signal. However, this phase drift can vary with time and temperature. Thus, the generated sampling clock signal can properly sample only video signals which have a fixed and stable phase relationship with the horizontal sync signal.
• a reference frequency oscillator provides a first input to the phase comparator of a phase-locked loop which functions as a frequency synthesizer for generating a variable-frequency master clock signal having a frequency which is Nm times the predetermined reference clock frequency.
• the master clock signal is divided by a further programmable frequency demultiplier by a dividing ratio Ns, to produce the sampling clock signal.
• the ratio Ns is set from outside the system and is reset by the horizontal sync signal, which is also provided from outside the system.
• sampling clock pulses are produced by a voltage-controlled oscillator which is instantaneously phase-synchronized with the synchronizing information of the input video signal.
• the oscillating frequency of the oscillator is stabilized by a feedback loop comprising a phase comparator which phase compares the oscillating output signal (or a divided signal proportional thereto) , with a reference signal having a constant frequency (or a divided signal proportional thereto) .
• the oscillating frequency of the voltage-controlled oscillator is controlled in response to the phase error generated by the phase comparator.
• the oscillator is controlled to at least one of start and stop oscillation in accordance with the synchronizing information.
• U.S. Patent 4,996,596 describes a phase synchronizing circuit in which a first phase-locked loop has a plurality of lock ranges, and a second phase-locked loop or automatic frequency control loop has an output characteristic with a single S curve and one wide lock range.
• the second PLL loop is supplied with a horizontal sync signal which has been separated in a synchronization separating circuit via a band pass filter.
• the first PLL loop is directly supplied with the horizontal sync signal extracted via the synchronization separating circuit.
• the first PLL loop shares a voltage controlled oscillator and a frequency divider with the second PLL loop or AFC loop.
• the phase synchronizing circuit further includes a circuit for detecting synchronization/non-synchronization of an output of the frequency divider circuit with the horizontal sync signals separated/extracted and synchronization separating circuit, and a switching circuit for activating one of the first PLL loop and the second PLL or AFC loop in response to an output of the synchronization detector circuit.
• a microprocessor is employed to control a digital genlock.
• An input analog signal such as an NTSC video signal, having a signal element that repeats at a first, nominally fixed frequency (e.g. the first positive-going zero crossing of a burst, repeating at line rate) , is used to generate a signal at a second, higher frequency and having a predetermined phase relationship to the repetitive signal element of the input signal.
• the digital words are then analyzed to identify where, in the succession of digital words, the signal element occurs and to determine the phase angle of the clock cycle at which the signal element occurs.
• This phase information is used to generate the control word of the programmable oscillator and to establish the desired predetermined phase relationship between the clock signal and the signal element of the input signal.
• the digital phase- locked loop that is thus provided avoids the disadvantages of an analog phase-locked loop but requires the use of a repetitive signal such as a positive-going zero burst.
• U.S. Patent 5,166,641 discloses a phase-locked loop which includes a VCO circuit for generating a recovered data signal and a charge pump circuit coupled to the phase detector for generating an error signal in response to the detected phase difference.
• the charge pump circuit includes first and second pump generators for respectively providing first and second sets of pump signals, with the pump generators preferably being interconnected to facilitate generation of the error signal.
• the PLL is designed to alternate between operation in phase correction and phase calibration cycles.
• a calibration network operates to adjust the second charge pump generator such that the first and second sets of pump signals are precisely balanced when the reference and recovered data signals have a predefined phase relationship.
• the predefined phase relationship corresponds to that of the reference and recovered data signals being matched in phase. In this way, inconsistencies in the operating characteristics of the pump generators are precluded from engendering steady-state phase alignment errors between reference and recovery waveforms.
• a charge pump circuit is utilized for charging a capacitor in response to a phase difference between first and second input signals.
• the charge pump circuit comprises a constant current source for providing a first constant current, a constant current sync for absorbing a second constant current, a circuit for substantially equalizing the magnitudes of the first and second constant currents, and a switching circuit for providing the first constant current and the second constant current flowing in opposed directions to the capacitor through an output terminal of the charge pump circuit in respon ⁇ e to the phase difference between the first and second input signals, to produce a voltage level across the capacitor corresponding to the phase difference.
• phase comparator produces a phase difference signal for controlling the provision of the first and second constant currents by the switching circuit capacitor.
• the capacitor acts as loop filter for supplying the voltage thereacross as a control voltage to a voltage controlled oscillator of the phase-locked loop system.
• a system for precise sampling of a video pixel in its active region close to the centre of the pixel, thereby eliminating intensity errors caused by sampling during the rising and/or falling edges of the video pixel.
• the system of the present invention utilizes a phase-locked loop in combination with a digitally controlled delay line, a luminance transient detector, a pixel generator, a phase comparator and counter, for phase correcting the sample clock signal generated by the phase- locked loop to align with the active area of the modified pixel pulse.
• the modified pixel pulse omits the rising and trailing edges of a video pixel, and thereby represent only the active portion of the pixel for sampling.
• Figure 1 is a block diagram of the video signal sampling circuit according to the preferred embodiment
• Figure 2 is a waveform diagram showing various waveforms generated by the circuitry of Figure 1;
• Figure 3 comprisings parts 3A and 3B together, is a schematic diagram of a luminance transient detector and modified pixel generator in the preferred embodiment of Figure 1;
• Figure 4 co prsing parts 4A and 4B together is a schematic diagram showing error signal generating circuitry in the preferred embodiment of Figure 1;
• FIG. 5 is a block diagram of a video signal sampling system according to an alternative embodiment of the invention.
• FIG. 1 is a block diagram depicting a system for digitizing video signals in accordance with a preferred embodiment of the present invention.
• the system comprises a phase-locked loop (PLL) implemented via phase detector 1, low pass filter 3, voltage-controlled oscillator (VCO) 5, frequency divider 7 and digitally controlled delay line 9.
• phase detector 1 detects any phase difference between the horizontal sync signal and a version of the sample clock signal which is output from voltage control oscillator 5, divided by N in divider 7 and delayed by a controllable amount in delay line 9.
• the generated sample clock is N times the frequency of the horizontal sync pulse.
• Low pass filter 3 smooths (i.e.
• phase detector 1 filters out high frequency components from) the error signal output by phase detector 1, and the DC error signal is applied as a control voltage to VCO 5 which, as indicated above, generates the sample clock.
• VCO 5 which, as indicated above, generates the sample clock.
• the generated sample clock signal is applied to an A/D converter 11 for digitizing an input analog video signal, in a well known manner.
• the input analog video signal (i.e. RGB waveform A in Figure 2) , is applied to a luminance transient detector 13.
• Detector 13 detects signal transients which exceed predefined levels on a pixel-by-pixel basis, and in response generates an output signal (i.e. waveform B in Figure 2) indicative of the detected signal transients (i.e. dV/dt) .
• the detector 13 may be implemented as a simple differentiator followed by an amplifier and comparator, or other type of programmable edge detector.
• Modified pixel generator 15 receives the signal output from detector 13 and in response generates a "modified” pixel in the event that the signal output from luminance transient detector 13 (i.e. waveform B) exceeds a predetermined level. By triggering only on transients which exceed predefined levels, the modified pixel generator 15 avoids being triggered due to noise signals. Modified pixel generator 15 is thus triggered by each detected video pixel "start” and in response generates a pulse representing a single "modified” video pixel.
• the "modification" to each detected pixel comprises wave shaping to eliminate the leading and trailing edges of the video pixel (e.g. the leading edge shown in phantom with reference to waveform A in Figure 2) . Accordingly, the resultant modified pixel represents only the active portion of the pixel for sampling purposes.
• the modified pixel pulse output from pixel generator 15 is represented by waveform C in Figure 2.
• a phase comparator 17 is provided for comparing the modified pixel pulse (waveform C) with the sample clock signal generated by VCO 5 (i.e. referred to herein as the initial sample clock signal with phase error, as represented by waveform Dl in Figure 2) .
• Phase comparator 17 generates an error pulse each time the sampling clock signal active edge is positioned outside the active region of the video pixel, as defined by the modified pixel pulse.
• phase comparator 17 generates an error pulse as a result of the positive-going edge (i) of waveform Dl (initial sampling clock signal), as shown in Figure 2.
• a preferred embodiment of phase comparator 17 is discussed greater detail below with reference to Figure 4.
• phase comparator 17 can be enabled once per video line, in the middle of a line, every few lines, once per frame, every few frames, etc., depending on system requirements, noise and stability.
• the selective enabling of phase comparator 17 is effected by lock detector 19.
• Lock detector 19 receives a pulse signal from phase detector 1 which is proportional to the PLL error, and in response determines the "lock", "no-lock” condition of the phase locked loop.
• the signal output from lock detector 19 to phase comparator 17 enables the phase comparator 17 only when the PLL is in lock.
• the error pulse output from phase comparator 17 serves as a clock signal for an up/down counter 21.
• Counter 21 has a decoded output which is applied to a control input of delay line 9 for delaying the divided sample clock signal by a predetermined amount proportional to the phase error detected by comparator 17, thereby effectively correcting the phase of the sampling clock so that the active edge is approximately centred in the active region of the detected pixel pulse (i.e. active edge (ii) of waveform D2 in Figure 2).
• Figure 3 represents blocks 13 and 15 of Figure 1.
• the capacitor C107 and resistors R91 and R92 represent the dv/dt circuit 13 of Figure 1.
• Amplifier U31 is a high gain amplifier and amplifier U32 is a comparator for slicing the differentiated signal pulse edges thereby producing a desired length of modified pixel output.
• a tapped delay line U101 provides different phases of the modified pixel where required for particular applications.
• Figure 4 shows an embodiment of phase comparator 17 in which the modified pixel is clocked in with an inverted sample clock.
• the phase comparator 17 generates error pulses whenever the rising edge of the inverted sample clock is inside the modified pixel period. This ensures a sampling clock phase as per Figure 2.
• the LOCKDET and CBL- composite blanking inputs receive control signals for enabling the phase comparator 17 only during valid video signal times.
• the high frequency digitally programmable delay line 9 is shown connected between the output of VCO 5 and one of the inputs of the phase comparator 17.
• operation of the circuit is similar as described in connection with Figure 1, except that the phase comparator 17 and counter 21 generate an error signal for controlling the delay line 9 on a pixel-by-pixel basis, rather than on a line- by-line basis as in Figure 1.
• Other alternative embodiments are possible without departing from the sphere and scope of the invention as defined by the claims appended hereto.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Synchronizing For Television (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

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• 1995
  • 1995-07-28 WO PCT/CA1995/000449 patent/WO1997005740A1/en not_active Ceased
  • 1995-07-28 EP EP95926345A patent/EP0842579A1/de not_active Ceased

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