JP3326627B2 - Dot clock phase adjusting device, method thereof, and liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dot clock required for displaying an image of a computer or the like on an LCD monitor.

[0002]

2. Description of the Related Art When an LCD monitor is connected to a computer or the like, the output terminals of the computer or the like are analog black and white signals or R, G, and B color signals, and horizontal and vertical synchronization signals. Black and white signal or R,
The G and B color signals must be sampled and A / D converted. For this purpose, a dot clock serving as a sampling timing signal must be generated using the synchronization signal.

That is, as shown in FIG. 3, a dot clock having a cycle of one pixel is generated from a synchronization signal obtained from an output terminal of a computer or the like by using a dot clock generation circuit 31. Is input to an A / D converter 32 of R, G, B color signals obtained from an output terminal of a computer or the like. Since the R, G, and B color signals are signals determined for each pixel, sampling is performed in accordance with the cycle of the dot clock.

As a result, the number of samplings per time becomes equal to the frequency of the dot clock, so that the number of samplings per time is reduced and the operating speed of the electronic parts can be reduced, thereby reducing the cost of the electronic parts. And power consumption can be reduced.

However, the dot clock has different frequencies and phases when the model of the computer or the like is different, and there is an individual difference even within the same model. Also, a computer or the like may output a horizontal synchronizing signal and a color signal such as R, G, B, etc., out of phase due to an AC power supply voltage or an environmental temperature. The phase of the dot clock generated from the generation circuit 31 becomes inappropriate.

If the phase of the dot clock sent to the A / D converter 32 is not appropriate, horizontal image fluctuation (at one dot level) occurs on the LCD screen, so the phase must be adjusted. .

Conventionally, the phase adjustment of the dot clock is performed by
The user moves the adjustment button or the like to a position where image shaking does not occur while watching the LCD screen by himself.

[0008]

Therefore, in the case where a plurality of computers or the like are switched and connected to the LCD monitor for use, the user himself or herself moves the adjustment button or the like to switch the phase of the dot clock for each switching. Adjustments had to be made and it was complicated.

Further, even when one computer or the like is connected to the LCD monitor and used, the phase of the dot clock changes depending on the AC power supply voltage, the environmental temperature, and the like. Move it,
The phase of the dot clock had to be readjusted, which was extremely complicated for the user.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a dot clock phase adjusting device, a method thereof, and a liquid crystal display device in which the user does not need to adjust the phase of the dot clock.

[0011]

To achieve the above object, according to the Invention The dot clock phase adjusting device of the present invention is less
A differentiating circuit for differentiating one color signal with a comparison between a voltage and a reference voltage outputted by the differentiating circuit, a comparator circuit for detecting an error <br/> Tsu di color signal samples the color signals
Dot clock generation cycle to generate the dot clock for
And a plurality of different delay time output terminals.
Output by the dot clock delay circuit and comparison circuit
Of the edge clock and the dot clock output by the delay circuit
Counting times when the peak or valley counts at the same time
The output of the delay circuit depends on the
A selection switch for changing the selection of force .

[0012] To achieve the above object, the dot clock phase adjustment method of the present invention, by differentiating the color signals, by comparing the voltage with a reference voltage that is the derivative, detects the edge of the color signal And the detected edge and dot
Count the time when the peak or valley of the
Change the dot clock delay time according to the count number
I do .

[0013]

The phase shift means includes a dot clock delay circuit having a plurality of different delay time output terminals,
It is preferable to comprise a count circuit that counts when the edge and the valley of the dot clock are at the same time, and a selection switch that changes the selection of the output terminal of the delay circuit according to the count number of the count circuit.

In the liquid crystal display device, the dot clock phase adjusting device and the liquid crystal panel may be inseparable.

[0016]

The rising edge and the falling edge of the black and white signal or the color signal become sharp voltages by passing through the differentiating circuit. The sharp voltage is detected by comparing with the reference voltage. Edges are detected. By comparing the edge with the phase of the dot clock by the phase shifting means and correctly adjusting the phase of the dot clock, the phase of the dot clock is automatically adjusted.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

In this embodiment, a color image is displayed on an LCD monitor using R, G, and B color signals output from a computer or the like. Further, in this embodiment, A
Assume that the / D conversion is performed in the section of the peak (H) of the dot clock.

In FIG. 1, an A / D converter 1 to which a dot clock phase adjusting device of the present invention is applied exists as a single product, and is provided between a computer or the like (not shown) and a liquid crystal display device 2. Connected.

Analog R, G, and B signals are input to the A / D converter 1 from analog R, G, and B color signal output terminals of a computer or the like. Each of these signals is input to the A / D converter 3 and converted into an 8-bit digital signal, and its output terminal is connected to the liquid crystal display device 2.

Next, a synchronizing signal is input to the A / D converter 1 from a synchronizing signal output terminal of a computer or the like, and this signal is transmitted as it is to the output terminal and connected to the liquid crystal display device 2. At the same time, part of the synchronization signal is input to the dot clock generation circuit 5.

The dot clock generated by the dot clock generation circuit 5 is input to the delayed buffer 6. The variable range of the delayed buffer 6 needs to be longer than the period of the dot clock. For example,
When the dot clock is 30 MHz, the period of the dot clock is 1 / (30M) [s] = 33.4 [ns], so that the variable range of the delayed buffer 6 is 33.4.
[Ns] or more is required. When connecting to a plurality of computers, etc., the delayed buffer 6
The variable range, Ru requires der that is the period over largest computer cycle of the dot clock. next,
In this embodiment, the delayed buffer 6 has five output terminals whose delay time increases or decreases at a phase interval width obtained by dividing the variable range into five. The delayed buffer 6 is connected to a selection switch 7 which will be described later. One of the five output terminals of the delayed buffer 6 is selected by the selection switch 7, and the output of each of the above-mentioned A / A It is input to the D converter 3.
The output selected by the selection switch 7 is simultaneously transmitted to the output terminal and connected to the liquid crystal display device 2.

Next, the analog R signal, G signal and B signal input to the A / D converter 1 are input to the differentiator 8, respectively. As a result, sharp voltages are obtained at the rising edge and the falling edge of each signal.

Next, each differentiator 8 includes a comparator 10
, A portion larger or smaller than the reference voltage 11 is found, and an edge portion is detected.

The output from each of the comparators 10 is input to an OR circuit 12 to perform a logical sum operation.

The output of the OR circuit 12 is input to the AND circuit 13 together with the dot clock from the output terminal of the one delayed buffer 6 selected by the selection switch 7. In the AND circuit 13, when the section of the peak H of the dot clock and the detected edge are at the same time,
Output is performed.

Next, the output from the AND circuit 13 is input to the counter 15. The counter 15 sets the upper limit of the count number to the output number of the selection switch 7, which will be described later,
It is preset according to the number of outputs of the buffer 6.
That is, the upper limit of the number of counts of the counter 15 is 4 , and after counting up to 4 , the process returns to the initial count of 0 . The counter 15 inputs the count number to the later-described selection switch 7 as 3-bit parallel data.

The selection switch 7 is an eight-to-one type switch and has eight selection branches. However, since the number of output terminals of the delayed buffer 6 is five, eight
Only 5 of the options are used. Each time the count number sent by the counter 15 increases by one, the output terminal of the delayed buffer 6 with a different delay time
The delay time is sequentially selected in a direction of increasing the delay time or in a direction of decreasing the delay time.

Next, the operation of the present invention will be described with reference to FIGS.

The A / D conversion device 1 is connected between a computer or the like to be used and the liquid crystal display device 2. When there are a plurality of computers or the like to be used, the changeover switch is used to switch the plurality of computers or the like to the A / D conversion device 1.
Connect to

When the liquid crystal display device 2 is operated, the analog R signal, G signal, and B signal (see FIG. 2, the same applies hereinafter) are respectively input to the differentiator 8, and the edge portion becomes a sharp voltage. The edge timing is detected by the detector 10 in comparison with the reference voltage. The signal of the edge portion is input to the OR circuit 12 to perform an OR operation, and this signal and the dot clock signal selected by the selection switch 7 are input to the AND circuit 13 to perform an AND operation. Thereby, R, G, B during the A / D conversion period
Is determined whether there is no change in the input signal. If there is a change, this signal is input to the counter 15.

That is, when the phase of the dot clock is not correct, the signal of the edge portion and the peak portion H of the dot clock signal are in the same period as shown in FIG. , And the number of the signals is counted by the counter 15.

Then, the counter 15 converts the count number at that time into a binary number and outputs it to the selection switch 7 as 3-bit parallel data. Then, the counter 15
Each time the count number increases by one, the count number indicated by the 3-bit parallel data increases by one. Therefore, in response to this control signal, the selection switch 7 sets the delay time to the next largest or the next smallest. , Delayed
The output terminal of the buffer 6 is selected.

The operation in which the counter 15 counts and the selection switch 7 selects the next output terminal of the delayed buffer 6 is performed during the A / D conversion period (the period when the dot clock is at the peak H). , B while the input signal changes.

Then, as shown in FIG.
When there is no change in the input signals of R, G, and B during the period of / D conversion, the signal input from the AND circuit 13 to the counter 15 becomes low as shown in the same manner, so that the changeover switch 7 does not switch the switch. Thereafter, the phase of the dot clock is determined.

As described above, the phase of the dot clock is automatically determined.

Even when switching to another computer or the like, the phase of the dot clock is automatically adjusted as described above. Etc. also change,
The dot clock phase adjusting device of the present invention immediately and automatically adjusts the phase of the dot clock.

Thus, the analog R, G, and B color signals are correctly converted to digital signals by the A / D converter based on the dot clock of the correct phase, and are input to the liquid crystal display device 2. Therefore, the liquid crystal display device 2 displays a correct color screen without horizontal image fluctuation based on these digital signals and the horizontal and vertical synchronization signals and dot clock signals input from other terminals. Therefore, the user can always obtain a color liquid crystal display screen free from image shaking, even if the user does not make any adjustments.

In the above embodiment, the reference voltage 11 of the comparator 10 is made sufficiently close to the sharp voltage value obtained by the differentiator 8 or the counter 15 is set to 2
By providing a stage configuration, or by inserting a one-shot multivibrator in front of the counter 15, the number of signals input to the counter 7 may be reduced, and the switching time of the switch 7 may be increased. Accordingly, it is possible to sufficiently cope with a case where the response speed of the phase change of the dot clock of the delayed buffer 6 is low.

In the above embodiment, a color image is displayed on an LCD monitor using R, G, B color signals output from a computer or the like.
Naturally, the present invention can also be applied to the case of displaying on a monochrome LCD monitor using a monochrome signal output from a computer or the like by connecting the differentiator 8 and the comparator 10 to the monochrome signal.

Further, in this embodiment, the A / D conversion is performed during the period of the peak (H) of the dot clock.
Since the conversion period varies depending on the type of IC and the circuit configuration, the correspondence between the A / D conversion period and the dot clock waveform is determined according to the actual circuit. And in this case,
Another logic circuit is configured in place of the AND circuit 13 of the above embodiment. For example, when the A / D conversion is performed in the period of the valley (L) of the dot clock, the dot clock output is input to the AND circuit 13 after being inverted.

Further, in the above embodiment, the A / D converter 1 to which the dot clock phase adjusting device of the present invention is applied exists as a single product, and includes a computer (not shown) and a liquid crystal display 2. Was connected between
The A / D conversion device 1 is incorporated in the liquid crystal display device 2,
The A / D converter 1 and the liquid crystal panel may be inseparably configured, that is, the A / D converter 1 and the liquid crystal panel may be arranged in one housing. Thus, since it is only necessary to connect the liquid crystal display device to a computer or the like, connection becomes easy.

Although the above embodiment is applied to the digital liquid crystal display device 2, the present invention is applied to an analog liquid crystal display device in which, for example, a sample hold circuit is integrally formed on a liquid crystal panel substrate. Is also applicable.

[0044]

Since the present invention is configured as described above, the phase adjustment of the dot clock is attenuated, and even when a plurality of computers or the like are switched and used by connecting to an LCD monitor, the user is required to switch every time. However, there is no need to adjust the phase of the dot clock.

Also, while one computer or the like is connected to the LCD monitor and used, even if the phase of the dot clock changes due to AC power supply voltage, environmental temperature, etc., the phase of the dot clock can be readjusted. It becomes completely unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIGS. 2A and 2B are timing charts showing signal states at respective positions in the block diagram of FIG. 1. FIG. 2A shows a state where the phase of the dot clock is correct, and FIG. 2B shows an incorrect phase of the dot clock. Indicates the state.

FIG. 3 is a block diagram of a conventional A / D converter.

[Explanation of symbols]

 2 liquid crystal display device 6 delay circuit 7 selection switch 8 differentiating circuit 10 comparing circuit 15 counting circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/00-5/42 H04N 5/66-5/74

Claims (3)

(57) [Claims] A differentiation circuit for differentiating at least one color signal; and a comparison circuit for comparing a voltage output by the differentiation circuit with a reference voltage to detect an edge of the color signal. The dot clock for sampling the above color signal
And a plurality of dot clock generating circuits and a plurality of different delay time output terminals.
A delay circuit for the clock signal, the edge output by the comparison circuit and the delay circuit.
The peak or valley of the dot clock output from
And a delay circuit for counting the time of the
A dot switch for changing the selection of the output . Wherein differentiating the color signals, compares the voltage with a reference voltage that is the differentiation to detect the edge of the color signal,
Above detected edge and peak or valley of dot clock
Department counts at the same time, and increases according to the above count.
A dot clock phase adjusting method characterized by changing a delay time of the dot clock. 3. A method for differentiating at least one color signal.
Comparing the partial circuit, the voltage and the reference voltage output by the differentiating circuit
And a comparison circuit for detecting an edge of the color signal, and a dot clock for sampling the color signal.
And a plurality of dot clock generating circuits and a plurality of different delay time output terminals.
A delay circuit for the clock signal, the edge output by the comparison circuit and the delay circuit.
The peak or valley of the dot clock output from
And a delay circuit for counting the time of the
A liquid crystal display device comprising: a dot clock phase adjusting device having a selection switch for changing an output selection; and a liquid crystal panel.