JPH048082A - Hard copy equipment - Google Patents

Abstract

PURPOSE:To always obtain an excellent hard copy by selecting a horizontal clock number outputted from a horizontal clock number output means to he small at first and increasing the horizontal clock number gradually till a detection circuit detects the coincidence between a frequency of a sampling clock and a frequency of a video signal. CONSTITUTION:A phase of a horizontal synchronizing signal is delayed by a phase adjustment circuit by 1/4 period of a sampling clock to obtain a clock CK'. When a CPU applies preset, a C-FF5 latches the clock CK' by a leading edge of a video signal. As a result, when the frequency of the sampling clock CK and the frequency of the video signal are coincident, an H level is always kept to an output Q2. On the other hand, in the case of coincidence, a level of the Q2 is at L in a timing S in figure and the L level is kept by the action of an AND gate 4. The CPU monitors the Q2 signal and when the level is L, the horizontal clock number given to a PLL is sequentially increased and the horizontal clock number having been given to the PLL at an H level is discriminated to be the horizontal clock number to be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a hard copy device for printing images displayed on a CRT via a video signal connection.

[Prior art]

To capture a video signal in a hard copy device, etc., a sampling clock having the same frequency as the video frequency is generated using a phase-locked loop (PLL) based on the edge of the horizontal synchronizing signal, and the sampling clock is synchronized with this. known to do. Figure 2 (i) shows an example of a CRT displaying a checkered pattern and a hard copy.
Figure 2 (ii) is a CRT displaying a grid pattern; Figure 2 (ii) is (i).
If the sampling clock and video frequency match in the hard copy of the CRT display shown in (1ii)
are the same (each case of mismatch is shown).

(iii) As can be seen from the figure, when the sampling clock and video frequency do not match, the horizontal direction is compressed from k to 1 by the error in the number of horizontal clocks, and the vertical line becomes double, or m An import error as shown has occurred. By the way, in order to generate a signal with the same frequency as the video frequency, it is necessary to give the number of horizontal clocks in the horizontal period, but the number of horizontal clocks is usually not disclosed to the public and is difficult for users to obtain. This is great information.

On the other hand, when trying to capture a video signal with a hard copy device, etc., it is conceivable that the hard copy device searches for an unknown number of horizontal clocks for the purpose of capturing the video signal. The method can be implemented using a counter or the like, with the premise that the horizontal display resolution is known and the first display line of the CRT is displayed in accordance with the resolution.

[Problem to be solved by the invention]

As described above, in order to determine the number of horizontal clocks, it is necessary to display a CRT that matches the horizontal resolution, but it is generally difficult to perform such a display and is not practical.

Further, depending on the personal computer, the number of horizontal clocks may differ depending on the software, and in such a case, it has been impossible to match the number of horizontal clocks.

Therefore, it is an object of the present invention to minimize the limitations of CRT image representation and to enable exploration of the number of horizontal clocks.

[Means to solve problems]

In order to solve the above problems, the present invention provides a hard copy device that prints out images on a CRT by inputting a video signal, and includes a phase adjustment circuit that adjusts the phase of a horizontal synchronization signal and outputs the number of horizontal clocks. a PLL circuit that uses the horizontal clock number as input to form a phase-locked loop and generates a sampling clock based on the edge of the phase-adjusted horizontal synchronization signal; and whether the frequencies of the sampling clock and video signal match. The present invention is characterized in that it has a horizontal clock number detecting circuit which includes a detection circuit for detecting whether or not the clocks match, and means for changing the clock number of the horizontal clock number output means in the case of a mismatch.

[Effect]

According to the above configuration, the horizontal clock number outputted from the horizontal clock number output means is initially set to a small value, and the horizontal clock number is changed to a small value until the detection circuit detects a match between the frequencies of the sampling clock and the video signal. By gradually increasing the number of horizontal clocks, it is possible to search for a horizontal clock number that matches the video frequency.

〔Example〕

Preferred embodiments of the invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a horizontal clock number detection circuit, which is a main part of a hard copy device according to the present invention. The other parts constituting the hard copy device are of known construction and will not be described here. The horizontal synchronization signal is sent to the phase adjustment circuit 1.
The signal is input to the PLL circuit 2 through the . A horizontal clock number is set in the PLL circuit 2 by the CPU in the device, and a sampling clock CK having a frequency equal to or in a predetermined relationship with the horizontal clock number is generated based on the edge of the phase-adjusted horizontal synchronization signal. . The video signal is input manually to the D input of the lunch 3 to which the sampling clock GK is input as a clock, and is latched in synchronization with the sampling clock CK. The sampling clock CK also serves as one input of an AND circuit 4, and the output of the AND circuit 4 is used as the D input of a D-FF 5 to which the video signal is input as a clock. 49 The Q output of the D latch 5 is the other input of the AND circuit, and the output of the AND circuit is latched in synchronization with the video signal. A signal from the CPU is input to the preset input of the FF. Frequency coincidence detection is performed by this AND circuit 4 and the D-FF.

FIG. 3 is a timing chart of each part of the horizontal clock number detection circuit shown in FIG. Figure 3(i) is
(11) shows a case where the frequencies of the video signal and the sampling clock match, and a case where they do not match. In the figure, Q1 and Q2 are latch 3 and D- in Figure 1.
Each Q output of FF5 is shown. As can be seen from the figure, when the frequencies of the video signal and the sampling clock match, the rising edge of the video signal always leads the rising edge of the sampling clock CK by half a period (γ in the figure). Therefore, Q1 The waveform of is correctly 1
It consists of dots. In this way, when the video signal rises or falls at the 7th stage, the phase with the sampling clock CK is always constant, and this state is CR
If the frequency is constant during the display period of T, it can be determined that the frequency matches. On the other hand, in the case of mismatch, the phase of T is not ensured and a portion corresponding to two dots occurs in the waveform of Ql. Here, by delaying the phase of the horizontal synchronizing signal using a phase adjustment circuit, the sampling clock is delayed by A period to CK', and when a preset is applied from the CPU, D-FF5 is activated by the rising edge of the video signal.
Q2 is always rH if the sampling clock CK and video frequency match.
J is retained. On the other hand, in the case of mismatch, Q2 becomes "L" at timing S in the figure, and thereafter r L J is held by the action of AND gate 4. Summary,
If the number of horizontal clocks with a low frequency is set and the 02 signal is monitored, the rLJ state is always maintained. CPU is this Q
2 signals are monitored, and in the case of rLJ, the number of horizontal clocks given to PLL is increased one by one, and when rHJ is reached, the number of horizontal clocks given to PLL I- is the number of horizontal clocks to be found. I judge that there is.

In this embodiment, the CRT display has been described as a grid pattern, but the same effect can be obtained with any display except extremely partial display.

〔Effect of the invention〕

As mentioned above, it is possible to search for the horizontal clock number without imposing any restrictions on the CRT image display, and to obtain a high-quality hard copy.
Even if the horizontal clock number on the T side changes, it can be followed on the hard copy side.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a horizontal Cronk number search circuit which is the main part of the present invention. FIG. 2 is an explanatory diagram for explaining the relationship between CRT display and hard copy. FIG. 3 is a timing chart of each part. 1゜Phase adjustment circuit 2, PLL circuit 3, latch circuit 4, AND gate 5, flip-flop CPU Essentials of the present invention alSb+17゛aatufu 2 First applicant Seiko Electronics Co., Ltd. Agent Patent attorney Keisuke Hayashi CRT Heho and Bartco's 9e4 Figure 2 Figure 451's timing 'rr-to' Figure 3

Claims (1)

[Claims] A hard copy device that prints out an image on a CRT by inputting a video signal includes a phase adjustment circuit that adjusts the phase of a horizontal synchronizing signal, a means for outputting the number of horizontal clocks, and a phase lock circuit using the number of horizontal clocks as input. A PLL that forms a loop and generates a sampling clock based on the edge of the phase-adjusted horizontal synchronization signal.
A detection circuit for detecting whether the frequencies of the sampling clock and the video signal match, and means for changing the number of clocks of the horizontal clock number output means if they do not match. A hard copy device characterized by: