JP2000276092A - Dot clock reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically adjust a dot clock frequency of high precision by using the maximum value and the minimum value of the result of accumulating the absolute values of a difference between the sample values of an input signal. SOLUTION: A clear pulse is inputted in an accumulation circuit 24 to be cleared after a latch circuit 25 is latched and as the result, the accumulation result of each one vertical frequency is inputted to a maximum value detecting circuit 26, a minimum value detecting circuit 27 and a control circuit 28. The circuit 26 receives the output of the circuit 25 to detect the maximum value until then to store. The circuit 27 receives the output of the circuit 25 to detect the minimum value until then to store. The circuit 28 controls the phase of a dot clock by outputting a phase control signal to a PLL circuit 14 and controls the frequency of the dot clock by receiving the outputs of the circuit 26 and the circuit 27 and outputting a frequency control signal to the circuit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer (for example, IBM) which does not output a dot clock of a video signal.
Matrix display device such as a liquid crystal connected to a PC, etc.)
The present invention relates to a scan conversion device.

[0002]

2. Description of the Related Art A video signal from a personal computer or an EWS changes its signal level at a constant period (hereinafter, dot period) shorter than a horizontal synchronizing signal. In order to perform signal processing by writing data to a clock, a clock that matches the dot cycle (hereinafter, dot clock) is required.

However, since there are few personal computers that output the dot clock, the image display device reproduces the dot clock by multiplying the horizontal synchronizing signal by assembling a PLL circuit.

However, since the horizontal blanking period of the dot clock frequency generated by the video signal source (computer) is unknown, it is difficult to reproduce a completely coincident frequency. Therefore, in many displays made using a conventional dot clock reproducing device, the user manually reproduces the dot clock frequency by adjusting the frequency division ratio of the PLL circuit while watching the video signal. It goes without saying that this adjustment is very difficult for the user.

Japanese Patent Laid-Open Publication No. Hei 10-91127 proposes that the adjustment is automated and the user is released from the adjustment. FIG. 7 shows a configuration of a conventional dot clock reproducing apparatus. A screen size detection circuit 16 compares a video signal with a no-signal level and detects a horizontal start position and an end position of an effective video signal. The microcomputer 15 calculates the measured resolution of the screen based on the value, and
The horizontal resolution of the signal source estimated from the horizontal synchronization signal and the vertical synchronization signal is compared, and the dot clock is adjusted so that they match.

[0006]

However, in the above configuration, the screen size detection circuit 16 generates an error of one dot in the detection of the start position and the end position in principle, and as a result, the number of effective screen dots is an error of two dots. Contains. The reason is that it is not known whether the dot indicating the start position is determined as the right or left dot depending on the phase state of the dot clock. Moreover, when there is no dot clock frequency, the phase states of the start position and the end position are completely different. In addition, depending on the image, there is not always a dot having a luminance satisfying a predetermined condition at the start position and the end position, and the waveform is dull with a cable, or a beard due to overshoot or the like is in an area other than the valid period. There is no denying that it may have happened.

In order to eliminate the effect of the two-dot error of the detected value, it is necessary to apply a certain period of the dot clock to be reproduced. For example, it is known that the total number of dots in one horizontal period of a signal output by a computer is almost a multiple of four. There is known a method in which this is applied and rounded so that the total number of dots in one horizontal period of a reproduced dot clock is a multiple of four.

However, one horizontal period of signals output from all computers is not always a multiple of four.
Not applicable to some computers and video cards. Naturally, in the above case, automatic clock adjustment cannot be performed.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a dot clock reproducing apparatus capable of automatically adjusting a dot clock frequency with high accuracy without depending on an image pattern or a waveform of an input signal and without using a computer or a video card. The purpose is to provide.

[0010]

In order to solve the above-mentioned problems, a dot clock reproducing apparatus according to the present invention samples an input signal using a dot clock to be reproduced, and calculates a difference between sample values between adjacent samples. Accumulate the absolute value,
From the plurality of accumulation results obtained each time the phase of the dot clock is shifted, using the ratio between the maximum value and the minimum value,
The frequency of the dot clock is automatically adjusted.

This makes it possible to automatically obtain the dot clock reproduction of the video signal source.

[0012]

According to the first aspect of the present invention, an input signal is sampled at a dot clock to be reproduced, and an absolute value of a difference between sample values between adjacent samples is accumulated. A dot clock reproducing device that automatically adjusts the frequency of the dot clock by using a ratio of a maximum value and a minimum value based on a plurality of accumulation results obtained each time the phase of the dot clock is shifted. Automatic adjustment is performed so that the ratio between the maximum value and the minimum value satisfies a predetermined condition by using the fact that the difference in sample value between adjacent samples is not easily increased or decreased even if the phase is shifted when the frequencies do not match. It has the action of:

According to a second aspect of the present invention, there is provided a dot clock reproducing apparatus capable of controlling phase and frequency, comprising: an A / D converter for converting an input signal into a digital signal by using the dot clock as a sampling clock; A latch circuit for delaying the digital signal after the A / D conversion by one sample period, a difference circuit for outputting a difference between an output of the latch circuit and an output of the A / D converter, and an absolute value of an output of the difference circuit An absolute value circuit that outputs the following, an accumulation circuit that sequentially accumulates the output of the absolute value circuit, a maximum value storage circuit that detects and stores the maximum value of the accumulation result output from the accumulation circuit, A minimum value storage circuit that detects and stores the minimum value of the accumulation result output from the accumulation circuit, an amplitude detection circuit that determines and stores a ratio of storage contents of the maximum value storage circuit and the minimum value storage circuit, A And a control circuit for controlling the frequency of the sampling clock of the / D converter using the content output from the amplitude detection circuit.When the dot clock frequencies do not match, the phase of the dot clock is shifted. This also has an effect of automatically adjusting the ratio between the maximum value and the minimum value to satisfy a predetermined condition by using the fact that the difference between sample values between adjacent samples is hard to increase or decrease.

According to a third aspect of the present invention, an input signal is sampled at a dot clock to be reproduced, an absolute value of a difference between sample values between adjacent samples is accumulated, and the dot clock of the dot clock is accumulated. A dot clock reproducing device that automatically adjusts the frequency of the dot clock using a standard deviation based on a plurality of accumulation results obtained each time the phase is shifted. Has the effect of automatically adjusting the standard deviation so as to satisfy a predetermined condition by using the fact that the difference between sample values between adjacent samples is hardly increased or decreased even if the position is shifted.

According to a fourth aspect of the present invention, in the dot clock reproducing apparatus capable of controlling the phase and the frequency, an A / D converter for converting an input signal into a digital signal by using the dot clock as a sampling clock is provided. A latch circuit for delaying the digital signal after the A / D conversion by one sample period, a difference circuit for outputting a difference between an output of the latch circuit and an output of the A / D converter, and an absolute value of an output of the difference circuit An absolute value circuit for sequentially outputting the output of the absolute value circuit; a standard deviation detection circuit for obtaining and storing a variance of a result output from the accumulator circuit; A control circuit for controlling the frequency of the sampling clock of the converter using the content output from the standard deviation detection circuit. Even if the phase is shifted when the clock frequencies do not match, the effect that the standard deviation satisfies a predetermined condition by using the fact that the difference in sample value between adjacent samples is not easily increased or decreased is used. Have.

According to a fifth aspect of the present invention, an input signal is sampled at a dot clock to be reproduced, an absolute value of a difference between sample values between adjacent samples is accumulated, and the dot clock of the dot clock is accumulated. A dot clock reproducing device that automatically adjusts the frequency of the dot clock by using variance based on a plurality of accumulation results obtained each time the phase is shifted, and shifts the phase when the dot clock frequencies do not match. Even if the difference between sample values between adjacent samples is not easily increased or decreased, an automatic adjustment is performed so that the variance satisfies a predetermined condition.

According to a sixth aspect of the present invention, there is provided a dot clock reproducing apparatus capable of controlling phase and frequency, comprising: an A / D converter for converting an input signal into a digital signal using the dot clock as a sampling clock; A latch circuit for delaying the digital signal after the A / D conversion by one sample period, a difference circuit for outputting a difference between an output of the latch circuit and an output of the A / D converter, and an absolute value of an output of the difference circuit An absolute value circuit that outputs the absolute value circuit, an accumulation circuit that sequentially accumulates the output of the absolute value circuit, a dispersion detection circuit that determines and stores the variance of the result output from the accumulation circuit, and the A / D conversion. And a control circuit for controlling the frequency of the sampling clock of the device using the content output from the standard deviation detection circuit. It has an effect of the dispersion difference between the sample values between the sample adjacent even by shifting the phase by using the hard decreasing performs automatic adjustment to meet the predetermined condition when the frequency does not match.

According to a seventh aspect of the present invention, there is provided a dot clock reproducing apparatus according to the fifth aspect, wherein the absolute value is simply used instead of the square for calculating the variance. The feature is that the load on the variance is reduced. It has the effect that adjustment can be performed.

In the dot clock reproducing apparatus according to the eighth aspect of the present invention, in the dot clock reproducing apparatus according to the sixth aspect, the variance detecting circuit performs two calculations for calculating the variance.
It is characterized by simplifying the circuit scale by simply using the absolute value instead of using the power.Instead of performing the square calculation used when calculating the variance, the absolute value is simply calculated. By using such a circuit, an automatic adjustment can be performed with a cheaper circuit without lowering the accuracy.

According to a ninth aspect of the present invention, there is provided a dot clock reproducing apparatus according to the first, third, fifth, and seventh aspects, wherein a plurality of accumulated clocks are obtained each time the phase of the dot clock is shifted. Is characterized by performing a smoothing process on the result, and has an effect that highly accurate automatic adjustment can be performed so that the influence of detection error due to noise or the like does not affect the result of automatic adjustment.

A dot clock reproducing apparatus according to a tenth aspect of the present invention is the dot clock reproducing apparatus according to the second, fourth, sixth and eighth aspects, wherein a smoothing process is performed on the output result of the accumulation result. And has an effect that highly accurate automatic adjustment can be performed without the influence of detection errors due to noise or the like affecting the result of automatic adjustment.

(Embodiment 1) Claim 1 of the present invention will be described below.
An embodiment of the invention described in claim 2 will be described with reference to FIGS. FIG. 2 is a block diagram of Embodiment 1 of the present invention. In FIG. 1, reference numeral 14 denotes
When the input signal is, for example, a video signal output from a computer, the circuit is a PLL circuit that reproduces a dot clock synchronized with the synchronization signal and that can control the phase and frequency of the dot clock. An A / D converter 11 samples the video signal using the dot clock as a sampling clock and converts the video signal into a digital signal. twenty one
Is a latch circuit for delaying the digital signal output from the A / D converter 11 by one cycle of the sampling clock, and 22 is a latch circuit for determining a difference between sample values between adjacent samples. A difference circuit 23 receives the two signals and outputs the difference, 23 is an absolute value circuit that outputs the absolute value of the output of the difference circuit 22, and 24 is an accumulation circuit that sequentially accumulates the output of the absolute value circuit 23. A latch circuit 25 latches the output of the absolute value circuit 23 in one vertical cycle. Accumulation circuit 24
Is a clear pulse input so that it is cleared after the latch circuit 25 latches.As a result, the maximum value detection circuit 26, the minimum value detection circuit 27, and the control circuit 28, which will be described later, Is entered. 26
Is a maximum value detection circuit which receives the output of the latch circuit 25 and detects and stores the maximum value up to then. 27 is a latch circuit 25
Is a minimum value detection circuit that receives the output of the above and detects and stores the previous minimum value. 28 controls the phase of the dot clock by outputting a phase control signal to the PLL circuit 14, receives the outputs of the maximum value detection circuit 26 and the minimum value detection circuit 27, and outputs the frequency control signal to the PLL circuit 14. Thus, the control circuit controls the frequency of the dot clock.

The operation will be described with reference to FIG. FIG. 2 is a graph showing how the output of the accumulation circuit 24 obtained through the latch circuit 25 changes when the phase of the dot clock changes when a video signal of a still image is input.

Numeral 30 is an example of a plot waveform in the case where the total number of dots in one horizontal period of the input video signal coincides with the total number of dot clocks generated by the PLL 14 in one horizontal period.

At points A and C on the plotted waveform 30, the dot clock phase is located at the transition of the video signal. As a result, the video signal sampled by the A / D converter 11 is sampled at the transition point. I have. The accumulation circuit 24 and the latch circuit 25 exist for the purpose of calculating the average of the difference circuit 22 within one frame. Therefore, the result of the latch circuit has a relatively small value as shown in the graph.

At point B, the phase of the dot clock is located at the midpoint of the transition of the video signal, and the video signal is being sampled most optimally. Theoretically, the accumulation result should show the largest value. However, actually, the accumulation result does not always match due to the influence of the waveform distortion due to the transmission line, the inclusion of noise, and the nonlinearity of the analog circuit as shown in this graph.

On the other hand, reference numerals 31 and 32 denote plot waveform examples when the total number of dots in one horizontal period of the video signal and the total number of clocks in one horizontal period of the dot clock generated by the PLL 14 do not match. The plot waveform 31 is an example when the dot clock generated by the PLL 14 is two clocks less, and the plot waveform 32 is
This is an example when the dot clock generated by the LL14 is two clocks more.

In the above example, since the dot clock frequencies do not match, there is no phase in any phase state except for a very small part of the screen. Therefore, the average adjacent dot difference, which means the output of the latch circuit 25, is almost unaffected by the phase as seen in the plot waveforms 31 and 32.

According to the present invention, the PLL circuit
Is automatically adjusted so that the reproduced dot clock frequency matches the dot clock of the video signal.

The latch circuit 25 for the above-mentioned phase change
In the present invention, the ratio between the maximum value and the minimum value of the plotted waveform is used to detect the state of change of the result.

The above ratio is obtained by the control circuit 28 taking the result of the maximum value detection circuit 26 for the maximum value and the result of the minimum value detection circuit 27 for the minimum value, and calculating the ratio. These detection circuits have an advantage that they can be realized by relatively simple circuits.

As an example of obtaining the clock frequency, for example,
The control circuit 28 obtains the above-mentioned ratio after adjusting the dot clock frequency by a conventional method as a rough adjustment. further,
Since an error of ± 2 clocks still remains due to the influence of the detection error, the above ratio is similarly obtained even when the total number of dots in one horizontal period of the PLL 14 is shifted by ± 2 dots before and after. The clock at the maximum ratio among the three ratios determined above is the clock to be determined.

Further, even if not all ratios are obtained, for example,
A predetermined value may be set as ε, and when the value is equal to or less than ε, the dot clock frequency may be determined to be inconsistent, and the dot clock frequency may be shifted to obtain the ratio again. This makes it possible to reduce the average operation time. According to the results of our experiments, it is known that such ε exists.

The maximum value detection circuit 26 and the minimum value detection circuit
2. Needless to say, it can be realized by performing software processing using a microcomputer instead of the control circuit 28.

As described above, in the present embodiment, the change in the result of the latch circuit 25 with respect to the change in the phase is determined by using the ratio of the result of the maximum value detection circuit 26 to the result of the minimum value detection circuit 27. There is an advantage that the reproduced dot clock frequency can be automatically adjusted with high precision so as to match the dot clock of the video signal, and can be realized at low cost. .

(Embodiment 2) The third embodiment of the present invention will be described below.
An embodiment of the invention described in claim 4 will be described with reference to FIG. FIG. 3 is a block diagram of Embodiment 2 of the present invention. Blocks having the same functions as those in FIG. 1 used in the description of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 41 denotes a standard deviation detecting circuit which receives the output of the latch circuit 25, detects and stores the standard deviation up to then.
28 controls the phase of the dot clock output by the PLL 14 by outputting the phase control signal to the PLL circuit 14, and receives the output of the standard deviation detection circuit 41, and converts the frequency control signal to the PLL.
A control circuit for controlling the frequency of the dot clock by outputting to the circuit 14.

The present invention uses the property described with reference to FIG. 2 in the first embodiment and automatically adjusts the dot clock frequency reproduced by the PLL circuit 14 so as to match the dot clock of the video signal. It is.

The latch circuit 25 for the above-mentioned phase change
In the present invention, the standard deviation of the plotted waveform in the graph of FIG. By using the standard deviation, the degree of dispersion of the latch circuit 25 with respect to the change in the phase is normalized, so that a more quantitative determination can be made, and there is an advantage that the detection accuracy is improved. The standard deviation can be obtained by the standard deviation detection circuit 41.

As an example of obtaining the clock frequency, as in the first embodiment, for example, the control circuit 28 adjusts the dot clock frequency by a conventional method as a rough adjustment, and then obtains the standard deviation. In addition, ± 2
Since the clock error still remains,
The standard deviation is similarly obtained even when the total number of dots in the horizontal period is shifted by ± 2 dots before and after. 3 obtained above
The clock when the maximum is one of the standard deviations is the desired clock.

Even if all the standard deviations are not found, for example, a predetermined standard deviation value is set to ε, and when the standard deviation value is equal to or smaller than ε, the dot clock frequency is determined to be inconsistent, and the dot clock frequency is shifted to standard The deviation may be obtained. This makes it possible to reduce the average operation time.

Needless to say, the present invention can also be realized by performing software processing using a microcomputer instead of the standard deviation detection circuit 41 and the control circuit 28.

As described above, in this embodiment, the change in the result of the latch circuit 25 with respect to the change in the phase is based on the result of the standard deviation detection circuit 41, so that the dot clock frequency reproduced by the PLL circuit 14 can It is possible to perform automatic adjustment with higher precision so as to match the dot clock.

(Embodiment 3) A fifth embodiment of the present invention will be described below.
An embodiment of the invention described in claim 6 will be described with reference to FIG. FIG. 4 is a block diagram of Embodiment 3 of the present invention. Blocks having the same functions as those in FIG. 1 used in the description of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 42 denotes a dispersion detection circuit which receives the output of the latch circuit 25, detects and stores the dispersion up to then. Numeral 28 controls the phase of the dot clock output from the PLL 14 by outputting a phase control signal to the PLL circuit 14, and a dispersion detection circuit.
This is a control circuit that receives the output of 42 and outputs a frequency control signal to the PLL circuit 14 to control the frequency of the dot clock.

The difference from the second embodiment of the present invention is that variance is used instead of using standard deviation. Computing the standard deviation requires complicated processing of finding the square root, but using variance has the merit that the same effect can be realized with simpler processing.

As described above, in the present embodiment, the change in the result of the latch circuit 25 with respect to the change in the phase is used as the result of the dispersion detecting circuit 42, so that the dot clock frequency reproduced by the PLL circuit 14 Automatic adjustment can be performed with higher accuracy and with a simpler circuit so as to match the clock.

Needless to say, the present invention can also be realized by performing software processing using a microcomputer instead of the standard deviation circuit 42 and the control circuit 28.

(Embodiment 4) A seventh embodiment of the present invention will be described below.
An embodiment of the invention described in claim 8 will be described with reference to FIG. FIG. 5 is a block diagram of Embodiment 4 of the present invention. Blocks having the same functions as those in FIG. 1 used in the description of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 43 denotes an average value detection circuit which receives the output of the latch circuit 25, detects and stores the average up to that time. 44 is a difference circuit which receives the output of the latch circuit 25 and the output of the average value detection circuit 43 and obtains the difference. An absolute value circuit 45 receives the output of the difference circuit 44 and calculates the absolute value. 28 controls the phase of the dot clock output by the PLL 14 by outputting the phase control signal to the PLL circuit 14, and receives the output of the absolute value circuit 45, and outputs the frequency control signal to the PLL circuit 14 This is a control circuit for controlling the frequency of the dot clock.

The output of the absolute value circuit 45 can be simply used instead of the dispersion used in the third embodiment, and the same effect can be realized by a simpler circuit.

As described above, in the present embodiment, the change in the result of the latch circuit 25 with respect to the change in the phase is used as the result of the dispersion detection circuit 42, so that the dot clock frequency reproduced by the PLL circuit 14 Automatic adjustment can be performed with higher accuracy and with a simpler circuit so as to match the clock.

Needless to say, the present invention can also be realized by performing software processing using a microcomputer instead of the absolute value circuit 45, the difference circuit 44, the average value detection circuit 43, and the control circuit 28.

(Embodiment 5) A ninth aspect of the present invention will be described below.
An embodiment of the invention described in claim 10 will be described with reference to FIG. FIG. 6 is a block diagram of Embodiment 5 of the present invention. Blocks having the same functions as those in FIG. 1 used in the description of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. 46 is a smoothing circuit that receives the output of the latch circuit 25 and smoothes the variation in the data obtained so far.

The difference between the present embodiment and the first to fourth embodiments is that the result of the latch circuit 25 obtained every time the phase of the dot clock is shifted is subjected to a smoothing process.

As a result, the effect of detection errors due to noise or the like appearing in the latch circuit 25 can be reduced by the smoothing process. As a result, more accurate automatic adjustment can be performed. As described above, the present embodiment can solve the problem that the accuracy of vertical correlation detection affects the dot clock phase state as in the fifth embodiment.

[0054]

As described above, according to the present invention, a dot clock capable of automatically adjusting the dot clock frequency with high accuracy regardless of the image pattern or the waveform of the input signal and not depending on the computer or the video card. An advantageous effect that a reproducing apparatus can be provided is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a dot clock reproducing device according to a first embodiment of the present invention.

FIG. 2 is a diagram of a result of a phase VS latch circuit 25 used for describing the present invention.

FIG. 3 is a block diagram of a dot clock reproducing device according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a dot clock reproducing device according to a third embodiment of the present invention.

FIG. 5 is a block diagram of a dot clock reproducing device according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a dot clock reproducing device according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram of a conventional dot clock reproducing device.

[Explanation of symbols]

 Reference Signs List 11 A / D converter 12 Image processing circuit 13 Liquid crystal display unit 14 PLL circuit 15 Microcomputer 16 Screen size detection circuit 21 Latch circuit 22 Difference circuit 23 Absolute value circuit 24 Accumulation circuit 25 Latch circuit 28 Control circuit 30, 31, 32 Plot waveform example 41 Standard deviation detection circuit 42 Variance detection circuit 43 Average value detection circuit 44 Difference circuit 45 Absolute value circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NC21 NC24 NC26 ND48 ND60 5C006 AA02 AA03 AA11 AC21 AF44 AF64 AF72 AF81 BB11 BC16 BF02 FA27 5C020 AA16 AA35 CA20 5C021 PA18 PA26 PA28 PA56 PA57 PA58 PA72 SA09 SA08 5A080 DD EE01 EE17 EE29 FF11 GG02 GG09 GG12 JJ02 JJ05

Claims (10)

[Claims] An input signal is sampled with a dot clock to be reproduced, an absolute value of a difference between sample values between adjacent samples is accumulated, and a plurality of samples are obtained each time the phase of the dot clock is shifted. A dot clock reproducing device that automatically adjusts the frequency of the dot clock using a ratio between a maximum value and a minimum value based on the result of the accumulation. 2. An A / D converter for converting an input signal into a digital signal using the dot clock as a sampling clock, wherein the digital signal is a digital signal after the A / D conversion. 1
A latch circuit that delays a sample period, a difference circuit that outputs a difference between an output of the latch circuit and an output of the A / D converter, an absolute value circuit that outputs an absolute value of an output of the difference circuit, and the absolute value circuit An accumulation circuit for sequentially accumulating the output of the accumulator, a maximum value storage circuit for detecting and storing the maximum value of the accumulation result output from the accumulation circuit, and a minimum value for the accumulation result output from the accumulation circuit. A minimum value storage circuit that detects and stores a value, an amplitude detection circuit that determines and stores a ratio of storage contents of the maximum value storage circuit and the minimum value storage circuit, and a frequency of a sampling clock of the A / D converter. A dot clock reproducing device, comprising: a control circuit for controlling using the content output from the amplitude detection circuit. 3. A method for sampling an input signal with a dot clock to be reproduced, accumulating an absolute value of a difference between sample values between adjacent samples, and obtaining a plurality of samples each time the phase of the dot clock is shifted. A dot clock reproducing apparatus for automatically adjusting a frequency of the dot clock using a standard deviation based on a result of the accumulation. 4. An A / D converter for converting an input signal into a digital signal using the dot clock as a sampling clock, in the dot clock reproducing apparatus capable of controlling the phase and frequency, and a digital signal after the A / D conversion. 1
A latch circuit that delays a sample period, a difference circuit that outputs a difference between an output of the latch circuit and an output of the A / D converter, an absolute value circuit that outputs an absolute value of an output of the difference circuit, and the absolute value circuit An accumulation circuit that sequentially accumulates the outputs of the accumulator, a standard deviation detection circuit that determines and stores a standard deviation of the result output from the accumulation circuit, and a dispersion detection that detects the frequency of the sampling clock of the A / D converter. A dot clock reproducing device, comprising: a control circuit for controlling using contents output from the circuit. 5. A method for sampling an input signal with a dot clock to be reproduced, accumulating an absolute value of a difference between sample values between adjacent samples, and obtaining a plurality of samples each time the phase of the dot clock is shifted. A dot clock reproducing apparatus that automatically adjusts the frequency of the dot clock using dispersion based on the result of the accumulation. 6. An A / D converter for converting an input signal into a digital signal using the dot clock as a sampling clock, in the dot clock reproducing device capable of controlling phase and frequency, and a digital signal after the A / D conversion. 1
A latch circuit that delays a sample period, a difference circuit that outputs a difference between an output of the latch circuit and an output of the A / D converter, an absolute value circuit that outputs an absolute value of an output of the difference circuit, and the absolute value circuit An accumulation circuit that sequentially accumulates the outputs of the above, a dispersion detection circuit that obtains and stores the variance of the result output from the accumulation circuit, and a frequency of the sampling clock of the A / D converter, And a control circuit for controlling using the output contents. 7. The dot clock reproducing apparatus according to claim 5, wherein a processing load is reduced by simply using an absolute value instead of using a square for the calculation of the variance. 8. The dot clock according to claim 6, wherein the variance detecting circuit uses a simple absolute value instead of using a square to calculate the variance, thereby simplifying the circuit scale. Playback device. 9. The dot clock reproducing apparatus according to claim 1, wherein a smoothing process is performed on a plurality of accumulation results obtained each time the phase of the dot clock is shifted. 10. The dot clock reproducing device according to claim 2, further comprising a smoothing circuit for performing a smoothing process on a result output from the accumulation result.