JP2661401B2 - Caption decoder circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a caption decoder circuit for selectively capturing caption data superimposed in a horizontal synchronizing signal section of a video signal.

[0002]

2. Description of the Related Art In recent years, it has become necessary to provide a television receiver with a telecaption function in consideration of the hearing impaired. Therefore, one-chip microcomputers with built-in caption decoders have been used.

[0003] Caption data is superimposed on a video signal in the same manner as conventional text data of teletext, and is used for reception and reception.
The character is displayed after decryption. Therefore, an NTSC teletext decoder will be described below as a conventional technique of a caption decoder.

FIG. 3 shows an example of a configuration diagram of a conventional teletext decoder. In FIG. 3, 5 is an oscillation circuit, 6 is a phase comparison circuit, 7 is a phase shift circuit, b is caption data, h is an oscillation clock, g is a phase difference between the clock run signal and the oscillation clock h in the caption data b. , I is an output signal synchronized with the phase of the clock run signal, 3 is a shift clock generator, 4 is a shift register, and e is a shift clock. The clock run signal will be described with reference to FIG.

[0005] The clock run signal in the caption data b is extracted, and the oscillation clock h is
And a comparison voltage output signal g corresponding to the phase difference is obtained. The comparison voltage output signal g is supplied to the phase shift circuit 7.
And the output signal i synchronized with the clock run signal is obtained by shifting the phase of the oscillation clock h according to the voltage.

[0006]

In this configuration, every time the caption data b arrives, synchronization is performed with the clock run signal included in the caption data b, so that the accuracy as a clock for sampling the caption data is high, but instead the phase is changed. Because of having a comparison circuit and a phase shift circuit, the circuit becomes complicated and the circuit scale becomes large. Therefore, there was a problem that the cost was high.

SUMMARY OF THE INVENTION The present invention solves such a problem, and constitutes a caption decoder circuit having a clock generator which generates a clock capable of sampling caption data while simplifying the circuit scale and which is advantageous in terms of cost. It is intended to be.

[0008]

In order to solve this problem, the present invention provides a horizontal synchronization signal as a set input, and
RS flip with caption data as reset input
Flop and output signal from the RS flip-flop
Is a reset input, and is synchronized with the horizontal synchronization signal.
A synchronous counter using the input signal as a clock input;
Shift clock that receives the output signal from the
Clock generator and a shift clock from the shift clock generator.
A shift that inputs a lock signal and the caption data
And a register for the RS flip-flop.
When the option data is input, the RS flip-flop
Count operation is started by the output signal from
A horizontal synchronization signal is input to the RS flip-flop
And the output signal from the RS flip-flop
Output from the synchronous counter that stops the
The caption data is sampled according to the output signal.
The caption decoder circuit is configured so as to be able to read data.

[0009]

With such a configuration, it is possible to sample a caption data in the same manner as in the related art, and realize a caption decoder circuit excellent in cost, with a simple circuit configuration.

[0010]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the configuration of the caption decoder circuit of the present invention. FIG. 2 shows a timing chart of each signal shown in FIG.

In FIG. 1, reference numeral 1 denotes an RS flip-flop (hereinafter referred to as RS-FF), 2 denotes a synchronous counter,
3 is a shift clock generator, 4 is a shift register, a is a horizontal synchronizing signal, b is caption data, c is a clock synchronized with the horizontal synchronizing signal (hereinafter referred to as DOSC), d.
Is the output signal of the synchronous counter 2, e is the shift clock,
f is an output signal of the RS-FF1.

In FIG. 2, a, b, c, d, and e are the signals in FIG. 1, t1 is a clock run signal in caption data, and t2 is data to be sampled.

The RS-FF1 has the horizontal synchronization signal a set.
When input to the terminal, the logical value of the output signal f becomes “1”.
And the caption data b is input to the reset terminal
And the logical value of the output signal f becomes '0'. Therefore, DOS
In the synchronous counter 2 using Cc as a clock input, RS
-The output signal f from FF1 is input to the reset terminal
Output when the caption data b is input.
The logical value of signal f becomes '0' and starts the count operation.
When the flat synchronization signal a is input, the logical value of the output signal f becomes
Since it becomes '1', the count value is reset and
Stop counting until caption data b is input.
Stop. At this time, the synchronous counter 2 outputs a horizontal synchronous signal.
DOSCc synchronized with clock is used as clock input
Therefore, a signal synchronized with the horizontal synchronization signal a as the output signal d
Is output.

Since the caption data b is input in synchronization with the horizontal synchronizing signal a, the output signal d of the synchronous counter 2
Can be sampled using The point that the period of DOSCc is selected so that the period of the output signal d of the synchronous counter 2 is synchronized with the clock run signal;
Satisfying the point that is synchronized with the horizontal synchronization signal a, a signal equivalent to the signal i synchronized with the conventional clock run signal can be obtained.

The shift clock e is generated by inputting the output signal d of the synchronous counter 2 to the shift clock generator, and the data t2 to be sampled can be sampled. Further, the cycle of DOSCc does not necessarily need to coincide with the cycle of clock run signal t1, and there is no problem even if the cycle is slightly different as long as the last data of data t2 to be sampled can be obtained. Therefore, the accumulation of the difference between the period of the DOSCc and the period of the clock run signal t1 has a tolerance that does not exceed the range of the final data of the data t2 to be sampled.

This is due to the DO voltage caused by fluctuations in the power supply voltage and temperature.
This is very effective against the periodic fluctuation of SCc, and means that the circuit is an excellent circuit having the same effect as the conventional sampling accuracy while being a simple circuit.

[0018]

As described above, according to the present invention, a sampling clock for caption data is generated from a clock synchronized with a horizontal synchronizing signal. An excellent caption decoder circuit having a clock generator can be configured.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a caption decoder circuit of the present invention.

FIG. 2 is a timing chart of each signal in the embodiment shown in FIG. 1;

FIG. 3 is a configuration diagram of an example of a conventional teletext decoder.

[Explanation of symbols]

 Reference Signs List 1 RS-flip-flop (RS-FF) 2 Synchronous counter 3 Shift clock generator 4 Shift register 5 Oscillator 6 Phase comparator 7 Phase shifter

Claims (1)

(57) [Claims] 1. A horizontal synchronization signal is set as a set input, and
RS flip with caption data as reset input
Flop and output signal from the RS flip-flop
Is a reset input, and is synchronized with the horizontal synchronization signal.
A synchronous counter using the input signal as a clock input;
Shift clock that receives the output signal from the
Clock generator and a shift clock from the shift clock generator.
A shift that inputs a lock signal and the caption data
A caption data is input to the RS flip-flop.
When this is done, the output signal from the RS flip-flop
Counting operation, and the RS flip-flop
When a horizontal synchronizing signal is input to the flip-flop,
Before the counting operation is stopped by the output signal from the
The output signal output from the synchronous counter
Sampling caption data
That caption decoder circuit.