KR100192412B1 - Osd clock generation apparatus - Google Patents

Abstract

The present invention relates to an OSD clock generator for generating multiple delay clocks using an external clock signal and finding a delay clock closest to a horizontal synchronization signal among them, and using the same as an OSD clock. A clock source, a plurality of delay buffers connected to the clock source to generate a plurality of sequential delayed clocks from a reference clock, and the closest of the plurality of delayed clocks at a moment when a state of a horizontal synchronization signal included in the TV signal changes. It consists of a plurality of flip-flops and AND gates for detecting delayed clocks that change state in time, and a multiplexer for selecting delay clocks detected by the flip-flops and AND gates as the clock for the OSD. Internal Synchronization Reduces Board Design Costs and Reduces Errors During Synchronization The additional cost is relatively small because it can be reduced within the buffer delay of the digital library, and the design of the digital library can be simplified. The delay block is optimized to allow the delay block to be easily matched to the operating frequency and the allowable synchronization error.

Description

Clock Generator for On Screen Display (OSD)

1 is a block diagram of a conventional clock generator for the OSD.

2 is an operation timing diagram of FIG.

3 is a block diagram showing the first embodiment of the clock generator for the OSD according to the present invention.

4 is a detailed circuit diagram of a delay unit of FIG. 3.

5 is a detailed circuit diagram of the multiplexer of FIG.

FIG. 6 is an explanatory diagram illustrating a process of selecting a delay clock having a falling edge closest to a falling edge of a horizontal synchronization signal in FIG.

FIG. 7 is an explanatory diagram showing the total delay time of the delay unit in FIG. 3; FIG.

FIG. 8 is an explanatory diagram showing selected clocks of a delay unit of FIG.

9 is a block diagram showing a second embodiment of the clock generator for OSD in accordance with the present invention.

FIG. 10A is an explanatory diagram showing the total delay time of the delay unit in FIG. 9; FIG.

10B to 10D are explanatory diagrams showing selected clocks of the delay unit of FIG.

* Explanation of symbols for main parts of the drawings

31: first delay portion 32: inverter

33: second delay 34: multiplexer

35: Buffer D0 ~ Dn-1: Delay

FF0 ~ FFn-1: Flip-flop A0 ~ An-1: End gate

M1 ~ Mn-1: Bidirectional switch 91: Delay

92: multiplexer 93: buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator, and in particular, generates a multiple delay clock using an external clock signal, and finds a delay clock closest to a horizontal sync signal among them and uses it as a clock for an on screen display (OSD). It relates to a clock generator for the OSD.

In general, in order to simultaneously display TV video signals from a broadcasting station and OSD characters on a screen, an OSD clock synchronized with the horizontal synchronization signal of the video signal is required. In this case, the conventional clock generator for OSD is generated in the TV processor 11, and the TV processor 11 for generating a reset signal at the falling edge of the horizontal synchronization signal (HSYNC), as shown in FIG. It is composed of an external OSD clock generator 12 which generates a clock for the OSD after being reset by the reset signal.

Here, the external OSD clock generator 12 constitutes a Colpitts oscillator and the like as discrete elements outside the chip. That is, the TV processor 11 outputs a reset signal as shown in FIG. 2B to the external OSD clock generator 12 at the falling edge of the horizontal synchronization signal HSYNC as shown in FIG. 12 outputs an OSD clock as shown in FIG. 2C to the TV processor 11 when a reset signal is input.

The TV processor 11 spreads OSD characters on the screen in synchronization with an OSD clock provided by the external OSD clock generator 12.

As described above, the conventional clock generator generates a synchronized clock for the OSD by resetting a separate oscillator according to the horizontal synchronization signal.

However, since the first diagram described above requires several tens of ns time until the clock is stabilized after reset, a large synchronization error occurs and the OSD characters appear on the actual screen, and the OSD clock generator 12 is external to the chip. ) Is expensive. In addition, even if the oscillator is implemented inside the chip, necessary inductors and capacitors must be externally connected, and the parasitic capacitance of the chip itself cannot be accurately predicted, making it difficult to attain the correct frequency at the time of implementation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to generate a multiple delay clock which is sequentially delayed by passing a stable external clock signal with a multi-tap delay and closest to the polling edge of the horizontal synchronization signal. The present invention provides an OSD clock generator that finds a delay clock and uses the clock as an OSD clock.

A feature of the clock generator for OSD according to the present invention for achieving the above object is, in the OSD clock generator for generating a clock required to display the OSD characters on the screen with a TV signal, one reference clock A clock source for generating a signal, delay means connected to the clock source for generating a plurality of sequential delayed clocks from a reference clock, and a plurality of delayed clocks at a moment when a state of a horizontal synchronization signal included in the TV signal changes. Detecting means for detecting a delayed clock whose state changes in a near time, and clock selecting means for selecting the delayed clock detected by the detecting means as a clock for the OSD.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram showing the first embodiment of the OSD clock generator according to the present invention, which sequentially delays the external clock s_clk and multi delay clock d_clk [n-1: 0]. The first delay unit 31 for generating the selection signal s [n-1: 0], the inverter 32 for inverting the external clock s_clk, and the inverted external block s_clkb are sequentially delayed so that a multiple delay clock ( Multiple delay clocks d_clk [n-1: 0] and d_clkb [n- according to d_clkb [n-1: 0]) and the selection signals s [n-1: 0] and sb [n-1: 0] 1: 0]) and a multiplexer 34 for selectively outputting one or two delayed clocks, and a buffer 35 for outputting the multiplexer 34 to the OSD clock clk.

4 is a detailed circuit diagram of the first delay unit 31 of FIG. 3, and the second delay unit 33 has the same configuration as that of FIG.

Referring to FIG. 4, a plurality of serially connected delay buffers D0 to Dn-1 and a horizontal synchronization signal HSYNC are simultaneously provided as clocks, and outputs of the respective delay buffers D0 to Dn-1 are inputted to respective inputs D. ) And a plurality of sampling flip-flops (FF0 to FFn-1), and a plurality of AND gates (A0 to An-1) for logical combination of the inverted output of the preceding flip-flop and the output of the following flip-flop. . The multiplexer 34 is composed of a plurality of bidirectional switches M1 to Mn-1 called transfer gates.

In the present invention configured as described above, the horizontal synchronization signal HSYNC is simultaneously input to the first and second delay units 31 and 33, and the external clock s_clk is input to the first delay unit 31 and the inverter 32. The external clock inverted by is input to the second delay unit 33. In this case, since each of the first and second delay units 31 and 33 has a structure in which a plurality of delay buffers are connected in series, multiple delay clocks d_clk [n-1: 0] and d_clkb having a phase difference by one buffer delay may be used. [n-1: 0]) is output.

Here, the delay time and the number of buffers of the delay buffer depend on the operating frequency and the size of the allowable synchronization error. In addition, the output of the delay buffer is a flip-flop input except for the last buffer in the connection sequence of the delay unit as shown in FIG. At this time, the flip-flops FF0 to FFn-1 are driven by the horizontal synchronization signal HSYNC. The flip-flops FF0 to FFn-1 read a value as a delay clock at the falling edge.

The outputs of the flip-flops FF0 to FFn-1 are input to the AND gates in succession, but the output of the preceding delay buffer is inverted to become the inputs of the AND gates. The multiplexer 34 selects signals s [n-1: 0] and sb output from the first and second delay units 31 and 33 at the falling edge at which the horizontal synchronization signal HSYNC changes from high to low. Select one or two clocks from multiple delayed clocks (d_clk [n-1: 0], d_clkb [n-1: 0]) according to [n-1: 0]), and this clock is used for OSD .

At this time, the first and second delay units 31 and 33 have the horizontal synchronization signal HSYNC high in the initial state, and the multiplexer selection signals s [n-1: 0] and sb [n-1: 0]. Are maintained in a '0' state, and the first and second delay units receive an external input clock s_clk or an inverted external input clock s_clkb and output a delay clock having a phase difference at regular intervals. Then, at the rolling edge at which the horizontal synchronization signal HSYNC changes from high to low, the sampling flip-flops in the first and second delay portions 31 and 33 sample the delay buffer output, that is, the delay clock at that moment. And hold).

For example, the first delay unit 31 and the second delay unit 33 are connected in series with 12 delay buffers, and the delay clock which is the output of each delay buffer at the falling edge of the horizontal synchronization signal HSYNC is shown in FIG. Assume that it is '000000111111' as in. At this time, the delay clock having the closest edge of the horizontal synchronization signal HSYNC among the twelve multiple delayed clocks becomes the two delayed clocks that change from '0' to '1' among the 12 consecutive flip-flop outputs.

That is, the portion where the multiple delay clock value changes from '0' to '1' is the falling edge portion of the horizontal synchronization signal HSYNC. At this time, the AND gate, which receives the inverted output of the preceding flip-flop and the output of the following flip-flop as inputs, examines the outputs of all the flip-flops, so that the corresponding selection signal (s [n-1: 0], sb [n-1: 0] is changed to '1'.

If configured to select a later clock having a value of '1', the outputs of the AND gates A0 to A5 and the outputs of the AND gates A7 to A11 become '0', and the output of the AND gate A6 is selected. Only '1'.

The delayed clock is output via the multiplexer 34 in accordance with this selection signal.

That is, since only the bidirectional switch M6 of the multiplexer 34 is turned on by the selection signal s [6] output from the AND gate A6, the delayed clock d_clk [6] input to the bidirectional switch M6 is conducted. ) Is finally output through the buffer 35.

In this way, multiple delayed clocks are read at the falling edge of the horizontal sync signal (HSYNC), and the delayed clock with the nearest falling edge is selected and used for the OSD. At this time, since the present invention is composed of two delay units, the total delay time τ of the first delay unit 31 or the second delay unit 33 should have the following range as shown in FIG.

T / 2τ (T is the external clock (s_clk) period)

That is, since one delay block does not completely cover one period of the external clock s_clk, two first and second delay units are used, and the first delay unit 31 includes an external clock s_clk, The second delay unit 33 inputs the inverted clock s_clkb to completely include one clock period. There are three cases as shown in FIG. 8 when the external clock and its inverted clock are sampled by flip-flops according to the horizontal synchronization signal HSYNC.

In all cases of FIGS. 8a, b, and c, when the falling edge of the horizontal synchronization signal HSYNC exists between the multiple delay clocks of the first and second delay units 31 and 33, the corresponding selection signal is '0' to '1'. Changed to '. Each of a and c selects a delay clock corresponding to one select signal having a value of '1', but in the case of b, two delay clocks are selected. At this time, even if two delay clocks are selected as shown in FIG. 8b, the delay error between the two delay clocks is at most one buffer delay, and is connected through the multiplexer, so that the operation of the system is not affected by the bidirectional switch serving as a resistor. Do not.

FIG. 9 is a block diagram showing a second embodiment of the OSD clock generator in accordance with the present invention, in which the external clock s_clk is sequentially delayed to select multiple delay clocks d_clk [n-1: 0]. The delay unit 91 for generating the signal s [n-1: 0] and the multiple delay clocks d_clk [n− according to the selection signal s [n-1: 0] output from the delay unit 91. 1: 0]) and a multiplexer 92 for selectively outputting one or two delayed clocks, and a buffer 93 for buffering and outputting the output of the multiplexer 92 to the OSD clock clk. Since the delay unit 91 is composed of one, the total delay time? Of the delay unit 91 completely includes a clock period that should have the following range as shown in FIG.

Tτ (T is the clock cycle)

That is, the total delay time τ of the delay unit 91 must be greater than the period T of the external clock. The configuration and operation of the delay unit 91 are the same as those in FIG. 4, and the configuration and operation of the multiplexer 92 are the same as in FIG. 5.

The second embodiment of the present invention is the same as the first embodiment of the present invention except that the hinge portion is composed of one, and the total delay time? Should be larger than the period T of the external clock. Similarly, there are three cases as shown in FIG. 10 when sampling the external clock by flip-flop according to the horizontal synchronization signal HSYNC.

In all cases of FIGS. 10B, c, and D, when a falling edge of the horizontal synchronization signal HSYNC exists between the multiple delay clocks of the delay unit 91, the corresponding selection signal is changed from '0' to '1'. In b and d, one select signal has a value of '1' to select a corresponding delay clock, but in the case of c, two delay clocks are selected.

At this time, even if two delay clocks are selected as shown in FIG. 8b, the delay error between the two delay clocks is at most one buffer delay, and is connected through the multiplexer, so that the operation of the system is not affected by the bidirectional switch serving as a resistor. Do not.

Meanwhile, although the present invention selects a delay clock having a falling edge closest to the falling edge of the horizontal synchronization signal among a plurality of delay clocks and uses it for the OSD, a rising edge closest to the falling edge of the horizontal synchronization signal among the plurality of delay clocks. You can select the delay clock with and use it for OSD. At this time, the delay clock having the rising edge closest to the falling edge of the horizontal synchronization signal is a delay clock that changes from '1' to '0' among a plurality of flip-flop outputs.

In order to select the delay clock that changes from '1' to '0', the AND gate may logically combine the output of the preceding flip flop and the inverted output of the following flip flop.

As described above, the OSD clock generator according to the present invention has the following effects.

First, by receiving an external stable clock and synchronizing inside the chip, the board design cost can be reduced and synchronization errors can be reduced to less than one buffer delay.

Secondly, the additional cost is relatively small because it can be designed simply by digital library, and it is flexible because the delay block can be easily adjusted to the operating frequency and allowable synchronization error by optimization of the delay buffer.

Third, even if the overall delay time of the delay block is not correctly set, the synchronization error is changed and the operation itself is not affected. Therefore, it has a relatively strong immunity to the process change compared to other systems using the internal delay.

Fourth, the present invention can be applied not only to generate the clock for the OSD but also to synchronize two independent signals.

Claims (8)

CLAIMS 1. An OSD clock generator for generating a clock for displaying characters using an on-screen display (OSD) signal included in a TV signal, comprising: a clock source for generating one reference clock; Delay means coupled to the clock source for generating a plurality of sequential delay clocks from a reference clock; Detecting means for detecting a delayed clock whose state is changed at the closest time of the plurality of delayed clocks at the moment when the state of the horizontal synchronization signal included in the TV signal is changed; And a clock selecting means for selecting the delayed clock detected by the detecting means as a clock for the OSD. The apparatus of claim 1, wherein the delay means comprises a plurality of delay buffers connected in series. 3. The clock generator for an OSD according to claim 2, wherein the total delay time (τ) of the delay means is greater than a period (T) of the reference clock. The method of claim 1, wherein the delay means comprises two independent delay blocks in which a plurality of delay buffers are connected in series, and one delay block sequentially delays the reference clock and the other delay block sequentially inverts the reference clock. OSD clock generator. 5. The apparatus of claim 4, wherein the total delay time (τ) of each delay block is greater than a half period T / 2) of the reference clock. The clock for OSD as claimed in claim 1 or 4, wherein the detecting means selects a delay clock having a falling edge closest to the falling edge of the horizontal synchronization signal among the plurality of sequential delayed clocks outputted from the delay means. Generator. 5. The OSD clock according to claim 1 or 4, wherein the detection means selects a delay clock having a rising edge closest to the falling edge of the horizontal synchronization signal among the plurality of sequential delay clocks output from the delay means. Generator. 5. The clock generator for an OSD according to claim 1 or 4, wherein the clock selecting means comprises a multiplexer.