KR970078493A - Clock generator for on-screen display (OSD) - Google Patents

Abstract

The present invention relates to an OSD clock generator for generating a multiple delay clock using an external clock signal and finding a delay clock closest to a horizontal synchronous signal as an OSD clock, and more particularly, A plurality of delay buffers connected to the clock source and generating a plurality of sequential delay clocks from the reference clock; a plurality of delay buffers connected to the clock source, And a multiplexer for selecting a delayed clock detected by the flip-flop and the end gate as an OSD clock, and receives an external stable clock to receive a clock Because it is synchronized internally, it reduces board design cost, And can be easily designed with digital library. Therefore, the additional cost is relatively small, and the delay block can be easily adjusted to the operating frequency and tolerable error by the optimization of the delay buffer, so that the design flexibility is obtained.

Description

Clock generator for on-screen display (OSD)

Since this is a trivial issue, I did not include the contents of the text.

FIG. 3 is a block diagram showing a first embodiment of a clock generator for OSD according to the present invention, FIG. 4 is a detailed circuit diagram of the delay unit of FIG. 3, and FIG. 5 is a detailed circuit diagram of the multiplexer of FIG.

Claims (8)

CLAIMS 1. An OSD clock generator for generating a clock for displaying characters using an on-screen display (OSD) signal included in a TV signal, the OSD clock generator comprising: a clock source for generating one reference clock; Delay means for generating a plurality of sequential delay clocks from the clock; Detecting means for detecting a delayed clock whose state changes at a nearest time among the plurality of delayed clocks at the moment when the state of the horizontal synchronizing signal included in the TV signal is changed; And clock selecting means for selecting the delay clock detected by said detecting means as the OSD clock. The apparatus of claim 1, wherein the delay unit includes a plurality of delay buffers serially connected. The apparatus of claim 2, wherein the total delay type (t) of the delay means is greater than the period (T) of the reference clock. [2] The apparatus of claim 1, wherein the delay unit comprises two independent delay blocks connected in series, one delay block delays the reference clock, and the remaining delay blocks sequentially delay the inverted reference flaps Clock generator for OSD. The apparatus of claim 4, wherein the total delay time (t) of each delay block is greater than a half period (T / 2) of the reference clock. The method as claimed in claim 1 or 4, wherein the detecting means selects a delayed clock having a polling edge closest to a polling edge of a plurality of sequential delay clock horizontal synchronizing signals output from the delay means, Device. The oscillation clock according to claim 1 or 4, wherein the detecting means selects a delayed clock having a rising edge closest to the polling edge of the horizontal synchronizing signal among the plurality of sequential delayed clocks output from the delaying means, Generating device. The apparatus of claim 1 or 4, wherein the clock selecting means comprises a multiplexer. ※ Note: It is disclosed by the contents of the first application.