JPH04339482A - Caption decoder circuit - Google Patents

Abstract

PURPOSE:To selectively input the caption data superposed in a horizontal synchronizing signal section of a video signal by a circuit configuration which is simple, and profitable as its cost, as well. CONSTITUTION:An RS-flip-flop 1 generates an output signal of a logical value '0' by a horizontal synchronizing signal (a), generates an output signal of a logical value 'l' by caption data (b), and supplies it to a reset terminal of a synchronizing counter 2. The synchronizing counter 2 operates, when the caption data (b) comes, and stops by the next horizontal synchronizing signal (a). In this case, DOSCc is inputted as its clock and an output signal (d) becomes a signal synchronized with the horizontal synchronizing signal (a). By inputting the output signal (c) of the synchronizing counter 2 to a shift clock generator, a shift clock (e) is generated, and the caption data (b) is subjected to sampling.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a caption decoder circuit that selectively captures caption data superimposed within a horizontal synchronizing signal section of a video signal.

0002

2. Description of the Related Art In recent years, it has become necessary to add a telecaption function to television receivers in consideration of the hearing-impaired. Therefore, one-chip microcomputers with a built-in caption decoder have come into use.

[0003] Caption data is superimposed on a video signal like the character data of conventional teletext broadcasting, and is
The characters are displayed after decoding. Therefore, as a conventional technology for caption decoders, an NTSC teletext decoder will be described below.

FIG. 3 shows an example of a configuration diagram of a conventional teletext decoder. In FIG. 3, 5 is an oscillation circuit, 6 is a phase comparison circuit, 7 is a phase shift circuit, b is caption data, h is an oscillation clock, and g is the phase difference between the clock run signal in the caption data b and the oscillation clock h. i is an output signal synchronized with the phase of the clock run signal, 3 is a shift clock generator, 4 is a shift register, and e is a shift clock. Note that the clock run signal will be explained with reference to FIG.

[0005] The clock run signal in the caption data b is taken out, and the phase comparison circuit 6 converts it into an oscillation clock h.
A comparison voltage output signal g corresponding to the phase difference is obtained. This comparison voltage output signal g is transferred to the phase shift circuit 7.
The output signal i synchronized with the clock run signal was obtained by shifting the phase of the oscillation clock h according to the voltage.

[0006]

[Problem to be Solved by the Invention] In this configuration, synchronization is achieved with the clock run signal included in caption data b every time caption data b arrives, so the accuracy as a clock for sampling caption data is high, but at the cost of Since it includes a comparison circuit and a phase shift circuit, the circuit becomes complicated and the circuit scale becomes large. Therefore, there was a problem that the cost was high.

The present invention solves these problems by constructing a caption decoder circuit having a cost-effective clock generator that generates a clock that can sample caption data while simplifying the circuit scale. The purpose is to

[0008]

[Means for Solving the Problem] In order to solve this problem, the present invention provides a caption decoder having a clock generator that generates a clock capable of sampling caption data using a clock synchronized with a horizontal synchronization signal. It constitutes a circuit.

[0009]

[Operation] With such a configuration, it is possible to realize a caption decoder circuit which is simple in circuit configuration, can sample caption data in the same way as in the past, and is superior in terms of cost.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the configuration of a caption decoder circuit according to the present invention. FIG. 2 shows a timing diagram of each signal shown in FIG.

In FIG. 1, 1 is an RS-flip-flop (hereinafter referred to as RS-FF), 2 is a synchronous counter,
3 is a shift clock generator, 4 is a shift register, a is a horizontal synchronization signal, b is caption data, c is a clock synchronized with the horizontal synchronization signal (hereinafter referred to as DOSC), d
is the output signal of synchronous counter 2, e is the shift clock,
f is the output signal of RS-FF1.

In FIG. 2, a, b, c, d, and e are the signals shown in FIG. 1, t1 is a clock run signal within caption data, and t2 is data to be sampled.

The output signal f of the RS-FF 1 becomes a logic value '0' due to the horizontal synchronization signal a, and becomes a logic value '1' due to the caption data b. Since the output signal f is input to reset the synchronous counter 2, the operation starts when the caption data b arrives and stops at the next horizontal synchronization signal a. At this time, D is used as the clock for the synchronous counter 2.
Since OSCc is input, the output signal d of the synchronous counter 2 is generated as a signal synchronized with the horizontal synchronizing signal a.

Since the caption data b is input in synchronization with the horizontal synchronizing signal a, the output signal d of the synchronous counter 2
It is possible to sample using The period of DOSCc is selected so that the period of output signal d of synchronous counter 2 is synchronized with the clock run signal, and DOSCc
By satisfying the point that is synchronized with the horizontal synchronization signal a, it is possible to obtain a signal equivalent to the signal i synchronized with the conventional clock run signal.

By inputting the output signal d of the synchronous counter 2 to a shift clock generator, a shift clock e is generated, and data t2 to be sampled can be sampled. Further, the period of DOSCc does not necessarily have to match the period of the clock run signal t1, and even if the period is slightly different, there is no problem as long as the final data of the data t2 to be sampled can be obtained. Therefore, the accumulation of the difference between the period of DOSCc and the period of clock run signal t1 has a tolerance that does not exceed the range of the final data of data t2 to be sampled.

[0017] This is due to changes in the power supply voltage and temperature.
This means that it is very effective against periodic fluctuations in SCc, and although it is a simple circuit, it is an excellent circuit that has the same effect as conventional sampling accuracy.

[0018]

[Effects of the Invention] As described above, according to the present invention, by generating a sampling clock for caption data from a clock synchronized with a horizontal synchronization signal, it is more advantageous than the conventional technology in terms of cost, and has the same performance as the conventional technology. An excellent caption decoder circuit with a clock generator can be constructed.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of a caption decoder circuit of the present invention.

[Figure 2] Timing diagram of each signal in the embodiment shown in Figure 1

[Figure 3] Configuration diagram of an example of a conventional teletext decoder

[Explanation of symbols]

1 RS-flip-flop (RS-FF) 2 Synchronous counter 3 Shift clock generator 4 Shift register 5 Oscillation circuit 6 Phase comparison circuit 7 Phase shift circuit

Claims (1)

[Claims] 1. A caption decoder circuit having a clock generator for generating a clock for sampling caption data from a clock synchronized with a horizontal synchronization signal.