JPH1070737A - Sampling converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide interleaved video signals in the digital circuit of a small scale by obtaining horizontal synchronizing signals from non-standard composite video signals by an arithmetic operation. SOLUTION: A color burst lock clock generation means 5 generates color burst lock clocks CK(C) locked to color burst signals P7(C) from a synchronizing separation means 7. A Y-C separation means 3 separates digital composite video signals S2 from an A/D conversion means 2 into luminance signals Y3 and chrominance signals C3. A re-sample coefficient generation means 6 generates re-sample coefficients K and (1-K) based on the luminance signals Y3 and timing pulses P8 from a timing pulse generation means 8. A re-sample means 4 level-corrects the luminance signals Y3 and the chrominance signals C3 by the re-sample coefficients K and (1-K) and outputs the digital luminance signals Y and chrominance signals C for which frequency interleaving is restored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite video signal sampling converter, and uses a small digital circuit to restore the frequency interleaving relationship between a luminance signal component and a carrier chrominance signal component from a non-standard composite video signal. The present invention relates to a sampling converter that generates a video signal.

[0002]

2. Description of the Related Art Conventionally, as a sampling converter for a composite video signal of this kind, for example, Japanese Patent Application Laid-Open No. 63-269697 is used.
As disclosed in Japanese Unexamined Patent Application Publication No. H10-204, in a device for converting a non-standard analog composite video signal into a digital composite video signal, a horizontal synchronization signal separated from the analog composite video signal and a color burst lock clock are divided. By detecting the time shift from the obtained digital horizontal synchronizing signal and weighting the sample values of the digital video signal converted according to this shift, the sampling signal obtained by linearly interpolating between adjacent pixel values is obtained. Are known.

[0003]

Problems to be Solved by the Invention Japanese Patent Application Laid-Open No. 63-2696
In the composite video signal sampling converter disclosed in Japanese Patent Application Laid-Open No. 97-1997, the level of the front porch or the back porch of the horizontal synchronizing signal to be clamped by the clamp circuit from the analog composite video signal is affected by the video signal, and accurate clamping is performed. Therefore, there is a problem that a DC reproduction of a correct video signal cannot be performed.

[0004] Further, a sampling and converting apparatus for a composite video signal disclosed in Japanese Patent Application Laid-Open No. 63-269697 includes:
There is a problem that it is not possible to separate a horizontal synchronizing signal having a small time-axis fluctuation, which is a time-axis reference, from an analog composite video signal by a sync separation circuit using a clamp circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and has as its object the purpose of performing an arithmetic operation from a non-standard digital composite composite video signal sampled with a color burst lock clock. Sampling that stably finds the timing of the horizontal synchronization signal that serves as a reference for the time axis, and uses a small digital circuit to generate a video signal that restores the frequency interleaving relationship between the color subcarrier and the horizontal synchronization signal. A conversion device is provided.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, a sampling converter according to the present invention is provided with a color burst lock for generating a color burst lock clock for sampling an analog composite video signal by locking to a color burst signal. A clock generation means, a timing pulse generation means for generating a timing pulse based on a horizontal synchronization signal, and a resampling coefficient generation for generating a resampling coefficient based on the timing pulse from the timing pulse generation means and the digital composite video signal And resampling means for resampling the digital composite video signal with a color burst lock clock from a color burst lock clock generating means based on a timing pulse from the timing pulse generating means. I do.

A sampling conversion apparatus according to the present invention comprises a color burst lock clock generating means for generating a color burst lock clock for sampling an analog composite video signal by locking to a color burst signal, and a timing based on a horizontal synchronizing signal. A timing pulse generator for generating a pulse, a resample coefficient generator for generating a resample coefficient based on the timing pulse from the timing pulse generator and the digital composite video signal, and a digital composite video signal from the timing pulse generator. Resampling means for performing resampling with the color burst lock clock from the color burst lock clock generation means based on the timing pulse of
Thus, a digital video signal obtained by restoring the frequency interleaving of the luminance signal component and the carrier chrominance signal component from the non-standard composite video signal can be obtained.

In the sampling converter according to the present invention, the resampling coefficient generating means includes a front edge extracting means for extracting a front edge portion of the horizontal synchronizing signal from the digital composite video signal based on the timing pulse from the timing pulse generating means. Pedestal level calculating means for extracting a pedestal level portion from a digital composite video signal based on a timing pulse from a timing pulse generating means and calculating an average pedestal level from a plurality of pedestal level values; and timing pulse generating means A sync tip level calculating means for extracting a sync tip level portion of the horizontal synchronizing signal from the digital composite video signal based on the timing pulse from and calculating an average sync tip level from a plurality of sync tip level values; Intermediate level calculating means for calculating an intermediate level between the pedestal level and the average sync tip level; level comparing calculating means for performing a level comparing operation between the front edge portion and the intermediate level from the front edge extracting means; Polarity inversion detection means for detecting polarity inversion of the output signal of the means, resampling coefficient calculation means for calculating a resampling coefficient based on the front edge portion from the front edge extraction means and the output signal of the polarity inversion detection means, It is characterized by having.

In the sampling conversion apparatus according to the present invention, the resampling coefficient generating means includes a front edge extracting means, a pedestal level calculating means, a sync tip level calculating means, an intermediate level calculating means, and a level comparing calculating means. , A polarity inversion detecting means, and a resampling coefficient calculating means, so that an accurate and stable timing of a horizontal synchronizing signal serving as a reference of a time axis can be obtained from the digital composite video signal. A highly accurate resample coefficient can be generated based on the signal timing.

Further, in the sampling conversion apparatus according to the present invention, the resampling means includes a one clock delay means for delaying the video signal by one clock, an input / output video signal of the one clock delay means, and a resampling means for the resampling coefficient generation means. Resampling value correcting means for performing linear interpolation between pixels adjacent in the horizontal scanning direction by calculating with a coefficient.

In the sampling conversion apparatus according to the present invention, the resampling means includes one clock delay means for delaying the video signal by one clock, input / output video signals of the one clock delay means, and resampling coefficients of the resampling coefficient generation means. And re-sample value correction means for performing linear interpolation between pixels adjacent in the horizontal scanning direction by the calculation of the above, so that the frequency interleaving of the luminance signal component and the carrier chrominance signal component from the non-standard composite video signal can be improved. A digital video signal restored with high accuracy can be obtained.

[0012]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is an overall block configuration diagram of a sampling conversion device according to the present invention. In FIG. 1, a sampling converter 1 includes an A / D converter 2, Y
-C separation means 3, resampling means 4, color burst lock clock generation means 5, resampling coefficient generation means 6, synchronization separation means 7, and timing pulse generation means 8.

The synchronizing separation means 7 converts the analog composite video signal V
s to the horizontal synchronization signal P7 (H) and the color burst signal P7 (C)
And separate. The color burst lock clock generating means 5 generates a color burst lock clock CK (C) locked to the separated color burst signal P7 (C).

The A / D converter 2 samples the analog composite video signal Vs with the color burst lock clock CK (C) and converts it into a digital composite video signal S2. Y
The -C separating means 3 separates the digital composite video signal S2 into a luminance signal Y3 and a chrominance signal C3.

The timing pulse generating means 8 generates a timing pulse P8 based on the horizontal synchronizing signal P7 (H).
The resampling coefficient generating means 6 calculates the resampling coefficients K and (1-K) based on the luminance signal Y3 and the timing pulse P8.
And generate

The resampling means 4 performs level correction of the luminance signal Y3 and the chrominance signal C3 sampled by the color burst lock clock CK (C) using resampling coefficients (K, 1-K), and performs frequency interleaving. The restored digital luminance signal Y and chrominance signal C are output.

As described above, the sampling conversion device 1
Since it includes an AD converter 2, a YC separator 3, a resampler 4, a color burst lock clock generator 5, a resample coefficient generator 6, a sync separator 7, and a timing pulse generator 8, In addition, a digital luminance signal Y and a color signal C obtained by restoring the frequency interleaving of the luminance signal component and the carrier chrominance signal component from the non-standard composite video signal can be obtained.

FIG. 2 is a block diagram of a main part of the resampling coefficient generating means according to the present invention. In FIG. 2, the resampling coefficient generating means 6 is a front edge extracting means 1.
0, pedestal level calculating means 11, sync tip
It comprises a level calculating means 12, an intermediate level calculating means 13, a level comparing calculating means 14, a polarity inversion detecting means 15, and a resampling coefficient calculating means 16.

The operation of the resampling coefficient generating means 6 will be described with reference to the drawing of the front edge portion of the horizontal synchronizing signal shown in FIG. In FIG. 3, sample values PX1 to PX12 are digital values sampled by the color burst lock clock CK (C), sample values PX1 to PX4 are sample values of the front porch portion of the horizontal synchronization signal, and sample values PX5 to PX5 P
X9 is the sample value of the front edge of the horizontal sync signal,
The sample values PX10 to PX12 are sample values of the sync tip portion of the horizontal synchronization signal.

The front edge extracting means 10 generates a plurality of sample values (PX5 to PX) of the front edge portion of the horizontal synchronizing signal based on the front edge timing pulse P8 (E) from the timing pulse generating means 8 from the luminance signal Y3.
9), and outputs this as a front edge signal S10.

The pedestal level calculator 11 calculates a plurality of sample values (PX1 to PX4) of the front porch portion of the horizontal synchronizing signal based on the front porch timing pulse P8 (P) from the timing pulse generator 8 based on the luminance signal Y3. Is extracted, the average value of a plurality of sampled values is calculated, and the calculation result is output as a pedestal level signal S11.

The sync tip level calculation means 12 calculates a plurality of sample values (PX10 to PX12) of the sync tip portion of the horizontal synchronization signal based on the sync tip timing pulse P8 (S) from the timing pulse generation means 8 from the luminance signal Y3. ) Is extracted, the average value of a plurality of sampled values is calculated, and the calculation result is output as a sync tip level signal S12.

The intermediate level calculating means 13 is provided with a pedestal
Pedestal level signal S11 from level calculating means 11
And an intermediate level of the sync tip level signal S12 from the sync tip level operation means 12 and outputs the operation result as an intermediate level signal S13.

The level comparison / calculation means 14 uses the intermediate level signal S13 from the intermediate level calculation means 13 as a threshold value and uses the front edge signal S
A level comparison operation (PXN-S13) with 10 is performed, and the operation result is output as a level comparison signal S14.

The polarity inversion detection means 15 detects sample values (PX7, PX8) before and after the polarity of the level comparison signal S14 from the level comparison operation means 14 is inverted from plus (+) to minus (-). Sample values before and after (PX7, PX8)
Is output as the polarity inversion signal S15, and when the level comparison signal S14 becomes zero (PXN-S13 = 0), the sample value PXN
Is output as the polarity inversion signal S15.

The resampling coefficient calculating means 16 calculates the resampling coefficient {K = │ (S13−PX8) │ / │ (PX7−PX8) based on the polarity inversion signal S15 from the polarity inversion detecting means 15.
|, 1−K}, and outputs a resample coefficient (K, 1−K).

As described above, the resampling coefficient generating means 6
Are front edge extracting means 10, pedestal level calculating means 11, sync tip level calculating means 12,
The provision of the intermediate level calculating means 13, the level comparing calculating means 14, the polarity reversing detecting means 15, and the resampling coefficient calculating means 16 allows the timing of the horizontal synchronizing signal to be accurate and stable from the digital composite video signal and to serve as a reference for the time axis. And the resampling coefficient (K, 1-K) can be generated based on the timing of the horizontal synchronization signal.

FIG. 4 is a block diagram of a main part of the resampling means according to the present invention. In FIG. 4, the resampling unit 4 includes a buffer storage unit 20, an AND gate 21, a one-clock delay unit 22, a storage unit 29, and an AND gate 3.
0, an AND gate 31, and a resample value correction unit 32. The resampling value correction means 32 includes multiplication means 23 and 2
4, 25, 26 and adding means 27, 28.

The buffer storage means 20 stores the luminance signal Y3 and the color signal C3 in a color burst lock clock CK (C).
The AND gate 21 is opened by the buffer read timing pulse P8 (BR) from the timing pulse generating means 8 which has been written and stored, and the delay time has been adjusted by the operation up to the resampling coefficient generating means 6, via the AND gate 21. The luminance signal Y3 and the color signal C3 are read by the color burst lock clock CK (C).

The one-clock delay means 22 delays the luminance signal Y20 and the chrominance signal C20 from the buffer storage means 20 by one clock of the color burst lock clock CK (C).

Multiplication means 23 of resample value correction means 32
Performs a multiplication operation on the resampling coefficient (K) generated by the resampling coefficient generation means 6 and the luminance signal Y20 to output a corrected luminance signal Y23 (K × Y20). The multiplying means 24 of the resampling value correcting means 32 performs a multiplication operation of the resampling coefficient (K) generated by the resampling coefficient generating means 6 and the color signal C20 to output a corrected color signal C24 (K × C20). .

The multiplication means 26 of the resample value correction means 32
Is the resampling coefficient (1-K) and one clock delay means 2
2 to output a corrected luminance signal Y26 {(1−K) × Y22}. The multiplication means 25 of the resample value correction means 32 outputs the resample coefficient (1-
K) is multiplied by the color signal C22 from the one-clock delay means 22 to output a corrected color signal C25 {(1−K) × C22}.

Adder 28 of resampled value corrector 32
Performs an addition operation of the corrected luminance signal Y23 and the corrected luminance signal Y26 to output a corrected luminance signal Y28 (Y23 + Y26).
The adding means 27 of the resample value correcting means 32 performs an addition operation of the corrected color signal C24 and the corrected color signal C25 and outputs a corrected color signal C27 (C24 + C25).

The storage means 29 opens the AND gate 30 with the write timing pulse P8 (W) from the timing pulse generation means 8, and outputs the corrected luminance signal Y28 with the color burst lock clock CK (C) via the AND gate 30. The correction color signal C27 is written and stored, and the AND gate 31 is opened by the read timing pulse P8 (R) from the timing pulse generation means 8, and the color burst lock clock CK (C) is passed through the AND gate 31. By reading out the stored corrected luminance signal Y28 and corrected color signal C27, a digital luminance signal Y and a color signal C whose frequency interleaving is restored are output.

As described above, the resampling unit 4 includes the buffer storage unit 20, the AND gate 21, the one-clock delay unit 22, the storage unit 29, the AND gate 30, the AND gate 31, and the resampled value correction unit 32. A digital luminance signal Y and color signal C can be obtained by restoring the frequency interleaving of the luminance signal component and the carrier chrominance signal component from the non-standard composite video signal.

The above embodiment is an example of the present invention, and the present invention is not limited to the above embodiment.

[0037]

According to the present invention, the following effects are exhibited by the above configuration. A sampling conversion apparatus according to the present invention includes: a color burst lock clock generating means for generating a color burst lock clock for sampling an analog composite video signal by locking to a color burst signal; and generating a timing pulse based on a horizontal synchronization signal. Timing pulse generation means, and a resample coefficient generation means for generating a resample coefficient based on the timing pulse from the timing pulse generation means and the digital composite video signal,
Resampling means for resampling the digital composite video signal with the color burst lock clock from the color burst lock clock generation means based on the timing pulse from the timing pulse generation means, and a small digital circuit, Since a digital video signal can be obtained by restoring the frequency interleaving of the luminance signal component and the carrier chrominance signal component from the non-standard composite video signal, an image with less interference by the carrier chrominance signal can be obtained.
Performance can be improved and economy can be improved.

In the sampling converter according to the present invention, the resampling coefficient generating means includes a front edge extracting means for extracting a front edge portion of the horizontal synchronizing signal from the digital composite video signal based on the timing pulse from the timing pulse generating means. Pedestal level calculating means for extracting a pedestal level portion from a digital composite video signal based on a timing pulse from a timing pulse generating means and calculating an average pedestal level from a plurality of pedestal level values; and timing pulse generating means A sync tip level calculating means for extracting a sync tip level portion of the horizontal synchronizing signal from the digital composite video signal based on the timing pulse from and calculating an average sync tip level from a plurality of sync tip level values; Intermediate level calculating means for calculating an intermediate level between the pedestal level and the average sync tip level; level comparing calculating means for performing a level comparing operation between the front edge portion and the intermediate level from the front edge extracting means; Polarity inversion detection means for detecting polarity inversion of the output signal of the means, resampling coefficient calculation means for calculating a resampling coefficient based on the front edge portion from the front edge extraction means and the output signal of the polarity inversion detection means, It is possible to obtain an accurate and stable timing of a horizontal synchronization signal as a reference of a stable time axis from a digital composite video signal, and to generate a highly accurate resampling coefficient based on the timing of the horizontal synchronization signal. Image with less interference from the carrier chrominance signal, improving performance and stability. It can be achieved.

Further, in the sampling conversion apparatus according to the present invention, the resampling means includes one clock delay means for delaying the video signal by one clock, input / output video signals of the one clock delay means, and resampling of the resampling coefficient generation means. Resampling value correction means for performing linear interpolation between pixels adjacent in the horizontal scanning direction by calculating with coefficients, and using a small-scale digital circuit, a luminance signal component and a carrier color signal component from a non-standard composite video signal. Therefore, it is possible to obtain a digital video signal obtained by restoring the frequency interleaving with higher accuracy, so that an image with less interference by the carrier chrominance signal can be obtained and the size can be reduced.

Therefore, high-performance, high-stability, and clear images can be obtained with little interference by the carrier color signal.
A compact and economical sampling conversion device can be provided.

[Brief description of the drawings]

FIG. 1 is an overall block configuration diagram of a sampling conversion device according to the present invention.

FIG. 2 is a block diagram of a main part of a resampling coefficient generation unit according to the present invention.

FIG. 3 is an explanatory diagram of a front edge portion of a horizontal synchronization signal.

FIG. 4 is a block diagram of a main part of a resampling unit according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Sampling conversion device, 2 ... AD conversion means, 3 ...
YC separation means, 4 ... resampling means, 5 ... color burst lock clock generation means, 6 ... resampling coefficient generation means, 7 ... synchronization separation means, 8 ... timing pulse generation means, 9 ... line lock clock generation Means, 10 ... front edge extracting means, 11 ... pedestal level calculating means, 12 ... sync tip level calculating means, 13 ...
Intermediate level operation means, 14 ... level comparison operation means, 15
... Polarity reversal detecting means, 16 ... Resample coefficient calculating means,
20: buffer storage means, 21, 30, 31 ... AND gate, 22: clock delay means, 23, 24, 25, 2
6 multiplication means, 27, 28 addition means, 29 storage means, 32 resample value correction means, C, C3 color signals,
C20: color signal, C24, C25, C27: corrected color signal, CK
(C): Color burst lock clock, K, (1-
K) ... resampling coefficient, P8 ... timing pulse, P8 (B
R): Buffer storage buffer read timing pulse,
P7 (C): color burst signal, P7 (H): horizontal synchronization signal,
P7 (HL): Horizontal synchronization signal, P8 (E): Front edge timing pulse, P8 (P): Front porch timing pulse, P8 (R): Read timing pulse, PX1 to PX12
... Sampling value, S2 ... Digital composite video signal, S10 ... Front edge signal, S11 ... Pedestal level signal, S12
... Sync tip level signal, S13 ... Intermediate level signal,
S14: level comparison signal, S15: polarity inversion signal, Y, Y
3, Y20: luminance signal, Y23, Y26, Y28: corrected luminance signal, Vs: analog composite video signal.

Claims (3)

[Claims] 1. A non-standard analog composite video signal in which a luminance signal component and a carrier chrominance signal component do not have a frequency interleaving relationship is converted into a digital composite video signal by a sampling clock locked to a color burst signal. In a sampling converter for resampling a video signal and generating a video signal in which a frequency interleaving relation is restored, a color burst for locking to a color burst signal and generating a color burst lock clock for sampling the analog composite video signal Lock clock generating means, timing pulse generating means for generating a timing pulse based on a horizontal synchronizing signal, and a resampling coefficient based on the timing pulse from the timing pulse generating means and the digital composite video signal. Resampling coefficient generating means for generating, and resampling means for resampling the digital composite video signal with a color burst lock clock from the color burst lock clock generating means based on a timing pulse from the timing pulse generating means And a sampling conversion device. 2. A re-sampling coefficient generating unit, comprising: a front edge extracting unit for extracting a front edge portion of a horizontal synchronizing signal from the digital composite video signal based on a timing pulse from the timing pulse generating unit; Pedestal level calculating means for extracting a pedestal level portion from the digital composite video signal based on the timing pulse from the means and calculating an average pedestal level from a plurality of pedestal level values; and timing from the timing pulse generating means. Sync tip level calculating means for extracting a sync tip level portion of a horizontal synchronizing signal from the digital composite video signal based on a pulse and calculating an average sync tip level from a plurality of sync tip level values; Wherein the Tal level average sync chip
Intermediate level calculating means for calculating an intermediate level with the level, level comparing calculating means for performing a level comparing operation between the front edge portion from the front edge extracting means and the intermediate level, and an output signal of the level comparing calculating means. Polarity inversion detection means for detecting polarity inversion, and resampling coefficient calculation means for calculating a resampling coefficient based on a front edge portion from the front edge extraction means and an output signal of the polarity inversion detection means. The sampling conversion device according to claim 1, wherein: 3. A one-clock delay means for delaying a video signal by one clock to the re-sampling means; and a horizontal circuit by calculating an input / output video signal of the one-clock delay means and a re-sampling coefficient of the re-sampling coefficient generation means. 2. The sampling conversion apparatus according to claim 1, further comprising: resampling value correction means for performing linear interpolation between pixels adjacent in the scanning direction.