JPH05199543A - Digital video signal processing circuit - Google Patents

Abstract

PURPOSE:To use an A/D converter for both the digital processing of TV video signals and for the video processing by supplying a sampling clock to the A/D converter during the processing. CONSTITUTION:The analog video signal inputted through a terminal 1 is given to an A/D converter 2 which converts this video signal into a digital signal. Then the converter 2 converts the clock signal sent from a selecting circuit 3 into a digital signal serving as a sampling standard. The circuit 3 switches the sampling clock given to the converter 2 to the clock signal given from an mFsc clock generating circuit 5 or an nFh clock generating circuit 6 in accordance with an H or L state of the timing signal CKS sent from a timing generating circuit 4. The circuit 5 produces a clock signal having a phase synchronous with a burst signal and supplies this clock signal to the circuit 3, a Y/C separating circuit 8, a color demodulating circuit 9, and various video processing circuits respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal processing circuit having an improved A / D function in digital processing of TV video signals.

[0002]

2. Description of the Related Art Recently, digital L including memory
With the development of SI technology and digital signal processing technology, the use of digital signal processing methods for home video equipment is also becoming widespread, and the number of TV receivers that use such digital signal processing methods is increasing. There is.
FIG. 3 shows the configuration of the video signal processing unit of the TV receiver according to the digital signal processing method. The digital video signal processing of the TV receiver shown in FIG. 3 will be described below.

The video signal supplied from the terminal 301 is first converted into a digital signal by the A / D converter 302.
The converted digital video signal is input to the burst separation circuit 304 together with the timing signal CBFP given from the timing generation circuit 303. The burst separation circuit 304 separates the burst signal, which is the reference carrier of the carrier color signal, from the digital video signal based on the timing signal CBFP and sends it to the mFsc clock generation circuit 305.

The mFsc clock generation circuit 305 generates a clock signal whose phase is synchronized with the burst signal based on the separated burst signal, and uses this clock signal for A / D.
Converter 302, Y / C separation circuit 306, color demodulation circuit 30
7 and the video processing circuit of each part.

In a TV receiver, the frequency of the clock signal is usually four times that of the burst signal, that is, 4Fsc. Further, the mFsc clock generation circuit 305 generates a signal DFS having the same phase and frequency as the burst signal in order to provide a reference phase when demodulating the C signal amplitude-modulated by the color demodulation circuit 307.

The output signal of the A / D converter 302 is Y
It is supplied to the / C separation circuit 306 and separates the Y signal and the C signal from the digital video signal. The separated Y signal is output from the terminal 308, and thereafter, contour compensation or the like is performed by a contour compensation circuit not shown in FIG.

The separated C signal is demodulated in the color demodulation circuit 307 with reference to the signal DFS given from the mFsc clock generation circuit 305. If an analog video signal is sampled at a frequency of 4 Fsc, the terminal 309
The R-Y / B-Y signals are alternately output every 1 clock.

Next, digital sync signal processing will be described. Normally, in an NTSC video signal, a burst signal, that is, a color carrier frequency Fsc and a horizontal sync frequency Fh.
The following relationship is established between and. Fsc = (455 × Fh) / 2 (Equation 1)

Therefore, if the clock generated by the mFsc clock generation circuit 305 is divided (for example, the frequency is 4F).
In the clock of sc, the frequency is divided by 1/910), and a signal having the same frequency as the horizontal synchronizing signal Fh is obtained.

However, some recent video media, especially VTRs, etc., generate signals which do not satisfy the above-mentioned relationship between Fsc and Fh. Even in such a video medium, it is possible to reproduce the horizontal synchronizing signal by the method of dividing the clock phase-synchronized with the color carrier as described above, but the horizontal synchronizing signal is reproduced with a precision smaller than one clock. It is impossible to do. Therefore, when a TV signal is displayed by the horizontal synchronizing signal reproduced by this method, the image slightly moves left and right with 1 line / 1 clock width on the TV screen, resulting in a remarkable deterioration of the image quality.

Therefore, in the synchronizing signal processing in the digital signal processing type TV receiver, a clock phase-synchronized with the horizontal synchronizing signal is used in addition to the video processing. That is, in order to separate the horizontal synchronizing signal of the digital signal processing system, the digital synchronizing signal separating circuit as shown in the figure is used.

The video signal supplied from the terminal 301 is first converted into a digital signal by the A / D converter 310.
At this time, the sampling clock signal of the A / D converter 310 is supplied from the nFh clock generation circuit 311 unlike the sampling clock signal supplied to the A / D converter 302. The converted digital video signal is applied to the horizontal sync separation circuit 312, and the horizontal sync separation circuit 312 extracts the horizontal sync signal from the digital video signal.

The nFh clock generation circuit 311 generates a clock signal having a frequency n times phase-locked with the horizontal synchronizing signal based on the separated horizontal synchronizing signal. In addition, a signal HRE whose phase and frequency completely match the horizontal sync signal
F is output as a reproduction horizontal synchronizing signal. In addition, the nFh clock generated by the nFh clock generation circuit 311 is
/ D conversion circuit 310, horizontal and vertical sync separation circuit 31
2, 314, a horizontal synchronization control circuit 313, a vertical synchronization control circuit 315, and various synchronization processing circuits (not shown).

The reproduced horizontal synchronizing signal HREF generated by the nFh clock generating circuit 311 is first supplied to the timing generating circuit 303 to generate a timing signal CBFP indicating the phase of the burst signal in the input video signal, and the burst separating circuit 304. Is given to. The reproduction horizontal synchronizing signal HREF is also given to the horizontal synchronizing control circuit 313, and the horizontal synchronizing control circuit 313 generates a signal HD for controlling the horizontal position of the TV screen based on the signal HREF.
This signal HD is output from the terminal 316. further,
The output signal of the A / D converter 310 is the vertical sync separation circuit 3
Then, the vertical synchronizing signal is extracted from the digital video signal. The extracted vertical synchronization signal is supplied to the vertical synchronization control circuit 315 together with the reproduction horizontal synchronization signal HREF. In the vertical synchronization control circuit 315, the signal HREF
A signal VD for controlling the vertical position of the TV screen is generated on the basis of the vertical synchronizing signal separated from the signal VD, and this signal VD is output from the terminal 317.

[0015]

As described above, in a digital signal processing type TV receiver, when operating with a clock phase-synchronized with the above-mentioned color carrier, the color carrier represented by (Equation 1) is used. It is necessary to process signals that deviate from the relationship between the frequency Fsc and the horizontal synchronizing frequency Fh. In order to deal with this, it is necessary for the synchronization processing circuit to operate with a clock that is phase-synchronized with the horizontal synchronization signal different from the color carrier. Therefore, as described above, the TV receiver using the digital signal processing method requires the A / D converter for video processing and for synchronization processing independently of the video processing. As described above, the need for a plurality of A / D converters to process one signal is inefficient and is a major negative factor in terms of cost.

The present invention has been made to solve the above problems, and a digital video signal processing circuit in which an A / D converter for video processing and an A / D converter for synchronization processing are shared. Is intended to provide.

[0017]

A digital video signal processing circuit according to the present invention includes at least two or more sampling clock generating means for A / D conversion of an A / D converter, and a process for processing these clocks. And a means for switching and supplying to the A / D converter.

Specifically, the sampling clock generating means is characterized by having at least a clock generating means phase-synchronized with the color carrier and a clock generating means phase-synchronized with the horizontal synchronizing signal.

In addition, in the digital video signal processing circuit which performs A / D conversion of the analog video signal compatible with SVHS by the A / D converter for Y and the A / D converter for C, and then digitally processes it, the phase is synchronized with the horizontal synchronizing signal. Synchronized clock generation means, clock generation means phase-synchronized with the color carrier, and A / Y for Y at least during the synchronization period of the video signal.
The clock from the clock generating means synchronized with the horizontal synchronizing signal is supplied to the D converter for the A / D for C at least during the burst period.
The converter is provided with means for supplying the clocks from the clock generation means synchronized with the color carrier waves as sampling clocks.

Further, for the Y A / D converter, the clock from the clock generating means that is phase-synchronized with the horizontal synchronizing signal at least during the synchronizing period of the video signal, and the clock generating means that is synchronized with the color carrier wave at least during the video period. It is also characterized in that it has means for switching and supplying the respective clocks as sampling clocks.

Further, the clock generating means which is phase-synchronized with the horizontal synchronizing signal generates a clock which is synchronized with the horizontal synchronizing signal based on the output signal of the A / D converter for Y, and the clock generating means which is synchronized with the color carrier wave is It is also characterized in that each means is provided for generating a clock synchronized with the color carrier wave based on the output signal of the C A / D converter.

[0022]

With this configuration, the A / D converter is provided for a necessary period, for example, a synchronizing signal period for a video signal and a video signal period for A / D conversion of a video signal. It is designed to be shared during the period.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A is a block circuit showing the configuration of the first embodiment. Further, FIG. 2B is an analog video signal, and FIG. 1C is a signal waveform diagram for switching the CK for the A / D converter of the embodiment. Hereinafter, this embodiment will be described with reference to these drawings.

An analog video signal input from the terminal 1 is applied to an A / D converter 2 for converting it into a digital signal, and converted into a digital signal using a clock signal supplied from the selection circuit 3 as a sampling reference. ..

The selection circuit 3 receives the timing signal CKS given from the timing generation circuit 4 as shown in FIG.
, The sampling clock for the A / D converter 2 is switched to either one of the two clock signals supplied from the mFsc clock generation circuit 5 or the nFh clock generation circuit 6.

As shown in the figure, the timing signal CKS is logically inverted between the synchronizing signal period of the analog video input signal and the period other than this, and the mFsc clock is generated during the "L" period of the video signal including the burst signal. On the contrary, the clock signal supplied from the circuit 5 is switched to the clock signal supplied from the nFh clock generation circuit 6 during the "H" synchronizing signal period and is output to the A / D converter 2 via the selection circuit 3. ..

The digital video signal converted by the A / D converter 2 is input to the burst separation circuit 7 together with the timing signal CBFP sent from the timing generation circuit 4. In this burst separation circuit 7, the timing signal CBF is
With P as a reference, the burst signal which is the reference carrier of the carrier C signal is separated from the digital video signal and sent to the mFsc clock generation circuit 5.

The mFsc clock generation circuit 5 generates a clock signal whose phase is synchronized with the burst signal based on the separated burst signal, and selects this clock signal from the selection circuit 3, the Y / C separation circuit 8 and the color demodulation circuit. 9 and various video processing circuits (not shown).

In the TV receiver of this embodiment, the frequency of the clock signal is usually four times that of the burst signal, that is, 4Fsc.
Are using. Further, the mFsc clock generation circuit 5 generates a signal DFS having the same phase and frequency as the burst signal in order to provide a reference phase when demodulating the C signal amplitude-modulated by the color demodulation circuit 9.

The output signal of the A / D converter 2 is Y / C.
The Y signal and the C signal are supplied to the separation circuit 8 and are separated from the digital video signal, and the separated Y signal is output from the terminal 10. Thereafter, this signal is subjected to contour compensation and the like by a contour compensation circuit not shown in FIG.

For the separated C signal, a signal DF given from the mFsc clock generation circuit 5 in the color demodulation circuit 9
Demodulated based on S. When an analog video signal is sampled at a frequency of 4 Fsc, the terminal 11 has R-
Y / B-Y are obtained alternately every clock. Next, the synchronization signal processing will be described.

First, the video signal given from the terminal 1 is
The digital signal is converted by the A / D converter 2. At this time,
The sampling clock of the A / D converter 2 is shown in FIG.
The sync signal period shown in the "H" state of (c) is given from the nFh clock generation circuit 6, and the sampling operation is performed by this clock signal. The converted digital video signal is supplied to the horizontal sync separation circuit 12, and the horizontal sync signal in the digital video signal is extracted. The nFh clock generation circuit 6 generates a clock signal having a frequency n times phase-locked with the horizontal synchronizing signal based on the separated horizontal synchronizing signal. Further, it outputs a reproduction horizontal synchronizing signal HREF whose phase and frequency are completely the same as those of the horizontal synchronizing signal. The generated nFh clock is used for the horizontal sync control circuit 13, the vertical sync control circuit 14, the horizontal and vertical sync separation circuit 12,
15, it is supplied as a clock to the selection circuit 3 and various synchronization processing circuits (not shown).

The reproduced horizontal synchronizing signal HREF generated by the nFh clock generating circuit 6 is first supplied to the timing generating circuit 4 to generate a timing signal CBFP indicating the phase of the burst signal in the input video signal to generate the burst separating circuit. Giving to 7. Furthermore, "H" in Fig. 1 (c)
A timing signal CKS as shown by "L" is generated and given to the selection circuit 3 as a control signal for circuit switching.

Further, based on the reproduction horizontal synchronizing signal HREF given to the horizontal synchronizing control circuit 13, the horizontal synchronizing control circuit 13 generates a signal HD for controlling the horizontal position of the TV screen, and this signal HD is supplied to the terminal 16 Is output from.

Further, the output signal of the A / D converter 2 is input to the vertical sync separation circuit 15, and the vertical sync signal in the digital video signal is extracted. The extracted vertical synchronizing signal is given to the vertical synchronizing control circuit 14 together with the reproduced horizontal synchronizing signal HREF. In the vertical synchronization control circuit 14, the signal H
A signal VD for controlling the vertical position of the TV screen is generated based on the vertical synchronizing signal separated from REF, and this signal VD is generated.
D is output from the terminal 17.

That is, in the present embodiment, since the synchronizing signal and the video signal are temporally divided in the television signal, the sampling clock of the A / D converter 2 is switched according to each period. The A / D converter 2 is used for both synchronous processing and video processing.

In recent years, the Y signal and the C signal have begun in the VTR.
Video equipment that outputs SVHS signals that handle signals independently by different signal systems has also become widespread. Figure 2 is this SV
The 2nd Example of this invention in the digital TV receiver corresponding to a HS signal is shown.

FIG. 2 (a) shows a block circuit showing the configuration of this embodiment, FIG. 2 (b) shows an analog video signal, and FIG. 2 (c) shows the A / D converter of the same embodiment. It is a signal waveform diagram for switching. Hereinafter, this embodiment will be described with reference to these drawings.

The video signal input to the terminal 201 is A
It is given to the / D converter 202 and the selection circuit 203. In the selection circuit 203, when a normal video signal is input, a video signal input from the terminal 201 is input, and when an SVHS signal is input, an SVHS-C signal input from the terminal 204 is input according to the input signal mode. Select.

The output signal of the selection circuit 203 is the BPF 20.
The frequency band is limited only to the frequency component near Fsc where the C signal is present. The signal band-limited by the BPF 205 is converted into a digital signal by the A / D converter 206. At this time, the sampling clock of the A / D converter 206 is always given from the mFsc clock generation circuit 207 regardless of the video / synchronization period.

The converted digital video signal is supplied with the timing signal CBF from the timing generation circuit 208.
It is input to the burst separation circuit 209 together with P. The burst separation circuit 209 separates the burst signal, which is the reference carrier of the carrier C signal, from the digital video signal with reference to the timing signal CBFP, and sends the separated burst signal to the mFsc clock generation circuit 207.

The mFsc clock generation circuit 207 generates a clock signal whose phase is synchronized with the burst signal based on the sent burst signal, and selects this clock from the selection circuit 21.
0, Y / C separation circuit 211, color demodulation circuit 212 and various image processing circuits not shown.

In the TV receiver of this embodiment, the frequency of the clock signal is four times that of the normal burst signal, that is, 4Fsc.
Are using. Further, the mFsc clock generation circuit 20
7, the signal DFS having the same phase and the same frequency as the burst signal is generated in order to provide a reference phase when demodulating the C signal amplitude-modulated by the color demodulation circuit 212.

On the other hand, the video signal supplied from the terminal 201 is converted into a digital signal in the A / D converter 202 using the clock signal supplied from the selection circuit 210 as a sampling reference.

In the selection circuit 210, the sampling clock for the A / D converter 202 is set to the mFsc clock depending on the "H" or "L" state of the timing signal CKS supplied from the timing generation circuit 208 as shown in FIG. 2 (c). Generating circuit 207 or nFh clock generating circuit 211
The clock signal is switched to one of the two clock signals given by

As shown in the figure, CKS is logically inverted in the synchronizing signal period and the period other than the synchronizing signal period and is in the "L" period, that is, at least the video signal period, the clock signal provided from the mFsc clock generation circuit 207 "H"
The sync signal period indicated by the state is nFh clock generation circuit 2
A clock signal given from the A / D converter 202
Is output to.

The digital video signal converted by the A / D converter 202 is applied to the horizontal sync separation circuit 214, the horizontal sync signal in the digital video signal is extracted, and nFh
It is sent to the clock generation circuit 213.

The nFh clock generation circuit 213 generates a clock signal having a frequency of n times as well as being phase-synchronized with the horizontal synchronizing signal based on the separated horizontal synchronizing signal. Further, a signal HREF whose phase and frequency completely match the horizontal synchronizing signal is output as a reproduction horizontal synchronizing signal. The generated nFh clock is supplied to the horizontal sync control circuit 215, the vertical sync control circuit 216, the horizontal and vertical sync separation circuit 21.
4, 217 and the selection circuit 210 are supplied to various synchronous processing circuits not shown.

The reproduced horizontal synchronizing signal HREF generated by the nFh clock generating circuit 213 is first supplied to the timing generating circuit 208 to generate the timing signal CBFP indicating the phase of the burst signal in the input video signal, and the burst separating circuit 209. Is given to. Further, a timing signal CKS as shown by "H" and "L" in FIG. 3 (c) is generated and given to the selection circuit 210 as a control signal for circuit switching.

The reproduction horizontal synchronizing signal HREF is also given to the horizontal synchronizing control circuit 215. The horizontal synchronization control circuit 215 generates a signal HD for controlling the horizontal position of the TV screen on the basis of the signal HREF.
Is output from the terminal 218.

Further, the output signal of the A / D converter 202 is also input to the vertical sync separation circuit 217, and the vertical sync signal in the digital video signal is extracted. The extracted vertical synchronizing signal is given to the vertical synchronizing control circuit 216 together with the reproduction horizontal synchronizing signal HREF. Vertical synchronization control circuit 21
In 6, the signal VD for controlling the vertical position of the TV screen is generated with reference to the vertical synchronizing signal separated from the signal HREF, and this signal VD is output from the terminal 219.

The output signal of the A / D converter 202 is Y
It is supplied to the / C separation circuit 211 and separates the Y signal and the C signal from the digital video signal. The separated Y signal is output from the terminal 220, and thereafter, in a contour compensation circuit not shown in FIG. 2, contour compensation or the like is performed.

The separated C signal is sent to the selection circuit 221. According to the input mode, the selection circuit 221 obtains the C signal sent from the Y / C separation circuit 211 in the case of a video signal and the C signal obtained by the A / D converter 206 independently of the Y signal when the SVHS signal is input. The signal is selected and given to the color demodulation circuit 212. Then, the color demodulation circuit 3-10 demodulates the signal DFS given from the mFsc clock generation circuit 207 as a reference. When an analog video signal is sampled at 4Fsc, the terminal 222 has R-
Y / B-Y are obtained alternately every clock.

In the above-described embodiment of the SVHS compatible digital signal processing TV receiver shown in FIG. 2, SVHS-Y is used.
A / D converters for SVHS-C and SVHS-C are required independently, but a clock phase-synchronized with the color carrier is used for SVHS-C.
By generating it based on the digital video signal obtained from the A / D converter 206 for C, the sampling clock of the A / D converter 202 for SVHS-Y can be used as a horizontal clock with a clock phase-synchronized with the color subcarrier. A clock that is phase-synchronized with the synchronization signal is used by switching between a synchronization period and a period other than that. As a result, another A for synchronization processing is used.
Digital sync signal processing can be realized without the need for a / D converter. The present invention is not limited to the above-mentioned embodiments, and can be modified and carried out without changing the gist.

[0056]

As described above, according to the present invention, the A / D converter for synchronization processing, which has been conventionally required independently, can be shared with the A / D converter for video processing, and the cost can be reduced. It becomes possible to realize the digital synchronization signal processing of.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of a first embodiment of a digital video signal processing circuit of the present invention.

FIG. 2 is a block circuit diagram showing a configuration of a second embodiment of a digital video signal processing circuit.

FIG. 3 is a block circuit diagram illustrating video signal processing of a conventional digital TV.

[Explanation of symbols]

1,201,303… Terminal (input) 2,202,206,302,31
o ... A / D converter 3,203,210,221 ... Selection circuit 4,208,303 ... Timing generation circuit 5,207,305 ... mFsc clock generation circuit 6,213,311 ... nFh clock generation circuit 7,209,304 ... Burst separation circuit 8,211,306 ... Y /
C separation circuit 9,212,307 ... color demodulation circuit 10,220,308 ... terminal (Y) 11,222,309 ... terminal (RY / BY) 12,214,312 ... horizontal synchronization separation circuit 13,215,313 ... horizontal synchronization control circuit 14,216,315 ... vertical synchronization control circuit 15,217,314 ... vertical synchronization separation circuit 16,218,317 ... terminal ( HD) 17,219,317… Terminal (VD) 204 ………… Terminal (SVHS-C) 205 ………… BPF

Claims (5)

[Claims] 1. A digital video signal processing circuit for A / D converting an analog video signal by an A / D converter and thereafter digitally processing it. At least two or more samplings for A / D conversion of the A / D converter. A digital video signal processing circuit comprising: clock generating means and means for switching and supplying these clocks to an A / D converter in a processing process. 2. The digital video signal according to claim 1, wherein the sampling clock generating means includes at least a clock generating means phase-synchronized with the color carrier and a clock generating means phase-synchronized with the horizontal synchronizing signal. Processing circuit. 3. An SVHS compatible analog video signal is converted into an A / D converter for Y and an A / D converter for C respectively.
In a digital video signal processing circuit for performing digital processing after D / D conversion, a clock generation means phase-synchronized with a horizontal synchronization signal, a clock generation means phase-synchronized with a color carrier, and an A / D for Y for at least a synchronization period of a video signal Means for supplying a clock from the clock generating means synchronized with the horizontal synchronizing signal to the converter, and means for supplying the clock from the clock generating means synchronized with the color carrier to the C / A converter at least during the burst period as sampling clocks. A digital video signal processing circuit provided with. 4. A clock from a clock generating means which is phase-synchronized with a horizontal synchronizing signal for at least a synchronizing period of a video signal for the Y A / D converter, and a clock generating means which is synchronized with a color carrier for at least a video period. 4. The digital video signal processing circuit according to claim 3, further comprising means for switching and supplying each of the clocks as sampling clocks. 5. A clock generator which is phase-synchronized with the horizontal synchronizing signal generates a clock which is synchronized with the horizontal synchronizing signal based on the output signal of the Y A / D converter, and a clock generator which is synchronized with the color carrier is 5. The digital video signal processing circuit according to claim 3, further comprising respective means for generating a clock synchronized with a color carrier wave based on the output signal of the C A / D converter.