JPH03207189A - Video signal recording and reproducing device - Google Patents

Video signal recording and reproducing device

Info

Publication number
JPH03207189A
JPH03207189A JP2002363A JP236390A JPH03207189A JP H03207189 A JPH03207189 A JP H03207189A JP 2002363 A JP2002363 A JP 2002363A JP 236390 A JP236390 A JP 236390A JP H03207189 A JPH03207189 A JP H03207189A
Authority
JP
Japan
Prior art keywords
signal
memory
circuit
signals
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002363A
Other languages
Japanese (ja)
Inventor
Takuya Otsuki
卓也 大槻
Shigeru Ogata
緒方 茂
Masao Tomita
冨田 雅夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002363A priority Critical patent/JPH03207189A/en
Publication of JPH03207189A publication Critical patent/JPH03207189A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To correct time base variation substantially in all modes by writing a video signal in a memory through a digital processing system in synchronism with an input horizontal and a vertical synchronizing signal and reading it out with a fixed clock. CONSTITUTION:A conversion controller 52 controls a decoder circuit 33, a memory control circuit 51, signal selection switches 40 and 42, and an encoder circuit 44 so as to perform specific television conversion corresponding to the system of a television signal inputted from an input terminal 31 and a specific television system. Thus, the signal is digitized in all the operation modes and processed through the memory, so a difference in delay time among the respective modes and a deviation in timing between a brightness signal and a color signal are eliminated. Further, the signal is written in the memory with a clock which is phase-locked to the synchronizing signals of the input signal in synchronism with the synchronizing signals and read out at a constant period with the clock of fixed frequency, so the time base variation of the input signal can be reduced in each mode.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、あるテレビジョン方式信号を別のテレビジョ
ン方式信号に変換して記録または再生することのできる
映像信号記録再生装置に関するものである. 従来の技術 第2図にテレビジョン方式の変換が可能な従来の映像信
号記録再生装置の主要部の構成の一例を示す。第2図に
おいて、lは方式変換回路部の入力端子であり、映像信
号などが入力される。YC分離回路2は入力端子1に接
続され、複合映像信号を輝度信号と搬送色信号に分離す
る。YC分離回路2に接続されるデコーダ回路3は搬送
色信号を色差信号に復調する。デコーダ回路3に接続さ
れるマルチプレクサ(MPX)4はR−YとB−Yの2
つの色差信号を時分割に切り換え多重する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal recording and reproducing apparatus that can convert one television system signal into another television system signal and record or reproduce the converted television system signal. 2. Description of the Related Art FIG. 2 shows an example of the configuration of the main parts of a conventional video signal recording and reproducing apparatus capable of converting television formats. In FIG. 2, 1 is an input terminal of the system conversion circuit section, into which video signals and the like are input. A YC separation circuit 2 is connected to the input terminal 1 and separates the composite video signal into a luminance signal and a carrier color signal. A decoder circuit 3 connected to the YC separation circuit 2 demodulates the carrier color signal into a color difference signal. The multiplexer (MPX) 4 connected to the decoder circuit 3 has two R-Y and B-Y
The two color difference signals are switched and multiplexed in a time-division manner.

YC分離回跡2に接続されるA/D変換器5は輝度信号
をディジタル信号に変換する。また、マルチプレクサ4
に接続されるA/D変換器6は時分割多重された色差信
号をディジタル信号に変換する.A/D変換器5,6が
それぞれ接続されるメモリ7はデジタル信号を記憶する
6メモリ7に接続される輝度信号走査線補間回路8は輝
度信号の走査線補間を行う。また、メモリ7に接続され
る色差信号走査線補間回路9は色差信号の走査線補間を
行う。輝度信号走査線補間回路8に接続されるD/A変
換器10は輝度信号をアナログ信号に戻す。色差信号走
査線補間回路9に接続されるD/A変換器11は色差信
号をアナログ信号に戻す。信号選択スイソチ】2はYC
分離回路2.D/A変換器10およびYC混合回路】3
に接続され、YC分離回路2の輝度信号出力とD/A変
換器10のm度信号出力とを切り換えて、YC混合回路
13に出力する。また、信号選択スイッチ14はデコー
ダ回路3、D/A変換器11およびエンコーダ回路15
に接続され、デコーダ回路3の色差信号出力とD/A変
換器j1の色差信号出力を切り換えて、エンコーダ回路
15に出力する。エンコーダ回路15は色差信号を搬送
色信号に変換する。YC混合回路13は信号選択スイッ
チ】2およびエンコーダ回路15に接続され、輝度信号
と搬送色信号を混合する。さらに、信号選択スイッチ1
6はYC混合回路13、入力端子1および出力端子17
に接続され、YC混合回路13からの出力信号と入力端
子1の入力信号を切り換えて出力端子17に出力する。
An A/D converter 5 connected to the YC separation circuit 2 converts the luminance signal into a digital signal. Also, multiplexer 4
An A/D converter 6 connected to converts the time-division multiplexed color difference signal into a digital signal. A memory 7 to which the A/D converters 5 and 6 are respectively connected stores digital signals. A luminance signal scanning line interpolation circuit 8 connected to the memory 7 performs scanning line interpolation of the luminance signal. Further, a color difference signal scanning line interpolation circuit 9 connected to the memory 7 performs scanning line interpolation of color difference signals. A D/A converter 10 connected to the luminance signal scanning line interpolation circuit 8 converts the luminance signal back into an analog signal. A D/A converter 11 connected to the color difference signal scanning line interpolation circuit 9 converts the color difference signal back into an analog signal. Signal selection switch] 2 is YC
Separation circuit 2. D/A converter 10 and YC mixing circuit】3
It switches between the luminance signal output of the YC separation circuit 2 and the m degree signal output of the D/A converter 10 and outputs it to the YC mixing circuit 13. Further, the signal selection switch 14 includes a decoder circuit 3, a D/A converter 11, and an encoder circuit 15.
The color difference signal output of the decoder circuit 3 and the color difference signal output of the D/A converter j1 are switched and outputted to the encoder circuit 15. Encoder circuit 15 converts the color difference signal into a carrier color signal. The YC mixing circuit 13 is connected to the signal selection switch 2 and the encoder circuit 15, and mixes the luminance signal and the carrier color signal. Furthermore, signal selection switch 1
6 is a YC mixing circuit 13, input terminal 1 and output terminal 17
, and switches the output signal from the YC mixing circuit 13 and the input signal of the input terminal 1 and outputs it to the output terminal 17.

一方、入力端子1に接続される低域通過フィルタ(LP
F)18は、入力信号の低域周波数或分だけを通過させ
る。低域通過フィルタI8に接続される同期分離回路(
SYNCSEP)19は低域通過フィルタ18で高城成
分が除去された入力信号から水平・垂直同期信号を分離
する。同期分離回路19に接続される書き込み基準クロ
ック発生器20はメモリ7に信号を書き込むための基準
になるクロツクを発生する。読み出し基準クロック発生
器2lはメモリ7から信号を読み出すための基準となる
クロツクを発生する。書き込み基準クロック発生器20
および同期分m回路19と読み出し基準クロツク発生器
21に接続され、メモリ7に接続されるメモリ制御回路
22はメモリ7への信号の書き込みと読み出しを制御す
る。変換制御器23は、メモリ制御回路22に接続され
,また,デコーダ回路3およびエンコーダ回路15に接
続され、さらに,信号選択スイッチ1.2, 14. 
16に接続されて、方式変換の動作を制御する。
On the other hand, a low-pass filter (LP
F) 18 passes only a certain portion of the low frequency of the input signal. A synchronous separation circuit (
SYNCSEP) 19 separates horizontal and vertical synchronization signals from the input signal from which the Takagi component has been removed by the low-pass filter 18. A write reference clock generator 20 connected to the synchronization separation circuit 19 generates a clock serving as a reference for writing signals into the memory 7. The read reference clock generator 2l generates a reference clock for reading signals from the memory 7. Write reference clock generator 20
A memory control circuit 22 connected to the synchronous minute m circuit 19 and the read reference clock generator 21 and to the memory 7 controls writing and reading of signals to the memory 7. Conversion controller 23 is connected to memory control circuit 22, and also to decoder circuit 3 and encoder circuit 15, and further includes signal selection switches 1.2, 14.
16 to control the system conversion operation.

以上のように構成された映像信号記録再生装置について
、以下、その動作を説明する。
The operation of the video signal recording and reproducing apparatus configured as described above will be described below.

まず、入力端子1には、記録モート時に外部入力端子よ
り入力する映像信号あるいはチューナからの映像信号が
入力され、再生モート時に再生映像信号が入力される。
First, to the input terminal 1, a video signal input from an external input terminal or a video signal from a tuner is inputted when in recording mode, and a reproduced video signal is inputted when in playback mode.

テレビジョン信号の方式を変換しない場合には、信号選
択スイッチ]6はb側の信号を選択し、入力端子1に入
力された信号はそのまま出力端子17から出力される。
When the format of the television signal is not converted, the signal selection switch [6] selects the signal on the b side, and the signal input to the input terminal 1 is outputted from the output terminal 17 as it is.

また、テレビジョン信号のフィールド周波数・走査線数
および色信号伝送方式を変換する場合には、信号選択ス
イッチ12, 14. 16はすべてa側の信号を選択
し、入力信号はYC分離回路2で輝度信号と色信号に分
離され、色信号はさらにデコーダ回路3で色差信号に復
調され、マルチプレクサ4でR−YとB−Yの2つの色
差信号が時分割多重されたあと、輝度信号、色信号それ
ぞれA/D変換器5,6でディジタル化されてメモリ7
に書き込まれる。メモリ7に書き込まれた信号はメモリ
制御回路22によりフィールド周波数と走査線数を変換
するように読み出されて走査線補間回路8,9でそれぞ
れ輝度信号と色差信号の走査線補間を行い、その後、D
/A変換器10. 11で輝度信号と色差信号がそれぞ
れD/A変換される。そして、色信号はエンコーダ回路
15で所望の変換搬送色信号に変換されたのち、YC混
合回路13で輝度信号と色信号が混合され、信号選択ス
イッチ16を通り、出力端子17から出力される。
Further, when converting the field frequency, number of scanning lines, and color signal transmission method of a television signal, signal selection switches 12, 14. 16 selects all signals on the a side, the input signal is separated into a luminance signal and a chrominance signal by a YC separation circuit 2, the chrominance signal is further demodulated into a chrominance signal by a decoder circuit 3, and a multiplexer 4 separates R-Y and B. - After the two color difference signals of Y are time-division multiplexed, the luminance signal and the color signal are each digitized by A/D converters 5 and 6 and stored in the memory 7.
will be written to. The signal written in the memory 7 is read out by the memory control circuit 22 so as to convert the field frequency and the number of scanning lines, and the scanning line interpolation circuits 8 and 9 perform scanning line interpolation of the luminance signal and color difference signal, respectively. ,D
/A converter 10. At step 11, the luminance signal and color difference signal are each subjected to D/A conversion. After the color signal is converted into a desired conversion carrier color signal by the encoder circuit 15, the luminance signal and the color signal are mixed by the YC mixing circuit 13, passed through the signal selection switch 16, and outputted from the output terminal 17.

さらに,フィールド周波数・走査線数は変換せず色信号
伝送方式だけを変換する場合には、信号選択スイッチ1
2. 14はb側、信号選択スイッチl6はa側の信号
を選択し、YC分離回路2で分離された輝度信号は信号
選択スイッチ12を通りYC混合器13に送られ,また
,色信号はデコーダ回路3で色差信号に復調されて信号
選択スイッチ14を通り、エンコーダ回路15に送られ
,所望の変換搬送色信号に変換されてYC混合回路13
に送られる。
Furthermore, when converting only the color signal transmission method without converting the field frequency or number of scanning lines, use the signal selection switch 1.
2. 14 selects the signal on the b side, and the signal selection switch l6 selects the signal on the a side.The luminance signal separated by the YC separation circuit 2 is sent to the YC mixer 13 through the signal selection switch 12, and the color signal is sent to the decoder circuit. 3, it is demodulated into a color difference signal, passes through the signal selection switch 14, is sent to the encoder circuit 15, is converted into a desired conversion carrier color signal, and is sent to the YC mixing circuit 13.
sent to.

そして、YC混合回路13で混合された信号は信号選択
スイッチ16を通り出力端子17から出力される。
The signal mixed by the YC mixing circuit 13 passes through the signal selection switch 16 and is output from the output terminal 17.

発明が解決しようとする課題 しかしながら、上記従来の構或では、各変換のモードに
よって信号の経路が異なり、しかも、アナログ処理系と
ディジタル処理系の経路が混在するため、輝度信号と色
信号の遅延時間のタイミングがずれたりタイミングの調
整が煩雑であったりするといった問題を有していた。ま
た、フイールト周波数・走査線数の変換を行うモードで
は入力の水平・垂直同期信号に位相ロックしたクロック
で水平周期毎に信号を書き込み,それを固定のクロック
で読み出すため、実質的に時間軸変動の補正を行うこと
ができるのに対し、それ以外のモード時には、アナログ
処理系を通るため、そうした時間軸変動補正の効果を得
ることができなかった。
Problems to be Solved by the Invention However, in the conventional structure described above, the signal path differs depending on each conversion mode, and moreover, the analog processing system and digital processing system paths coexist, resulting in delays in the luminance signal and chrominance signal. There have been problems such as timing shifts and timing adjustments being complicated. In addition, in the mode that converts the field frequency and the number of scanning lines, a signal is written every horizontal period using a clock that is phase-locked to the input horizontal and vertical synchronization signals, and is read out using a fixed clock, so there is virtually no time axis variation. However, in other modes, the effect of time axis fluctuation correction cannot be obtained because the data passes through an analog processing system.

本発明は上記従来の問題を解決するもので、輝度信号と
色信号の遅延時間のタイミング調整が容易でかつ各モー
ド毎のタイミングのずれが小さく、しかもすべてのモー
ドで実質上時間軸変動補正の効果が得られる映像信号記
録再生装置を提供することを目的とするものである。
The present invention solves the above-mentioned conventional problems. It is easy to adjust the timing of the delay time of the luminance signal and the color signal, and the timing deviation between each mode is small. Moreover, in all modes, time axis fluctuation correction is virtually impossible. It is an object of the present invention to provide a video signal recording and reproducing device that can obtain effects.

課題を解決するための手段 上記課題を解決するために本発明の映像信号記録再生装
置は、テレビジョン方式の変換を行う方式変換回路を備
えた映像信号記録再生装置であって、少なくともテレビ
ジョン信号の1フィールドを記憶できる容量をもつメモ
リと、前記メモリを制御するメモリ制御回路と、前記メ
モリから読み出される隣接した複数ラインの信号から補
間信号を作戒する走査線補間回路と、前記走査線補間回
路で走査線補間される信号かまたは前記メモリから読み
出される信号かを選択する選択スイッチと、テレビジョ
ン方式の変換動作を制御する変換制御手段と、入力信号
から水平・垂直同期信号を分離する同期分離回路と、前
記同期分離回路で分離される同期信号に位相ロツクした
クロツクを発生し、前記メモリ制御回路に出力する書き
込み基準クロノク発生器と、固定周波数のクロックを発
生し、前記メモリ制御回路に出力する読み出し基準クロ
ック発生器とを備え、前記変換制御手段は前記メモリ制
御回路と前記選択スイッチを制御し、フィールド周波数
と走査線数を変換するか否かに関わらずすべての動作モ
ートで前記メモリへの信号の書き込みと前記メモリから
の信号の読み出しを行うように構成したものである。
Means for Solving the Problems In order to solve the above problems, the video signal recording and reproducing device of the present invention is a video signal recording and reproducing device that is equipped with a format conversion circuit that converts television formats, and that is capable of converting at least a television signal. a memory having a capacity to store one field, a memory control circuit for controlling the memory, a scanning line interpolation circuit for generating an interpolation signal from signals of a plurality of adjacent lines read from the memory, and a scanning line interpolation circuit for generating an interpolation signal from signals of adjacent lines read from the memory; a selection switch for selecting a signal interpolated by scanning lines in the circuit or a signal read from the memory; a conversion control means for controlling the conversion operation of the television system; and a synchronizer for separating horizontal and vertical synchronization signals from the input signal. a separation circuit; a write reference clock generator that generates a clock phase-locked to the synchronization signal separated by the synchronization separation circuit and outputs it to the memory control circuit; and a write reference clock generator that generates a fixed frequency clock and outputs it to the memory control circuit. a readout reference clock generator for outputting a readout reference clock, and the conversion control means controls the memory control circuit and the selection switch to output the memory in all operating modes regardless of whether or not the field frequency and number of scan lines are converted. The memory is configured to write signals to and read signals from the memory.

作用 上記構成によって、テレビジョン信号の変換を行わない
モートをも含むすべてのモードでデイジタル処理系を通
り、このため輝度信号と色信号の遅延時間のずれが生じ
にくく調整も容易であり、しかも、入力の水平・垂直同
期信号に同期してメモリに書き込みそれを固定のクロツ
ク゛で読み出すため、全てのモードで実質的に時間軸変
動補正を行うことが可能となる。
Effects With the above configuration, all modes, including modes that do not convert television signals, pass through the digital processing system, so that the delay time difference between the luminance signal and color signal is unlikely to occur, and adjustment is easy. Since it is written into the memory in synchronization with the input horizontal and vertical synchronizing signals and read out with a fixed clock, it is possible to substantially correct time axis fluctuations in all modes.

実施例 以下、本発明の一実施例について図面を参照しながら説
明する。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の映像信号記録再生装置の主
要部の構成を示すブロック図である。第1図において、
31は方式変換回路部の入力端子であり、映像信号など
が入力される。YC分離回路32は入力端子31に接続
され、複合映像信号を輝度信号と搬送色信号に分離する
。YC分離回路32に接続されるデコーダ回路33は搬
送色信号を色差信号に復調する。デコーダ回路33に接
続されるマルチプレクサ(MPX)34はR−YとB−
Yの2つの色差信号を時分割に切り換え多重する。YC
分離回路2に接続されるA/D変換器35は輝度信号を
デイジタル信号に変換する。また,マルチプレ?サ34
に接続されるA/D変換器36は時分割多重された色差
信号をディジタル信号に変換する.A/D変換器35.
 36がそれぞれ接続されるメモリ37はディジタル信
号を記憶する。メモリ37に接続■される輝度信号走査
線補間回路38は輝度信号の走査線補間を行う。また、
メモリ37に接続される色差信号走査線補間回路39は
色差信号の走査線補間を行う。方式変換のモードを切り
換えるための信号選択スイッチ40はメモリ37と輝度
信号走査線補間回路38の接続点に接続されるとともに
.m度信号走査線補間回路38に接続され、さらに、D
/A変換器4】に接続されて、メモリ37からの輝度信
号出力と輝度信号走査線補間回路38からの輝度信号出
力を切り換えてD/A変換器4lに出力する。また、方
式変換のモードを切り換えるための信号選択スイッチ4
2はメモリ37と色差信号走査線補間回路39の接続点
に接続されるとともに、色差信号走査線補間回路39に
接続され、さらに、D/A変換器43に接続されて、メ
モリ37からの色差信号出力と色差信号走査線補間回路
39からの色差信号出力を切り換えてD/A変換器43
に出力する。D/A変換器41は輝度信号をアナログ信
号に戻す。D/A変換器43は色差信号をアナログ信号
に戻す。D/A変換器43に接続されるエンコーダ回路
44は色差信号を搬送色信号に変換する。D/A変換器
41およびエンコーダ回路44に接続されるYC混合回
路45は輝度信号と搬送色信号を混合する。VC混合回
路45には出力端子46が接続されている。一方、入力
端子31に接続される低域通過フィルタ(LPF)47
は入力信号の低域周波数成分だけを通過させる。
FIG. 1 is a block diagram showing the configuration of the main parts of a video signal recording and reproducing apparatus according to an embodiment of the present invention. In Figure 1,
Reference numeral 31 denotes an input terminal of the system conversion circuit section, into which video signals and the like are input. A YC separation circuit 32 is connected to the input terminal 31 and separates the composite video signal into a luminance signal and a carrier color signal. A decoder circuit 33 connected to the YC separation circuit 32 demodulates the carrier color signal into a color difference signal. A multiplexer (MPX) 34 connected to the decoder circuit 33 has R-Y and B-
The two Y color difference signals are switched and multiplexed in a time-division manner. YC
An A/D converter 35 connected to the separation circuit 2 converts the luminance signal into a digital signal. Also, multiplayer? Sa34
An A/D converter 36 connected to converts the time-division multiplexed color difference signal into a digital signal. A/D converter 35.
Memories 37 to which 36 are connected respectively store digital signals. A luminance signal scanning line interpolation circuit 38 connected to the memory 37 performs scanning line interpolation of the luminance signal. Also,
A color difference signal scanning line interpolation circuit 39 connected to the memory 37 performs scanning line interpolation of color difference signals. A signal selection switch 40 for switching the mode of system conversion is connected to the connection point between the memory 37 and the luminance signal scanning line interpolation circuit 38. m degree signal scanning line interpolation circuit 38;
/A converter 4], the luminance signal output from the memory 37 and the luminance signal output from the luminance signal scanning line interpolation circuit 38 are switched and output to the D/A converter 4l. In addition, a signal selection switch 4 for switching the mode conversion mode is also provided.
2 is connected to the connection point between the memory 37 and the color difference signal scanning line interpolation circuit 39, is connected to the color difference signal scanning line interpolation circuit 39, and is further connected to the D/A converter 43, and is connected to the connection point between the memory 37 and the color difference signal scanning line interpolation circuit 39. The D/A converter 43 switches between the signal output and the color difference signal output from the color difference signal scanning line interpolation circuit 39.
Output to. The D/A converter 41 converts the luminance signal back into an analog signal. The D/A converter 43 converts the color difference signal back into an analog signal. An encoder circuit 44 connected to the D/A converter 43 converts the color difference signal into a carrier color signal. A YC mixing circuit 45 connected to the D/A converter 41 and the encoder circuit 44 mixes the luminance signal and the carrier color signal. An output terminal 46 is connected to the VC mixing circuit 45 . On the other hand, a low pass filter (LPF) 47 connected to the input terminal 31
passes only the low frequency components of the input signal.

低域通過フィルタ47に接続される同期分離回路(SY
NCSEP)4Bは低域通過フィルタ47で高城成分が
除去された入力信号から水平・垂直同期信号を分離する
。同期分離回路48に接続される書き込み基準クロツク
発生器49はメモリ37に信号を書き込むための基準に
なるクロックを発生する。
A synchronous separation circuit (SY
NCSEP) 4B separates horizontal and vertical synchronizing signals from the input signal from which the Takagi component has been removed by a low-pass filter 47. A write reference clock generator 49 connected to the synchronization separation circuit 48 generates a reference clock for writing signals into the memory 37.

読み出し基準クロック発生器50はメモリ37から信号
を読み出すための基準となるクロックを発生する。同期
分離回路48および書き込み基準クロック発生器49と
読み出し基準クロツク発生器50に接続され、メモリ3
7に接続されるメモリ制御回路5lは、メモリ37への
書き込みと読み出しを制御する。デコーダ回路33およ
びエンコーダ回路44に接続され、また、信号選択スイ
ッチ40. 42に接続され,さらに、メモリ制御回路
51に接続される変換制御器52は方式変換の動作を制
御する。
A read reference clock generator 50 generates a reference clock for reading signals from the memory 37. The memory 3 is connected to a synchronization separation circuit 48, a write reference clock generator 49, and a read reference clock generator 50.
A memory control circuit 5l connected to the memory 37 controls writing to and reading from the memory 37. The signal selection switch 40 .is connected to the decoder circuit 33 and the encoder circuit 44 . 42 and further connected to the memory control circuit 51, a conversion controller 52 controls the system conversion operation.

以上のように構成された映像信号記録再生装置について
,以下、その動作を説明する。
The operation of the video signal recording and reproducing apparatus configured as described above will be described below.

まず、入力端子3lには記録モード時に外部入力端子よ
り入力する映像信号あるいはチューナからの映像信号が
入力され、再生モード時に再生映像信号が入力される。
First, a video signal input from an external input terminal or a video signal from a tuner is inputted to the input terminal 3l in the recording mode, and a reproduced video signal is inputted in the playback mode.

テレビジョン信号を変換しない場合には、信号選択スイ
ッチ40. 42はb側の信号を選択し、入力信号はY
C分離回路32で輝度信号と色信号に分離され、色信号
はさらにデコーダ回路33で色差信号に復調されてマル
チプレクサ34でR−YとB−Yの2つの色差信号が時
分割多重されたあと、輝度信号、色信号それぞれA/D
変換器35. 36でディジタル化され、メモリ37に
書き込まれる。メモリ37に書き込まれた信号はメモリ
制御回路5lでフィールド周波数・走査線数は変換せず
に読み出され、輝度信号は信号選択スイッチ40を通り
、色差信号は信号選択スイッチ42を通ってそれぞれD
/A変換器41. 43でD/A変換される。そして色
差信号はエンコーダ回路44でもとの搬送色信号に再変
換した後、yc混合回路45で輝度信号と色信号が混合
された出力端子46から出力される。
If you do not want to convert the television signal, press the signal selection switch 40. 42 selects the signal on the b side, and the input signal is Y
The C separation circuit 32 separates the luminance signal and the chrominance signal, the chrominance signal is further demodulated into a chrominance signal by the decoder circuit 33, and the multiplexer 34 time-division multiplexes the two chrominance signals R-Y and B-Y. , luminance signal, color signal each A/D
Converter 35. It is digitized at 36 and written to memory 37. The signal written in the memory 37 is read out by the memory control circuit 5l without converting the field frequency or the number of scanning lines, the luminance signal passes through the signal selection switch 40, and the color difference signal passes through the signal selection switch 42, and is read out by the memory control circuit 5l.
/A converter 41. D/A conversion is performed at 43. The color difference signal is then reconverted into the original carrier color signal by an encoder circuit 44, and then outputted from an output terminal 46 where the luminance signal and color signal are mixed by a YC mixing circuit 45.

また、テレビジョン信号のフィールド周波数・走査線数
および色信号伝送方式を変換する場合には、信号選択ス
イッチ40. 42はa側の信号を選択し、入力信号は
yc分離回路32で輝度信号と色信号に分離され、色信
号はさらにデコーダ回路33で色差信号に復調され、マ
ルチプレクサ34でR−YとB−Yの2つの色差信号が
時分割多重されたあと、輝度信号、色信号それぞれA/
D変換器35,36でディジタル化され、メモリ37に
書き込末れる。
Further, when converting the field frequency, number of scanning lines, and color signal transmission method of the television signal, the signal selection switch 40. 42 selects the signal on the a side, the input signal is separated into a luminance signal and a color signal by the yc separation circuit 32, the color signal is further demodulated into a color difference signal by the decoder circuit 33, and the multiplexer 34 separates R-Y and B- After the two color difference signals of Y are time-division multiplexed, the luminance signal and the color signal are respectively A/
The data is digitized by D converters 35 and 36 and written into memory 37.

メモリ37に書き込まれた信号はメモリ制御回路51に
より、フィールド周波数と走査線数を変換するよう読み
出され、走査線補間回路38. 39でそれぞれ輝度信
号と色差信号の走査線補間を行い、D/A変換器4],
43で輝度信号と色差信号がそれぞれD/A変換される
。そして色信号はエンコーダ回路44で所望の変換搬送
色信号に変換されたのち、YC混合回路45で輝度信号
と色信号が混合されて出力端子46から出力される。
The signal written in the memory 37 is read out by the memory control circuit 51 to convert the field frequency and the number of scanning lines, and is sent to the scanning line interpolation circuit 38. 39 performs scanning line interpolation of the luminance signal and color difference signal, respectively, and the D/A converter 4],
At step 43, the luminance signal and color difference signal are each subjected to D/A conversion. The color signal is converted into a desired conversion carrier color signal by an encoder circuit 44, and then a luminance signal and a color signal are mixed by a YC mixing circuit 45 and outputted from an output terminal 46.

さらに,フィールド周波数・走査線数は変換せず色信号
伝送方式だけを変換する場合には、信号選択スイッチ4
0. 42はb側の信号を選択し、入力信号はYC分離
回路32で輝度信号と色信号に分離され色信号はさらに
デコーダ回路33で色差信号に復調され、マルチプレク
サ34でR−YとB−Yの2つの色差信号が時分割多重
されたあと、輝度信号、色信号それぞれA/D変換器3
5, 36でディジタル化され、メモリ37に書き込ま
れる。メモリ37に書き込まれた信号はメモリ制御回路
51でフィールト周波数・走査線は変換せずに読み出さ
れ、輝度信号は信号選択スイソチ40を通り、色差信号
は信号選択スイソチ41を通って、それぞれD/A変換
器4I,43でD/A変換される。そし,て色差信号は
エンコーダ回路44で所望の変換搬送色信号に変換され
た後、yc混合回路43で輝度信号と色信号が混合され
、出力端子46から出カされる。
Furthermore, when converting only the color signal transmission method without converting the field frequency or number of scanning lines, use the signal selection switch 4.
0. 42 selects the b side signal, the input signal is separated into a luminance signal and a color signal by a YC separation circuit 32, the color signal is further demodulated into a color difference signal by a decoder circuit 33, and a multiplexer 34 separates R-Y and B-Y. After the two color difference signals are time-division multiplexed, the luminance signal and the color signal are each sent to an A/D converter 3.
The data is digitized at 5 and 36 and written into memory 37. The signals written in the memory 37 are read out by the memory control circuit 51 without converting the field frequency and scanning line, the luminance signal passes through the signal selection switch 40, and the color difference signal passes through the signal selection switch 41, and is then read out by the memory control circuit 51. D/A conversion is performed by /A converters 4I and 43. Then, the color difference signal is converted into a desired conversion carrier color signal by an encoder circuit 44, and then a luminance signal and a color signal are mixed by a YC mixing circuit 43 and outputted from an output terminal 46.

変換制御器52は入力端子31から入力されるテレビジ
ョン信号の方式と出力端子46から出カされるテレビジ
ョン信号の方式に応じて前述した各場合に対応して所定
のテレビジョン方式の変換が行われるように、デコーダ
回路33とメモリ制御回路51と信号選択スイッチ40
. 42とエンコーダ回路44を制御する。
The conversion controller 52 converts a predetermined television system in accordance with the format of the television signal input from the input terminal 31 and the format of the television signal output from the output terminal 46 in accordance with each of the above-mentioned cases. The decoder circuit 33, the memory control circuit 51 and the signal selection switch 40
.. 42 and an encoder circuit 44.

以上、説明したように、テレビジョン方式の変換を行わ
ないモードをも含むすべての動作モードで一旦信号をデ
ィジタル化し、メモリを経由して信号を処理するため、
各モード毎での遅延時間が異なったり輝度信号と色信号
のタイミングがずれるということがなく、また,メモリ
への書き込みは入力信号の同期信号に位相ロックしたク
ロツクで同期信号に同期して行い、読み出しは固定周波
数のクロックで一定周期で行うため、各モードで入力信
号の時間軸変動を軽減することができる6信号選択スイ
ノチ40. 41では走査線補間回路38,39で走査
線補間される信号かメモリ37かG読み出される信号か
を選択して切り換えるが、この部分はデイジタル処理部
であるため両経路における遅延時間を合わせることは容
易である。
As explained above, in all operating modes, including modes that do not convert television formats, the signal is first digitized and then processed via memory.
There is no difference in delay time for each mode, and there is no difference in the timing of the luminance signal and color signal, and writing to the memory is performed in synchronization with the synchronization signal using a clock that is phase-locked to the synchronization signal of the input signal. Since reading is performed at a constant cycle using a fixed frequency clock, 6-signal selection switch 40. can reduce time axis fluctuations of input signals in each mode. 41, the scanning line interpolation circuits 38 and 39 select and switch between the signal interpolated by the scanning line and the signal read out from the memory 37, but since this part is a digital processing section, it is not possible to match the delay times in both paths. It's easy.

発明の効果 以上のように本発明によれば、テレビジョン信号の変換
を行わないモードをも含むすべての動作モードで、信号
の遅延時間および輝度信号と色信号の遅延時間がずれる
ことがなく、また各モード毎の遅延時間の調整も容易で
,しかも各モードで入力信号の時間軸変動を軽減するこ
とができるといったすぐれた効果を得ることができる。
Effects of the Invention As described above, according to the present invention, the signal delay time and the delay time of the luminance signal and color signal do not deviate in all operating modes, including modes in which television signal conversion is not performed. Further, it is easy to adjust the delay time for each mode, and it is possible to obtain excellent effects such as being able to reduce time axis fluctuations of the input signal in each mode.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における映像信号記録再生装
置の主要部の構成を示すブロック図、第2図は従来の映
像信号記録再生装置の主要部の構戊を示すブロック図で
ある。 37・メモリ,38・・輝度信号走査線補間回路、39
色差信号走査線補間回路、40. 42一信号選択スイ
ンチ、48・・・同期分離回路、49・・・書き込み基
準クロック発生器. 50・・・読み出し基準クロック
発生器、51・・メモリ制御回路、52・・変換制御器
FIG. 1 is a block diagram showing the configuration of the main parts of a video signal recording and reproducing apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the structure of the main parts of a conventional video signal recording and reproducing apparatus. 37. Memory, 38... Luminance signal scanning line interpolation circuit, 39
Color difference signal scanning line interpolation circuit, 40. 42 - signal selection switch, 48... synchronization separation circuit, 49... write reference clock generator. 50... Read reference clock generator, 51... Memory control circuit, 52... Conversion controller.

Claims (1)

【特許請求の範囲】[Claims] 1、テレビジョン方式の変換を行う方式変換回路を備え
た映像信号記録再生装置であって、少なくともテレビジ
ョン信号の1フィールドを記憶できる容量をもつメモリ
と、前記メモリを制御するメモリ制御回路と、前記メモ
リから読み出される隣接した複数ラインの信号から補間
信号を作成する走査線補間回路と、前記走査線補間回路
で走査線補間される信号かまたは前記メモリから読み出
される信号かを選択する選択スイッチと、テレビジョン
方式の変換動作を制御する変換制御手段と、入力信号か
ら水平・垂直同期信号を分離する同期分離回路と、前記
同期分離回路で分離される同期信号に位相ロックしたク
ロックを発生し、前記メモリ制御回路に出力する書き込
み基準クロック発生器と、固定周波数のクロックを発生
し、前記メモリ制御回路に出力する読み出し基準クロッ
ク発生器とを備え、前記変換制御手段は前記メモリ制御
回路と前記選択スイッチを制御し、フィールド周波数と
走査線数を変換するか否かに関わらずすべての動作モー
ドで前記メモリへの信号の書き込みと前記メモリからの
信号の読み出しを行うように構成した映像信号記録再生
装置。
1. A video signal recording and reproducing device equipped with a format conversion circuit for converting television formats, comprising a memory having a capacity to store at least one field of a television signal, and a memory control circuit for controlling the memory; a scanning line interpolation circuit that creates an interpolation signal from signals of a plurality of adjacent lines read from the memory; and a selection switch that selects between a signal subjected to scanning line interpolation by the scanning line interpolation circuit and a signal read from the memory. , a conversion control means for controlling a conversion operation of a television system, a synchronization separation circuit for separating horizontal and vertical synchronization signals from an input signal, and generating a clock phase-locked to the synchronization signal separated by the synchronization separation circuit, The conversion control means includes a write reference clock generator that outputs to the memory control circuit, and a read reference clock generator that generates a fixed frequency clock and outputs it to the memory control circuit, and the conversion control means controls the memory control circuit and the selection. A video signal recording/reproducing device configured to control a switch to write signals to the memory and read signals from the memory in all operating modes regardless of whether or not the field frequency and number of scanning lines are converted. Device.
JP2002363A 1990-01-09 1990-01-09 Video signal recording and reproducing device Pending JPH03207189A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002363A JPH03207189A (en) 1990-01-09 1990-01-09 Video signal recording and reproducing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002363A JPH03207189A (en) 1990-01-09 1990-01-09 Video signal recording and reproducing device

Publications (1)

Publication Number Publication Date
JPH03207189A true JPH03207189A (en) 1991-09-10

Family

ID=11527176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002363A Pending JPH03207189A (en) 1990-01-09 1990-01-09 Video signal recording and reproducing device

Country Status (1)

Country Link
JP (1) JPH03207189A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107984A (en) * 1996-03-08 2000-08-22 Hitachi, Ltd. Processor of video signal and display unit using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107984A (en) * 1996-03-08 2000-08-22 Hitachi, Ltd. Processor of video signal and display unit using the same

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