JPH0360236B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a video signal digital processing method, and in particular, it is possible to process signals of the NTSC system and PAL system in the same circuit. The present invention relates to a video signal digital processing method that can reduce the scale of a signal processing circuit by using PS (phase shift) processing and decimation processing. (Prior art) In recent years, the method of digitizing and processing video signals has become an excellent method in terms of reducing the number of circuit components (mainly capacitors, resistors, and coils) and eliminating the need for equipment adjustments. Many research and developments related to this have been attempted, and some manufacturers are commercializing it as a "digital television." In addition, the current television broadcasting systems mainly include the NTSC, PAL, and SECAM systems, but the market for the NTSC and PAL systems is especially large, and the color signal multiplexing system is
Compared to the SECAM method, both of these methods have the characteristic of being similar. Therefore, if it were possible to perform signal processing for both the NTSC system and the PAL system using the same (or approximately equivalent) circuit, it would be a great advantage. Furthermore, since there is no major difference in luminance signals between the NTSC and PAL systems except for the frequency band, if the color signal processing circuits are standardized, the NTSC and PAL systems can be used.
It becomes possible to configure the PAL system using the same circuit. (Object of the invention) Therefore, the present invention has been made in view of the above-mentioned prior art, and its object is to provide an NTSC system,
PAL format can be processed in the same circuit,
For example, we provide a video signal digital processing method that can reduce the size of the signal processing circuit by using PS (phase shift) processing as the color signal processing when processing color signals in a magnetic recording/reproducing device (VTR) using digital signal processing. It's about doing. (Means for Solving the Problems) In order to achieve the above object, the present invention changes the sampling frequency when sampling an input analog video signal and converting it into digital data to match the horizontal synchronization of the analog video signal. The frequency is N times the signal frequency (N is an integer), and the integer N is divided by 4 to obtain N=4K+M (K is an integer, M is any number of 0, 1, 2, or 3), and the above-mentioned Divide the integer N by 3 to get N=3L+Q (L is an integer, Q is 0,
+1, -1), P=M+
The integer P represented by Q is set to be an odd number, and 1/3 decimation processing is performed to leave every second sampling point on the time axis as valid data from among the sampled and converted digital data. The present invention provides a video signal digital processing method. (Example) A video signal digital processing method according to the present invention will be described below. Generally, the frequency when sampling an analog video signal and converting it to digital data must be higher than twice the highest frequency included in the analog signal, according to the "sampling theorem", and approximately 10 MHz or higher is usually suitable ( conditions). Furthermore, in order to configure a comb-shaped filter for color signal processing, sample points must be arranged vertically on the screen. In other words, the sampling frequency must be an integral multiple of the horizontal synchronization signal frequency (condition). Furthermore, in the case of the NTSC system, the above-mentioned comb-shaped filter requires a delay circuit (delay line; memory) for one line (horizontal scanning period).
In the case of PAL system, two lines are required, but
The higher the sampling frequency, the more memory that constitutes the filter will be used. Therefore, since the band of the color signal is narrower than that of the luminance signal, it is effective to perform decimation processing. By making the subcarrier (color subcarrier) frequency common between the NTSC system and the PAL system, color signal processing for both systems can be performed using substantially the same circuit. Here, the above conditions and sampling frequencies (fs) that satisfy the conditions are as shown in the following table.

[Table] In the above table, f _H = 15.734265 KHz for NTSC _{system, f H =} 15.625 KHz for PAL system, NTSC system, PAL system at any frequency fs in the table.
Assuming that the composite video signal of each method is sampled, the signals of both methods can be sampled using the same circuit.
For example, in order to separate a luminance signal (Y) and a chrominance signal (C), the subcarrier frequencies of the chrominance signal may be converted so that they become common to each other. By making the above common, the subsequent processing circuits can also be made common. At this time, if the frequency of the subcarrier to be converted is set to 1/4 fs, for example, both DP (differential phase) and DG (differential gain) can be made smaller than when the frequency is set to 1/3 fs. Here, decimation processing, which is one of the digital signal processing methods, will be explained. This decimation process is to leave the sampled data as significant valid data every one, two, three, etc. on the time axis, and change the sampling frequency to 1/2, 1/3, 1 /Four,
...to lower it. In addition, in digital signal processing of video signals, filters are configured depending on various uses.
The higher the sampling frequency, the larger the filter configuration. For example, if a 2H comb filter is applied to a PAL video signal converted into an 8-bit digital signal by sampling at a frequency of 18.00MHz,
A memory of 1152 x 8 bits (=18432 bits) is required. On the other hand, if you perform 1/3 decimation processing (a processing method that leaves every second data and sets the sampling frequency to 1/3, 6.00MHz),
The required memory is 6144 bits, which is 1/3 of the above.
12288 bits can also reduce memory. This number is enough to compensate for the increase in circuitry due to decimation processing. By performing decimation processing in this manner, it is possible to significantly reduce the circuit scale, and it can be said that this has a large impact on cost, power consumption, reliability, etc. When performing the above decimation process, as shown in Figure 2, if the subcarrier is 1/4 of the sampling frequency (fs),
Decimation of 1/2 {shown in Figure 2 a}, that is,
In the operation of validating every other sample point, the signal loops around 1/4 fs, resulting in the signal looping back to the subcarrier itself. Furthermore, in the 1/4 decimation {shown in FIG. 2c}, that is, in the operation of validating every third sample point, the subcarrier component disappears and the signal returns to the baseband, making subsequent signal processing difficult to handle. Therefore, 1/3 decimation processing as shown in FIG. 2b can be considered. In other words, since 1/3 decimation processing folds back at 1/6fs, the signal components do not overlap with the original signal, and the bandwidth is sufficient (±
1/12 fs) and is the most effective. Furthermore, this 1/
The circuit is also reduced to 1/3 by 3 decimation processing. Here, even if 1/3 decimation processing is performed, the frequency at which the sample points for each line (horizontal scanning line) are arranged vertically on the drawing is an integral multiple of 3 of the horizontal synchronizing signal frequency. Only when Otherwise, the sample points for each line (horizontal scanning line) will shift. This is because while the PAL system always has a frequency that is an integral multiple of 3 (in the examples in the table above), this is not necessarily the case with the NTSC system. By the way, in the color signal processing circuit of a magnetic recording/reproducing device (VTR), the phase of the color signal is shifted (transitioned) by 90 degrees for each line (horizontal scanning period) and recorded. In some cases, so-called PS (Phase Shift) processing is used, or in other cases, so-called PI (Phase Invert) processing is used, in which the phase is inverted and recorded on a line-by-line basis. This demodulation can also be performed by digital processing, and can be performed by a frequency converter in a digital signal processing circuit of a digital magnetic recording/reproducing apparatus, which will be described later. In addition, as processing to remove crosstalk from adjacent signal tracks, PS processing or
This is done by demodulating the PI processed data and performing addition processing between two adjacent lines (horizontal scanning lines).
This is because the phase is reversed and canceled by processing or PI processing). In other words, it is a condition for the above-mentioned addition process that the phases be aligned between two adjacent lines. Therefore, if the sample points shift after decimation, the above addition process cannot be performed even if the phases are aligned. In other words, even if the sample points are shifted, as long as the phases match (align), addition processing can be performed. Let's now consider the phase relationship when PS demodulation processing is not performed. First, the sampling frequency fs is an integer N times the horizontal synchronizing signal frequency _fH , and the remainder when dividing the integer N is M (N=4K+M, K is an integer, and M is any number of 0, 1, 2, or 3. )year,
Also, the remainder when dividing the integer N by 3 is Q (N=3L
+Q, L are integers, Q is any number of 0, +1, -1), then P=M+Q (P is also an integer). Figure 3 shows sampling frequency fs=18.00MHz
{=f _H ×1144, M=O (1144=4×286+O), Q=
+1 (1144=3×381+1), P=O+1=1},
The subcarrier frequency is 1/4fs (4.5M
Hz), indicating that there are 286 subcarrier waves in one line. Also, Figure 3a is the nH line, Figure 3b is the (n
+1) H line, Figure 3c shows the (n+262) H line, and in the figure, ● indicates the sampling frequency.
The sample point at 18.00MHz is shown, and the circle indicates the sample point after decimation. In the figure, the nH line in Figure 3a and the (n+1) line in Figure 3b below it are 4.5MHz.
As shown by the thick solid line and the wave ′, the phase is 90° ahead of the line 1H ago. Also, in the figure, the longer wavelength 1.5MHz wave, ′
(thin solid line) is 1/3 decimated and 1.5M
This is a subcarrier folded back to Hz. Also, between the nH line and the (n+1)H line,
4.5MHz wave for PS processing (thick solid line and ′)
The phases of the 1.5MHz waves (thin solid line, ′) are 30° different from each other, while the phases of the 1.5MHz waves (thin solid line, ′) are 90° different from each other. However, the phases of the sample points after decimation in the 1.5MHz wave of both lines are 0°, 90°,
It is the same at 180° and 270°, and the closest points are in the same phase (for example, x point and x' point, y point and y' point, z point and z' point, etc. in the figure). Further, the above phase relationship is the same for (n+262)H, which is the crosstalk component in FIG. 3c. Strictly speaking, the sample points are not arranged vertically, but the time is 56 ns (i.e., 1144 ns on one line).
The difference is only 1/1), so there is no problem as long as the phases match. From the above, it can be seen that even if the sample points are shifted, the phases match, so that crosstalk between two lines can be removed without performing PS demodulation processing. Note that in the PS-processed sample, the direction of phase shift is reversed due to the field. For example, if the field in the above example is the X field and the other field is the Y field, the Y field will have a waveform with a phase shift of 90° in the opposite direction to the waveform in Figure 3b, so the decimation Contrary to the case of the X field, the subsequent phase relationship is such that the phases of the sample points are opposite to each other. Therefore, for example, in order to remove crosstalk components with a comb-shaped filter, instead of performing addition processing with the data of the previous line, by performing subtraction processing, the same effect as in the case of the X field can be obtained. It is easy to understand that this can be obtained. The above was an example when the sampling frequency fs was 18.00MHz, but in general, the subcarrier is set to 1/4fs with respect to the sampling frequency fs, so
The relationship between the number A of waves in one line and its remainder B can be expressed as fs = f _H × 4 × A + B, 3≧B≧0. When the remainder B is not 0, the phase of the subcarrier for each line is 1/ The phase is 4×B×360°.
Adding to that the 90° phase shift due to PS processing, we get
When the remainder B is 1 or 3, the final phase shift is "none" or "opposite phase", and the remainder B is 0.
or 2, the phase shift is "+90°" or "-90°". In addition, the relationship between the number of samples C in one line after decimation and its remainder D can be expressed as fs÷f _H = 3 × C + D, 2≧D≧0.Similarly to the remainder B above, the sampling point is also It shifts by the remainder D each time. By making this remainder D match the above-mentioned remainder B plus the phase shift due to the PS processing, a 1H comb-shaped filter or the like in the above-mentioned PS processing or the like can be constructed. Moreover, even if the remainder D and the above-mentioned remainder B plus the phase shift due to PS processing do not match, if they have an antiphase relationship, the addition of the comb filter can be performed as in the processing of the Y field. By making the circuit a subtraction circuit, a 1H comb filter etc. can be easily constructed. Including the above cases, there is no remainder in the number of waves (that is, one line's subcarrier is an integer multiple of waves),
In addition, if we generalize to the case where the sampling points after decimation do not shift, the sampling frequency can be selected as follows. In other words, "The frequency is N times the horizontal synchronization signal frequency of the analog video signal (N is an integer), and the integer N is divided by 4 to obtain N = 4K + M (K is an integer and M is 0, 1, 2, 3. ) and
Divide the integer N by 3 to get N=3L+Q (L is an integer,
Q is any number of 0, +1, -1), then P
=M+Q, so that the integer P is an odd number. FIG. 1 is a diagram showing an embodiment of a circuit to which the video signal digital processing method of the present invention is applied. The circuit applied to the digital signal processing circuit will be explained below. In the same figure, 1 is an input terminal, a composite video signal is supplied to this input terminal 1, this composite video signal is converted into a digital signal by an AD converter 2, and then its frequency is converted by a frequency converter 3. be done. In this frequency converter 3, during recording,
The frequency is converted from 3.58MHz to 4.5MHz, and during playback, the frequency is converted from 629KHz to 4.5MHz. In addition, the sampling frequency fs at this time is 18.00MHz
shall be. Furthermore, after being subjected to 1/3 decimation (thinning) processing in a decimation processing circuit 5 through a simple band pass filter (BPF) 4 for YC separation, in a digital processing circuit 6,
Digital processing such as ACC (automatic chroma control) and APC (automatic phase control) is performed, and a filter 7 for signal processing and a comb-shaped filter 8 for crosstalk cancellation during playback are used. Then, the interpolation circuit 9 performs a decimation process (interpolation process) opposite to that of the decimation process circuit 5 to restore the decimation. Then, the signal is frequency-converted again by a frequency converter 11 via a bandpass filter (BPF) 10 for interpolation. In this frequency converter 11, the recording time ranges from 4.5MHz to 629KHz.
The frequency is converted to 4.5MHz during playback.
The frequency is converted to 3.58MHz, and PS demodulation processing of the color signal is performed. Finally, it is converted into an analog video signal by the DA converter 12 and output from the output terminal 13. In addition, 14 and 16 are data generation oscillators for supplying data for frequency conversion to the frequency converters 3 and 11, and 15 is a data generation oscillator for supplying data for frequency conversion to the frequency converters 3 and 11. This is a control section that supplies control signals to the digital processing circuit 6 and the oscillators 14 and 16 using instruction signals. Reference numeral 17 denotes an oscillator that supplies a clock signal (sampling frequency fs) to each of the digital signal processing circuits described above. By configuring as described above, the circuit configuration can be simplified, and the sampling frequency fs can be set to a frequency N times (N is an integer) the horizontal synchronization signal frequency of the analog video signal as described above, and the integer N divided by 4, N=4K+M (K is an integer, M
is any number of 0, 1, 2, or 3), and when the integer N is divided by 3 and N = 3L + Q (L is an integer and Q is any number of 0, +1, -1), P=M
By making the integer P +Q an odd number, it becomes possible to process signals for the NTSC system and the PAL system using the same circuit. (Effects of the Invention) As described above, according to the video signal digital processing method of the present invention, it is possible to process signals of the NTSC system and the PAL system in the same circuit, and for example, the color signal processing of a magnetic recording/reproducing device (VTR) can be performed. When digital signal processing is used, it has the advantage that the scale of the processing circuit can be reduced by using PS (phase shift) processing and decimation processing.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a circuit to which the video signal digital processing method of the present invention is applied, and FIG.
3A to 3C and 3A to 3C are diagrams for explaining the principle of the video signal digital processing method according to the present invention. 1...Input terminal, 2...AD converter, 3, 11
...Frequency converter, 4,10...BPF, 5...
Decimation processing circuit, 6...Digital processing circuit, 7...Filter, 8...Comb filter,
9...Interpolation circuit, 12...DA converter, 13...
Output terminal, 14, 16, 17... Oscillator, 15...
...control section.

Claims (1)

[Claims] 1. The sampling frequency when sampling the input analog video signal and converting it into digital data is set to a frequency N times the horizontal synchronizing signal frequency of the analog video signal (N is an integer);
Then, divide the integer N by 4 to get N=4K+M (K is an integer, M is any number of 0, 1, 2, or 3), and divide the integer N by 3 to get N=3L+Q (L is an integer). , Q is any number of 0, +1, -1), P = M + Q, so that the integer P is an odd number. A video signal digital processing method characterized in that 1/3 decimation processing is performed to leave sampling points as valid data.