JPH0385976A - Television system converter - Google Patents

Abstract

PURPOSE:To attain the wide mode display with simple constitution by aborting a signal data of one scanning line among the data of 3 scanning lines of the high definition television system and using the signal data of the remaining scanning lines to interpolate the scanning line of the standard television system. CONSTITUTION:A scanning line interleave circuit 11 aborts one scanning line from 3 scanning lines among High Vision 1125 scanning lines and only 750 scanning lines are extracted. Then a time axis conversion circuit 12 gives a dummy scanning line data to convert the time axis to from 1050 scanning lines for each frame and an interpolation circuit 13 interpolates to form 525 scanning lines of the NTSC system. Thus, the MUSE/NTSC down-converter applying wide mode display is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention relates to a television format conversion device, and in particular to an MU
Related to wide mode display of SE/NT SC down converter.

(b) Conventional technology The multiple sub-Nyquist sampler encoder encoding method (MUSE method) is a method for band-compressing a high-definition video signal and transmitting it using a broadcasting satellite.
QUIST Sampling Encoding) was proposed by NHK, and NHK Satellite 2nd Channel (BS
It is broadcast on Channel 11).

This method uses a single channel of satellite broadcasting (bandwidth 27M).
In order to transmit a high-definition video signal at a frequency of 8.Hz), this high-definition video signal is subjected to sub-Nyquist sampling using a band compression encoder. It converts into an IM Hz band compressed video signal (MUSE signal, sub-sampled video signal).

The MUSE method is introduced in the following documents.

(a) NHKa Jutsu Kenkyu 1986, Vol. 39, No. 2, No. 172, pp. 18 (76) to 53 (111), Ninomiya, Ohma, Izumi, Koshi, Iwadate rMUSE method (b)
Magazine published by Nikkei McGraw-Hill, "Nikkei Electronics, November 2, 1987, 433", 189-21
Page 2, by Ninomiya, “Using satellites/%Ivision transmission system MUSEJ” The image of this MUSE signal is transmitted to the current television receiver (
To watch on TV), scan 491,125 MUSE
MU that converts the signal into a 9525-scan NTSC signal
SE/NTSC converter required.

This MUSE/NTSC converter (hereinafter referred to as converter) converts the MUSE playback screen with an aspect ratio of 16=9 shown in Figure 8a to a normal TV with an aspect ratio of 4:3.
In order to display the reproduced image on the TV, the "wide mode" shown in FIG. 8 and the "zoom up mode" shown in FIG. 8 C can be selected.

The zoom up mode for converting a high quality TV signal such as a MUSE signal into a standard TV signal will be described below.

In zoom up mode, the television signal converter
As shown in Fig. 9, the high definition signal (HD TV signal) has 1125 scanning lines and a field frequency of 60H2.
is created by the horizontal image truncation circuit (21) in Figure 10 (a
), the image data on the left and right sides of the screen in the horizontal direction are discarded. Next, the scanning line number conversion circuit (22) discards 75 scanning lines from the original number of 1125 and converts the time axis, reducing the number of scanning lines for each frame to 1050 (10
50/60). Thereafter, as shown in FIG. 11, the scanning line 525 passes through an interpolation circuit (23) that converts the interlace so that the interlace is correctly performed.
Book, Field Frequency! It becomes a video signal of k 60 Hz.

In reality, the horizontal image data truncation circuit (21) and the time axis conversion circuit (22) are combined into one image by controlling the writing and reading of the time axis expansion circuit (20), as shown in FIG. It becomes a circuit. This time axis expansion circuit (20
) are separated from the buffer memory (24), write address counter (25), read address counter (26), and gate (27). CKI is a 1125/60 system clock, and CK2 is a 1050/60 system clock. HDTV aspect ratio is I6:9, NTS
Since the aspect ratio of C is 43, in order to cut out the high-visibility 3 screen in the horizontal direction, only a part of the screen in the horizontal direction is used at the gate (27) using the "writing period pulse (2)" shown in Fig. 3. is written into the buffer memory (24). 1050/6 from buffer memory (24)
Image data is constantly read out according to the 0 system clock.

Next, 525 video signals (525/
60) The operation of the device that outputs two sets of
This will be explained with reference to FIG.

Figure 13 shows a satellite broadcasting receiving system, (40) is B
It is an S antenna. (41) is the antenna body. (
42) is a frequency conversion circuit, which converts the received signal in the 12 GHz band to the I GHz band.

(43) is a BS tuner with a converter (44). (45) converts the signal of the desired channel among the signals in the 1 GHz band into the second intermediate frequency signal of 402.78 MHI (
2ndlF). (46
) is an FMg tone circuit. (47) is an amplifier.

(48) is a control circuit consisting of a channel selection microcomputer. i
The control circuit (48) controls the PLL control circuit (50) to receive the signal of the desired channel.

(50) is an output processing circuit for normal broadcasting (NTSC broadcasting), which performs triangular wave removal, etc.; (51) is a synchronization separation circuit, which separates and outputs synchronization signals.

(44) is a converter, and when the MUSE signal is input, M
Identify the USE signal reception and send the discrimination signal to the terminal (44b)
At this time, the keyed AFC pulse (P) indicating the clamp level period of the MUSE signal is also output from the terminal (
44 (:). The converter (44) outputs a pseudo-NTSC video signal from a terminal (44d).

(52) is an operation switch section.

(s*1) is an output changeover switch, and (sw2) is an input changeover switch section.

(55) is a normal television receiver. (56)
is a MUSE decoder, and (57) is a high-definition television receiver. (58> is a MUSE disc player.

Keyed AFC pulse (P) from MUSE decoder (56) and converter (44) and synchronous separation circuit (51)
The vertical synchronization signal is a signal for receiving a desired channel without the influence of triangular waves in satellite broadcasting, and is well known (for example, Japanese Patent Laid-Open No. 135582/1982).

Figure 14 shows a converter (
44). (59) on the left side of the figure is MU
This is an SE signal processing system, and basically various timing controls are performed using synchronization signals and clock signals from a clock synchronization reproducing circuit (91). (60> is the NTSC signal processing system, basically a clock synchronization generation circuit (93
) Various timing controls are performed using synchronization and clock signals from

In FIG. 14, (61) is an 8.1 MH2 low-pass filter. (62) is a clamp circuit that performs a clamp operation during the horizontal synchronization period. (63) is 16°zHt
This is an A/D conversion circuit that operates using a sampling clock.

(64> is a time axis expansion circuit, which expands the central 1050 video signals of the 1125 scanning lines of the MUSE signal on the signal amount axis for the NTSC signal.

(65) is an IH delay circuit for the MUSE signal. (66
) (67) is a memory for time axis expansion of the Y signal, the memory (66) is for even lines, and the memory (67) is for odd lines.

(68) is a vertical filter circuit (interpolation circuit) for luminance signals
(69) is an IH delay circuit, and (70) is a vertical filter arithmetic circuit.

(71) is a vertical filter circuit for the RY signal. (
72) is a shift register for the time axis expansion circuit, (73)
(74) is a shift register for the IH delay circuit, and (74) is an arithmetic circuit for the vertical filter.

(75) is a vertical filter circuit for the B-Y signal, (
76) is a time axis expansion circuit, (77) and (78) are IH delay circuits, and (79) is a vertical filter arithmetic circuit.

(80) is the Y signal layer D/A conversion circuit, (81) is the R-Y
Signal layer D/A conversion circuit, (82) is D/A for B-Y signal
It is a circuit of change. (83) is a low-pass filter for the Y signal, (84) and (85) are low-pass filters for the RY and B-Y color difference signals, and (86) is a matrix circuit.

(87) is an NTSC color encoder. (88)
is a color modulation circuit, and (89) is a color printing and carrier wave oscillation circuit, which oscillates at 3579545 Hz. (90) is an adder circuit.

(91) is a clock synchronized regeneration circuit, and the input MUSE
16.2MH synchronized to the clock component of the signal.

The clock signal, freight pulse, and horizontal synchronization signal are regenerated. Further, this clock synchronization reproducing circuit (91) determines whether or not it is the MUSE signal time based on the presence or absence of synchronization, and outputs a determination signal. It also outputs a keyed AFC pulse (P) corresponding to the clamp level period.

(92) is a control timing signal generation circuit that generates various signals for IJJ control of the circuits (65), (66), and (67) based on the signals from the clock synchronization regeneration circuit (91).

(93) is a clock synchronization generation circuit that generates horizontal synchronization and clock signals for NTSC. This circuit (93)
The 10.08 MHz reference signal is 16.2 MHz for MUSE.
MH! PLL control is performed to synchronize with the clock signal. (94) is a 1/45 frequency divider circuit, (95) is a 1/45 frequency divider circuit, and (95) is a 1/45 frequency divider circuit.
28 frequency divider circuit, (96) is a phase comparator, (97) is a low-pass filter, and (98) is a 10.08MH2 reference oscillation circuit. (99) is l/64 for horizontal synchronization signal creation
This is a 0 frequency divider circuit. Furthermore, this 1/640 frequency dividing circuit (99
) is reset by the frame synchronization signal of the MUSE signal of 30H2 from the clock synchronization regeneration circuit (91). (100) is a circuit (66) (67) (69) (7
2) A control timing signal generation circuit that generates various signals for controlling (73), (76), (77), and (78). This circuit (100) also generates a vertical synchronization signal from the horizontal synchronization signal and frame signal, and generates a composite synchronization signal (S
YNC) is output.

The processing of the above video signal will be briefly explained.

The input MUSE signal is passed through a low pass filter (61)
, the clamp circuit (62>) and the A/D conversion circuit (63) to the time axis expansion circuit (64).The MUSE signal (15th
In Fig. a), the IH delay is performed by the IH delay circuit (65). This output is shown in FIG. 15C.

Writing to the memory (67) is performed by the aforementioned control timing signal generation circuit (92)! 191+ and writes only the central part of the Y signal of the even line and the color signal (RY signal) of the odd line.ii Control pulse first cause memory (67) is controlled like a FIFO memory, and reading is , the aforementioned control timing signal generation circuit (100)
It outputs the signal shown in FIG. 15d. Among these signals, the time expansion of the color signal is insufficient, but the time axis of the Y signal is expanded to the normal value of the NTSC signal.

The memory (66) is also controlled in the same manner as shown in FIG. 15a.
Extend the time axis as shown in b.

The two Y signals shown in FIG. 15 bd are input to a Y signal vertical filter circuit (68) (interpolation circuit), subjected to vertical filter processing, and output as Y signals.

In addition, the RY signal and BY signal in FIG. Afterwards, vertical filter processing is performed and output as an RY signal and a BY signal.

These Y, R-Y, B-Y signals are processed by the D/A conversion circuit (
80) (81) (82), low pass filter circuit (83
) (84) (85), the color encoder circuit (
87) and the color television video signal (
NTSC signal).

(c) Problems to be Solved by the Invention The present invention is directed to an MU that performs wide mode display as shown in FIG.
The present invention provides an SE/NT SC down converter.

It also provides a MUSE/NTSC down converter that performs both zoom up mode display and wide mode display.

(2) Means for Solving the Problems The present invention is an apparatus for converting a high-definition television system signal into a standard television system signal, which converts the three scanning lines of the high-definition television system into a standard television system signal. This is a television format conversion device that discards the signal data of one of the scanning lines one by one and uses the signal data of the remaining scanning lines to interpolate the scanning lines of the standard television format.

Further, the present invention provides a television format converter equipped with a time axis expansion circuit that inputs a MUSE signal of 1125 scanning lines and outputs a video signal of 525 scanning lines in two series, in a wide mode and In accordance with the zoom up mode, the read clock frequency to the time axis expansion circuit is switched, and in the zoom up mode, the two video signals are the video signals of the 20th line and 20+1 line (n is an integer) of the MUSE signal. Set the writing period as much as possible, and in wide mode, the video signals of the two systems are connected to the MUSE
Signal 3rn+l! line and 3m+$+1 line (m is an integer, t is 0, 1.

It is characterized in that the writing period is set as much as possible to obtain the video signal of any one of (2).

(e) Effect Out of the 1125 scanning lines of a high-definition system, 750 lines are extracted by discarding the scanning line signal data of every third line, and 300 dummy scanning lines are added to make the number of scanning lines 1050. , 525 scanning lines of the NTSC system are created by interpolation.

Further, by controlling the time axis expansion circuit (64), wide mode and zoom up mode can be selected.

(F) Embodiment An embodiment of the present invention is shown in FIGS. 1 and 2. In FIG. 1, the high-definition signal is processed by a scanning line thinning circuit (1
1>, one out of every three scanning lines is discarded, and only 750 scanning lines are taken out. Thereafter, a time axis conversion circuit (12) adds dummy scanning line data and converts the time axis, resulting in two sets of signals each frame having 1050 scanning lines or 525 scanning lines. Second
The figure shows a scanning line thinning circuit (11) and a time axis conversion circuit (12).
), and the circuit is approximately the same as that in FIG. 12.

This time axis expansion circuit (20) includes a buffer memory (14).
), write address, counter (15>, read address counter (16), game) (17) (18).

CKI is a 1125/60 series clock, and CK2 is a 1050/60 series clock.

By inputting the "write period pulse (1)" shown in FIG. 3 to (17), only two out of three scanning lines are written into the buffer memory (14).

At this time, all video data is written in the horizontal direction. When reading from the buffer memory (14),
The “readout period pulse (1)” shown in Fig. 4 is gated (
18) to read data only in a vertical portion of the screen.

In other words, 750 out of 1125 high-definition scanning lines
The book is written to the buffer memory (14), then the written scan lines and 300 dummy scan lines are added,
1050 scanning lines are the interpolation circuit (12) in Figure 1.
sent to. The interpolation circuit (12) performs almost the same operation as the conventional example as shown in FIG.
C scan lines are created. Here, the "x" mark indicates a scanning line that is not written into the buffer memory (14). Note that the interpolation circuit (13) may have different coefficients and configuration from the conventional example.

When the above-mentioned thinning is performed using the circuit shown in FIG. 14, the operation in the zoom up mode is the same as the conventional one. Then, in the wide mode, the write periods of the memories (66) and (67) are switched. The writing period of this memory (66) (67) is shown in FIG. 7e.

Further, the read clock at this time requires a higher frequency clock than in the zoom up mode. For this,
The clock synchronization generation circuit (93) is shown in FIG. In FIG. 6, (98a) is a 30° 24 MHz oscillation circuit, (98b) is a 1/3 frequency divider, and (98c) is a 172 frequency divider.

That is, in the wide mode, the clock from the 172 frequency divider (98c) is used instead of the 1/3 frequency divider (98b) output.

(G) Effects of the Invention As described above, according to the present invention, wide mode display can be performed.

Also, wide mode and zoom up mode display can be performed.

[Brief explanation of drawings]

FIG. 1, FIG. 112, FIG. 3, FIG. 4, and FIG. 5 are diagrams for explaining one embodiment of the present invention. FIG. 6 and FIG. 7 are diagrams showing a second embodiment. Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 1
3, FIG. 14, and FIG. 15 are diagrams showing conventional examples. (20) (64)...Time axis expansion circuit.

Claims (2)

[Claims] (1) A device that converts a high-definition television system signal into a standard television system signal, which discards the signal data of one of the three high-definition television system scanning lines and uses the remaining scanning lines. A television format conversion device that interpolates standard television format scanning lines using signal data. (2) In a television format conversion device equipped with a time axis expansion circuit that inputs a MUSE signal with 1125 scanning lines and outputs two video signals with 525 scanning lines, the Then, the read clock frequency to the time axis expansion circuit (64) is switched, and when zooming up, the video signals of the two systems are switched to the MUS.
The write period is set so that the video signals of 2n lines and 2n+1 lines (n is an integer) of the E signal are set, and in the wide mode, the video signals of the two systems are written to the 3m+l line and 3m+l+1 line (m is an integer) of the MUSE signal. 1. A television format conversion device characterized in that a writing period is set as much as possible to obtain a video signal (l is any one of 0, 1, and 2).