JPH04172885A - Television receiver - Google Patents

Abstract

PURPOSE:To display videos in accordance with the intention of a TV station by switching the program given to each digital signal processor(DSP) by utilizing a pulse inserted at the TV station. CONSTITUTION:Video signals inputted through an input terminal 1 are given to the latch circuit 6 of a program switching section 4 and, at the same time, to synchronizing separator circuit 2 and synchronizing signals are separated from the video signals. A timing circuit 5 generates timing signals indicating the 263 lines of the video signals on the basis of the synchronizing signals and supplies the timing signals to a program counter 7. The counter 7 generates the addresses of program storing sections 9 and 10 in accordance with the timing signals. The latch circuit 6, on the other hand, is controlled by the circuit 5 and latches the 263 lines of the video signals. When no switching signal is inserted into the video signals, an 'L' control signal from the circuit 6 is outputted to a select circuit 8 and, when the switching signal is inserted, an 'H' control signal is outputted to the circuit 8. Thus the prescribed program of the storing section 9 or 10 is given to a DSP 3 and videos are processed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a television receiver that is capable of realizing a plurality of types of video processing by switching programs given to a digital signal processor.

(Prior Art) FIGS. 7 to 10 and 11 are a block diagram and an explanatory diagram, respectively, for explaining a digital signal processor (hereinafter referred to as DSP).

These block diagrams and explanatory diagrams are from the document rA GENE
-RAL PURPO3E PROGRAHHA
BLE VIDEOS IGMAL PROCESSO
RJ (IEEE Transactions on
C0n5uler Electronics Vo
1, 35 No. 3 AUGUST 1989), and indicates a DSP for video signal processing.

FIG. 7 shows a DSP chip 100 for video. D
The SP chip 100 is a DSP chip having five data ports to enable interconnection between multiple DSPs.
101. Clock generator 102
creates an internal clock based on an external clock. The initial controller 103 is given initial data and a reset signal, and when given a chip address indicating this DSP chip 100, performs predetermined initial settings.

FIG. 11 is an explanatory diagram for explaining the architecture of the DSP.

The DSP has three systems of ALE (＾ri-t
Tvetic and Logic Element
) and two systems of M E (Memor
y Elcvent) and five systems of OB (output buffer).

The three ALE systems, the two ME systems, and the five OB systems are controlled by programs P1 to PIO, respectively.

FIG. 8 shows the configuration of ALE.

The ALE has ports 105 to 107 that take in data, and data A, B, and C input through each port 105 to 107 are sent to the ALU ( (logical operation unit) 114.

FIG. 9 shows the configuration of the ME.

The address data is given to an adder 116 via a port 115, added to a predetermined value, and further added to a multiplexer 117.
to RAM 118 via. - On the other hand, data is input via port t-119 and multiplexer 1
20 to RAM Hl.

RAM 18 is a 512x12 static memory.

FIG. 10 shows a DSP chip 121 composed of three DSPs 122 to 124. Each DS
The DSPs 122 to 124 are interconnected using data ports, and each DSP 122 to 124 has one data port for data transfer with the outside.

In recent years, an increasing number of home appliances use the above-mentioned DSP to perform digital processing.
The DSP is also employed in the image reproducing device j, etc. described in the specification of Japanese Patent Application No. 2-84628, which the present applicant previously discussed.

According to this proposal, a television receiver is configured that utilizes a plurality of DSPs to realize a plurality of functions. A plurality of processing programs are prepared to realize a plurality of functions, and these processing programs are switched by a timing signal created during a vertical or horizontal blanking period of a video signal transmission period. For example, this timing signal switches the processing program of each DSP so that normal television video processing is performed during the video period and ghost cancellation processing is performed during the non-video period.

By the way, in recent years, with the proliferation of large display devices, there has been a demand for higher image quality, and from 1989 onwards, the first generation EDT
Television broadcasting by i-tion TV has begun. Furthermore, the second generation E is used to improve image quality.
Research on television broadcasting using DTV is also being conducted.

One of these is the wide aspect television receiver (hereinafter referred to as wide TV), which expands the aspect ratio of the screen.
) is being considered.

Wide TVs maintain compatibility with current NTSC television receivers while increasing the aspect ratio to 5=3 or 16.
: This is an enlarged image of 9 mag.

By applying the above-described image reproducing device to such a wide TV, it is possible to easily switch the display between the current NTSC television broadcast and the second generation EDTV television broadcast.

However, in this case, the display must be switched on the image playback device, and the broadcasting station must switch between NTSC and E.
It is not possible to switch between the DTV system and the DTV system.

(Problem to be Solved by the Invention) Conventionally, in television receivers, the program given to each DSP is changed on the receiver side, so the broadcasting station can freely display the intended video. There was a problem that it could not be displayed on the display screen.

The present invention has been made in view of such problems, and includes:
To provide a television receiver capable of displaying images intended by a broadcasting station by making it possible to switch programs given to each DSP using pulses inserted at the broadcasting station.

[Structure of the Invention] (Means for Solving the Problems) A television receiver according to claim 1 of the present invention includes a receiving means for receiving a video signal from a transmitting side capable of inserting a switching signal at a predetermined timing; a synchronization separation circuit that separates a synchronization signal from the video signal received by the receiving means; a timing circuit that uses the synchronization signal to generate a timing signal indicating a predetermined timing at which the switching signal is inserted; a digital signal processor that performs image processing on a signal based on a program; program memory means that stores a plurality of programs to be applied to the digital signal processor; and detects the switching signal from the received video signal at the timing of the timing signal. The present invention is characterized by comprising a switching signal detection means for outputting a detection signal, and a selection means for selecting a program in the program memory means based on the detection signal and applying it to the digital signal processor. The television receiver according to claim 2 of the present invention is characterized in that the switching signal detection means detects a switching signal composed of a digital code, and the television receiver according to claim 3 of the present invention is The apparatus is characterized in that the program memory means stores a program for causing the digital signal processor to perform video processing for displaying an NTSC television signal, and the invention is characterized in that: The television receiver according to Item 4 is characterized in that the program memory means stores a program for causing the digital signal processor to perform video processing for displaying a wide aspect television signal.

(Function) In claims 1 and 2 of the present invention, the timing circuit uses a synchronization signal to generate a timing signal indicating the timing of the switching signal inserted on the transmitting side. The switching signal detection means detects the switching signal at the timing of this timing signal and provides the detection signal to the selection means. The selection means selects a program stored in the program memory means based on this detection signal. The selected program is supplied to the digital signal processor, and the digital signal processor performs video processing based on this program. The switching signal is inserted on the transmitting side, and the processing of the digital signal processor is switched by the operation on the transmitting side.

In claim 3 of the present invention, the program memory means stores a program for causing the digital signal processor to perform video processing for displaying the NTSC television signal, and the program memory means stores a program for causing the digital signal processor to perform video processing for displaying the NTSC television signal, and the switching signal inserted at the transmitting side allows the program memory to display the NTSC television signal. television images can be displayed.

In claim 4 of the present invention, the program memory means stores a program for causing the digital signal processor to perform video processing for displaying the wide aspect television signal, and the program memory means stores a program for causing the digital signal processor to perform video processing for displaying the wide aspect television signal. Television images can be displayed.

(Example) An example of the present invention will be described below with reference to one drawing. FIG. 1 is a block diagram showing an embodiment of a television receiver according to the present invention.

A video signal is input to the input terminal 1. A switching signal for switching the DSP program is inserted into this video signal. This switching signal is inserted at a level of 70 IRE at a position delayed by a predetermined time from the burst signal.

This switching signal is inserted into, for example, the 263rd line and transmitted.

A video signal input through the input terminal 1 is supplied to the synchronization separation circuit 2, the DSP 3, and the program switching section 4. The synchronization separation circuit 2 separates a synchronization signal from the input video signal and supplies it to the timing circuit 5. The timing circuit 5 converts the synchronization signal based on the burst signal, detects the timing of the 263rd line in which the switching signal is inserted, and controls the latch circuit 6 and the program counter 7 at this timing. . The latch circuit 6 is
The 26th input video signal is controlled by the timing circuit 5.
Latch 3 lines. As a result, the latch circuit 6
If a switching signal is inserted, it will be high level (hereinafter referred to as
(referred to as “H”) control signal (for example, TTL “H”)
is output, and if it is not inserted, a low level (hereinafter referred to as "L") control signal (for example, TTL "L") is output.
1) is output to the select circuit 8.

The program counter 7 provides an address output to the program storage section 9.10 by counting a predetermined clock. The program counter 7 is reset by the timing circuit 5, and is reset when the power is turned on and when the switching signal changes. The program storage unit 9.10 stores programs for causing the DSP 3 to perform different signal processing. The program storage units 9 and 10 have a read address specified by the address output from the program counter 7, and output the stored programs to the select circuit 8.

The select circuit 8 switches the program from the program storage section 9-10 in accordance with a control signal from the latch circuit 6 and supplies it to the DSP 3. For example, the select) circuit 8 selects the program storage section 9 with a control signal of "H",
The program storage section 10 is selected by the "L" control signal.

The DSP 3 operates with processing functions based on these programs, performs video processing on the input video signal, and outputs the processed video signal to the output terminal 11.

Next, the operation of the television receiver configured as described above will be explained with reference to the timing chart of FIG. 2. FIG. 2(a) shows a switching signal included in a video signal from a broadcasting station, and FIG. 2(b) shows a control signal from the latch circuit 6.

A video signal input through the input terminal 1 is applied to a latch circuit 6 of a program switching section 4, and is also applied to a synchronization separation circuit 2, where a synchronization signal is separated. The timing circuit 5 uses the separated synchronization signal to determine the 26th timing of the video signal.
A timing signal indicating three lines is applied to the latch circuit 6 and the program counter 7.

The program counter 7 is reset by a timing signal to generate address outputs for the program storage units 9 and 10. In this way, the predetermined programs in the program storage units 9 and 10 are sequentially read out and applied to the select circuit 8.

On the other hand, the latch circuit 6 is controlled by the timing circuit 5 to latch the 263rd line of the video signal.

If the switching signal is not inserted into the input video signal, the latch circuit 6 outputs an L'' control signal to the select circuit 8. In this case, the select circuit 8 outputs an L'' control signal to the select circuit 8. The program is given to the DSP 3. Based on the program given via the select circuit 8, the DSP 3 processes the video signal from the input terminal 1 and outputs it to the output terminal 11.

Conversely, as shown in FIG. 2(a), the second
When the switching signal is inserted in the 63rd line, the latch circuit 6 outputs the "H" control signal shown in FIG. 2(b) to the select circuit 8. Then, the select circuit 8 Select storage section 9. In this way, D
The program supplied to SP3 is switched and the DSP3
performs video processing on the video signal that is different from that before the switching signal is inserted.

In this way, in this embodiment, by detecting the switching signal included in the video signal from the broadcasting station, the DSP
3, and different video processing is automatically performed without user operation when the power is turned on or when the switching signal changes. That is, a predetermined image intended by the broadcasting station is displayed on the display screen of the terminal receiver.

FIG. 3 is a block diagram showing a television receiver according to another embodiment of the present invention. This embodiment allows the broadcasting station to switch between NTSC video and EDTV wide aspect video displayed on the display screen of a terminal receiver.

Further, FIG. 4 is a block diagram showing an encoder on the broadcasting station side. This encoder is rA, WIDE 5
CREENE D T V J (IEEE TRA
NSACTIONS ON C0N5UHEREL
ECTRONIC 3 AUGUST 1989'')

First, a method of creating a video signal from a broadcasting station for displaying current NTSC video or EDTV wide aspect video will be described with reference to the encoder shown in FIG.

On the broadcast station side, first, a wide aspect video signal with an aspect ratio of 16.9 (the band of the luminance signal Y is 5.6
MHz, the bands of color difference signals I and Q are each 2.0MHz
, 0.67MHz) is the signal of a part of the screen center corresponding to the part with an aspect ratio of 4:3 (hereinafter
The signal is divided into a center signal (hereinafter referred to as a center signal) and a screen side signal (hereinafter referred to as a side signal) corresponding to the left and right edges of the screen.

The center signal is time-expanded 473 times, and its luminance signal component (4,2MH2>) and color difference signal component I,Q (I
Q: 1.5 MHz, Q: 0.5 MHz) are respectively given to preprocessors 21 and 24 which perform multiplexing without deteriorating the image quality of a part of the screen center.

The luminance signal components of the side portion of the screen are luminance signals of three types of frequency components Yl, Y2. It is divided into Y3 and transmitted using three types of multiplexing methods. That is, the luminance signal component Y1 ranges from 0 to Q
, has a band of 9 MHz, and after being time-compressed to 1/4, the horizontal overscan part (shaded part) of the center signal
multiplexed into

The luminance signal from the brightness processor 21 is output to a combining circuit 26.

The luminance signal Y2 is 0.9 to 5.6M in the first field.
It has a band of H2, oblique high frequency components are removed, and the time is expanded twice on average. Time-stretched luminance signal Y2
is given to the frequency shift circuit 22, and the frequency is set to 615.
fsc (fsc is color subcarrier frequency) (4,3MH2)
Then, the frequency is shifted by the subcarrier whose field phase is inverted.

This luminance signal Y2 is given to the synthesis circuit 26, and is three-dimensionally frequency multiplexed into 2 to 4 MH2 of the luminance signal of a part of the center of the screen.

The luminance signal Y3 is 0.9 to 2.7M in the second field.
It has a band of Hz, and time is compressed by 1/2.

Furthermore, regarding the luminance signal Y3, the data is rearranged using a buffer memory, etc., and the output of the 0 frequency shift circuit 23, which is frequency shifted by a subcarrier of 10/13 fsc (2°8 MH2) in the frequency shift circuit 23, is sent to the synthesis circuit 26. is given and multiplexed in the vertical overscan area (shaded area).

The luminance signals Yl to Y3 from the synthesis circuit 26 are supplied to a precombing circuit 28, where they undergo motion adaptive precombing, and are band-limited to horizontal and vertical two-dimensional diagonal high frequencies of the moving image area.

On the other hand, the color difference signal 1 on the side of the screen. Q is divided into two types of frequency components C1 and C2 and transmitted using two types of multiplexing methods. That is, the signal C1 has a frequency band of 0 to 0.12.
MHz, time-compressed to 1/4, and the color difference signal ■ in the center of the screen.

It is multiplexed into the horizontal overscan area of Q. signal C2
The frequency band of the color difference signal I is 0.12 to 2.0MH7
, and the frequency band of the color difference signal Q is 0.12 to 0.6.
It is 7MH2, and the time is compressed by 4 times. Furthermore, signal C
2, the frequency is 1/7f in the frequency shift circuit 25.
sc (0,5MH2>), the frequency is shifted by a subcarrier whose line and field phases are inverted.The signal C2 from the frequency shift circuit 25 is given to the synthesis circuit 27, and is converted into the color difference signals I and Q of a part of the screen center. 3D frequency multiplexed.

The signals C1 and C2 from the synthesis circuit 27 are fed to a precombing circuit 29 and subjected to motion adaptive precombing, and the horizontal high frequency range of the moving image area is band-limited to 0.5 MHz. Further, the color difference signals I and Q from the precombing circuit 29 are orthogonally modulated by a 3°58 MHz color subcarrier in a quadrature modulation circuit 30.

The luminance signal Y from the precombing circuit 28 and the color signal C from the quadrature modulation circuit 30 are multiplexed in a combining circuit 31 and sent out.

This video signal is received and decoded on the receiving side. A switching signal is inserted into this video signal (not shown).In this embodiment, three switching signals are inserted.
．． Use binary NZR format digital data with a data rate of 58 MHz. For example, as a switching signal, use a data code such as "1110010" with a sharp autocorrelation function peak like Parr series data. . On the transmitting side, this data is inserted at a position a predetermined number of clocks apart from the trailing edge of the 263rd line of the vertical blanking period based on the clock of the color burst signal.

On the other hand, on the receiving side, as shown in FIG. (omitted), the tuning section 42 selects a channel based on the tuning signal, converts it into an intermediate frequency (IF) signal, and supplies it to the IP section 43. The IF section 43 detects the IP signal and outputs a baseband video signal.

The audio intermediate frequency amplification/detection circuit 44 audio detects the audio intermediate frequency signal included in the video signal from the IP section 43 and converts it into an A/D converter.
Output to converter 45. The A/D converter 45 converts the audio detection output into a digital signal and outputs it to the audio signal processing circuit 46. The audio signal processing circuit 46 performs various processes such as audio multiplexing, soundscape, sound quality, and balance, and outputs the audio signal to the D/A converter 41. The D/A converter 47 converts the audio signal from the audio signal processing circuit 46 into an analog signal and supplies it to the speaker 48 for audio output.

On the other hand, the video signal from the IF section 43 is also given to the A/D converter 49. The A/D converter 49 converts the analog video signal into a digital signal and supplies it to the synchronization separation circuit 50, the color subcarrier regeneration circuit 51, and the DSP array group 52.

The synchronization separation circuit 50 separates the synchronization signal from the video signal and supplies it to the timing circuit 54.

Further, the color subcarrier reproducing circuit 51 generates a clock having a frequency of fsc based on the input video signal, and supplies it to the timing circuit 54 and the switching signal detection circuit 55. The timing circuit 54 uses the synchronization signal from the synchronization separation circuit 50 to detect the 263rd line of the vertical blanking period, counts the clock of frequency fSC from the color subcarrier regeneration circuit 51, and detects the 263rd line of the vertical blanking period by A pulse is generated at a position separated by a predetermined number of clocks from the trailing edge of the line and applied to the latch circuit 56.

The switching signal detection circuit 55 samples the binarized input video signal and reproduces it as discretized data. The output of the switching signal detection circuit 55 is supplied to a latch circuit 56 and a program counter 57.

The latch circuit 56 latches the output of the switching signal detection circuit 55 at the timing of the pulse from the timing circuit 54, and sends an "H" control signal to the select circuit 53 when the switching signal is inserted into the video signal. If it is not inserted, a "no" control signal is output to the select circuit 53.

The program counter 57 is reset by the output of the switching signal detection circuit 55 and counts a predetermined clock. The count output of the program counter 57 is given to the program storage sections 58 and 59 as a read address. The program storage sections 58 and 59 each have a normal NTSC
A video processing program A for receiving television broadcasting and a video processing program B for receiving wide aspect television broadcasting are stored. Program storage section 58.5
9 is a read address designated by the program counter 57, and selects the respective program storage portion FI853.
It is designed to output to .

The select circuit 53 selects the program storage section 58 in response to an "L" control signal from the latch circuit 56, and selects the program storage section 59 in response to an "H" control signal.

The DSP array group 52 is arranged in a 4×4 array.
It is composed of six DSP groups D1 to D16. Each DSP group D1 to D16 of the DSP array group 52 is
As described above, it has an internal memory (not shown), and receives a program from the select circuit 53 to implement processing functions based on this program. That is, D
A video processing program A is sent to the SP array group 52 via a select circuit 53.

B is given, and processing for receiving normal television broadcasting or processing for receiving wide aspect broadcasting is performed.

The video processing program A is stored in the program storage unit 58 as DS.
When given to PDl to D16, DSP groups DI, D
2 performs Y/C separation, DSP groups D5゜D9 perform three-dimensional filter processing, DSP groups D14゜D15 reproduce the center signal whose time has been expanded by 4/3 on the broadcasting station side, and
The SP group D16 provides a center signal to the D/A converter 60, and also performs mask processing on the left and right ends of the monitor 63.

Furthermore, the DSP group D3 separates the color difference signals I and Q, and the DSP
Groups D4 and D8 perform three-dimensional filter processing on the color difference signals, DSP groups Dll and D12 reproduce the original screen center signal by 3/4 times time compression, and DSP1D1
2 supplies this reproduced output to the D/A converter 61 and performs mask processing on the left and right ends of the monitor 63.

On the other hand, the video processing program B for wide aspect signal reception from the program storage unit 59 is stored in the DSP array group 52.
, the DSP group D1. D2 performs Y/C separation processing, DSP groups D5 and D9 perform three-dimensional filter processing to separate the luminance signal Y1 multiplexed in the horizontal overscan portion and the luminance signal Y2 frequency multiplexed, and the DSP Group D14. D15 compresses the center signal by 3/4 times to reproduce the original center signal, and expands the side signal by 4 times to restore the original side signal.
The SP group D13 performs a frequency shift using a subcarrier of 615 fsc and time compression of 1/2 on the luminance signal Y2 to reproduce the screen side part of the first field, and the DSP group D6 rearranges the data and outputs the DSP$ fD10 is 615f
The side part of the screen of the second field is reproduced by frequency shifting and twice the time expansion using the subcarrier of D.
SP group D16 is DSP group D15. D13. The outputs of Dlo are combined and output to the D/A converter 60.

Regarding color difference signals, DSpH\D3 performs separation processing of color difference signals I and Q, and DSP1ffD4゜D8 performs 3
Dimensional filter processing is performed, and the DSPs 9D11 and 12 compress the center signal by 3/4 times and return it to the original center signal, and the DSP group D12 outputs the output to the D/A converter 61.

The D/A converters 60 and 61 convert the input signals into analog signals and output them to the matrix circuit 62. The matrix circuit 62 processes the luminance signal from the D/A converter 60 and the color difference signal from the D/A converter 61 into R, G,
A B video signal is created and output to a monitor 63.

Next, the operation of the television receiver configured as described above will be explained with reference to the flowcharts of FIGS. 5 and 6. FIG. 5 shows the operation when receiving a normal NTSC television broadcast, and FIG. 6 shows the operation when receiving an EDTV wide aspect television broadcast.

Now, it is assumed that a processing function for receiving normal television broadcasting is realized. In this case, no switching signal is inserted into the 263rd line during the vertical blanking period on the transmitting side.

The RF multiplied signal induced in the antenna 41 is given to the tuning section 42. The zero tuning section 42 selects a channel based on the tuning signal, converts it into an IP signal, and gives it to the IF section 43.

The IF section 43 performs IF multiplied signal detection and outputs a baseband video signal. The audio intermediate frequency signal included in the video signal from the IF section 43 is applied to an audio intermediate frequency amplification/detection circuit 44 and detected, and then converted into a digital signal by an A/D converter 45. This digital audio signal is
The audio signal processing circuit 46 performs audio multiplexing and processes such as volume, tone quality and balance, and the D/A converter 47 converts the signal into an analog signal. This analog signal is applied to the speaker 48 and output as audio.

On the other hand, the baseband video signal from the IF section 43 is
After being converted into a digital signal by the D converter 49,
939714 group 52 DSP group DI, synchronous separation circuit 50
and the color subcarrier recovery circuit 51.

Since no switching signal is inserted into the video signal from the A/D converter 49, the output of the switching signal detection circuit 55 causes
The output of the latch circuit 56 becomes "L", and the select circuit 5
3 selects the program storage section 58.

The read address of the program storage section 58 is specified by the program counter 57, and the 939714 group 52 is supplied with the video processing program A for normal television broadcast reception.

In this case, the 939714 group 52 operates based on the flowchart in FIG. That is, in step S1 of FIG. 5, the video signal input via the DSP $\D1 is subjected to Y/C separation by the DSP groups DI and D2. Regarding the luminance signal component, three-dimensional filter processing is performed in the next step S2. That is, the luminance signal is DSP1
The luminance signal Y1, which is applied to f\D5 and D9 and multiplexed in the horizontal overscan portion, is separated.

From DSP group D13, the luminance signal of a part of the screen center is DS.
It is supplied to P group D14. The DSP group D14 performs time compression in the next step S3, and the broadcasting station side
The center signal, which has been time-expanded twice, is regenerated into the original signal. In the next step S4, the DSP group D16 supplies this luminance signal to the D/A converter 60 to convert it into an analog signal, and also performs processing for masking the left and right ends of the monitor 63.

On the other hand, for the color signal, the processes of steps S5 to S8 are performed. Step S5 is a zero-order step S in which the color difference signals I and Q are separated from the color signal by the DSP group D3.
6, three-dimensional filter processing is performed. That is, D.S.
P groups D4 and D8 separate the signal C1 of the screen side portion multiplexed in the horizontal overscan portion.

In the next step S7, the DSP groups Dll and D12 are
As with the luminance signal component, by 3/4 time compression,
Play back the original center signal. The DSP group DI2 transmits this center signal to the D/A converter 6 in the next step S8.
Output to 1. Furthermore, in this case, the DSP group D12 also performs processing for masking the left and right ends of the monitor 63.

The luminance signal and color difference signal from the D/A converters 60 and 61 are subjected to matrix processing by a matrix circuit 62, and a monitor 63 is provided with R, G, and B signals of a part of the center of the screen. Further, the side portion of the screen is masked, and a predetermined black level is displayed, for example.

In this way, a portion of the screen center of the wide aspect video having an aspect ratio of 4=3 is displayed on the screen of the monitor 63.

On the other hand, it is assumed that the 939714 group 52 realizes a processing function for displaying wide aspect video of the EDTV system. In this case, a switching signal is inserted into the 263rd line of the vertical blanking period on the transmitting side.

Since the switching signal is inserted into the video signal, the output data of the switching signal detection circuit 55 causes the output of the latch circuit 56 to become "H". This causes the selection circuit 53 to select the wide aspect broadcast from the program storage section 59. The video processing program B for reception is given to the 939714 group 52. In this case, the 939714 group 52 operates based on the flowchart in FIG.

First, in step S11, the video signal input via the DSP group D1 is Y/C separated by the DSP groups Di and D2.In step S12, the luminance signal component is passed through a three-dimensional filter by the DSP groups D5 and D9. It is processed. As a result, the luminance signal Y1 multiplexed in the horizontal overscan portion and the luminance signal Y2 frequency multiplexed are separated.

In the next step S13, the luminance signal of a part of the center of the screen and the luminance signal Y1 are reproduced. That is, DSP group D
I4. C15 time-compresses the luminance signal at the center of the screen by 3/4 times and returns it to the original center signal, and expands the luminance signal Y1 at the screen side by 4 times to return it to the original side signal; on the other hand, the luminance signal Y2 is frequency-shifted by the subcarrier with a frequency of 615 fSC by the DSP group D13, and is further time-compressed by 1/2 (step 514).
), thereby the signal of the screen side portion of the first field is reproduced.

Furthermore, the luminance signal from DSP@02 is processed in step S15.
is given to DSP group D6, the data is rearranged, and D
The frequency is shifted by a subcarrier of 615 fsc by the SP group D10, and the time is further expanded by a factor of two. In this way, in step S16 of the 0th order in which the luminance signal of the screen side part of the second field is reproduced in step S15, the DS
P group D15. Luminance signals Yl, Y from C13°Dlo
2. Y3 is synthesized by the DSP group D16 and transferred to the D/A converter 60.
is supplied to

On the other hand, the color signals separated in step S11 are processed in steps S17 to S21. That is, D.S.
The P group D3 converts color difference signals I and Q from the color signals in step S17.
In the zero-order step 318 of separating the DSP group D4
, D8, three-dimensional filter processing is performed similarly to the luminance signal, and the signals CI and C2 are separated.

In the next step S19, the DSP group D11°C1
2, the center signal is reproduced with 3/4 time compression. On the other hand, in step S20, the color difference signals I and Q at the side of the screen are frequency-shifted by a subcarrier of 1/7 fSC, time-compressed to 1/4 times, and combined with the signal at the center of the screen.

In the next step S21, step S19゜S2
Signals C1 and C2 obtained at 0 are combined and D/
The signal is supplied to the A converter 61. The luminance signals and color difference signals from the D/A converters 60 and 61 are subjected to matrix processing by a matrix circuit 62. In this way, the R, G, and B signals of wide aspect broadcasting are supplied to the monitor 63, and an image with an aspect ratio of 16:9 is displayed on the display screen.

As described above, in this embodiment, by inserting a switching signal at the broadcasting station, NTSC video and wide aspect video are switched and displayed according to instructions from the broadcasting station.

[Effects of the Invention] As explained above, according to the present invention, by making it possible to switch programs given to each DSP using pulses inserted at the broadcasting station, the video intended by the broadcasting station can be displayed. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a television receiver according to the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment, and FIG. 3 is a diagram showing another embodiment of the present invention. Block diagram, Figure 4 is a block diagram showing an encoder that creates NTSC and EDTV video signals, Figure 5
6 and 6 are flowcharts for explaining the operation of the embodiment of FIG. 3, and FIGS. 7 to 10 and 11 are block diagrams and explanatory diagrams, respectively, for explaining the DSP. 2... Synchronous separation circuit, 3... DSP, 5... Timing circuit, 6... Latch circuit, 7... Program counter, 8... Select circuit, 9.10... Program storage Department. L-i Figure 1 Figure 2±Sigto (c) 7〈81to3 N-L ito lol

Claims (4)

[Claims] (1) A receiving means for receiving a video signal from a transmitting side capable of inserting a switching signal at a predetermined timing, a synchronization separation circuit for separating a synchronization signal from the video signal received by the reception means, and a synchronization separation circuit for separating a synchronization signal from the video signal received by the reception means; a timing circuit that generates a timing signal indicating a predetermined timing at which the switching signal is inserted; a digital signal processor that processes the received video signal based on a program; and a plurality of programs that store a plurality of programs to be applied to the digital signal processor. program memory means for detecting the switching signal from the received video signal at the timing of the timing signal and outputting a detection signal; and selecting a program in the program memory means based on the detection signal. and selecting means for supplying the digital signal to the digital signal processor. (2) Claim 1, wherein the switching signal detection means detects a switching signal composed of a digital code.
The television receiver described in . (3) The television receiver according to claim 1, wherein the program memory means stores a program that causes the digital signal processor to perform video processing for displaying an NTSC television signal. Machine. (4) The television receiver according to claim 1, wherein the program memory means stores a program that causes the digital signal processor to perform video processing for displaying a wide aspect television signal. .