JP3246084B2 - MUSE decoder that prevents remaining images - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MUSE decoder for decoding a Hi-Vision signal encoded by the MUSE method, and more particularly, to a MUSE decoder suitable for specially reproducing a Hi-Vision signal recorded on a laser disk or the like. Things.

[0002]

2. Description of the Related Art Recently, high-definition television broadcasting called high-definition television has been broadcasted using satellite broadcasting. According to the Hi-Vision standard, the number of scanning lines is 1125, the interlace ratio is 2: 1, the field frequency is 60 Hz, the luminance signal band is 20 MHz, and the signal bands of the color difference signals RY and BY are both 7 MHz.

In order to transmit the Hi-Vision signal as it is, a frequency band exceeding 100 MHz is required. However, the allocation of the frequency band for satellite broadcasting is fixed, and the currently usable 12 GHz band is 27 MHz per channel. However, the modulation method is frequency modulation (F
M). Then, high-definition broadcasting requires several satellite broadcasting channels, but it is not preferable to use a plurality of channels from the viewpoint of economy, and the channel allocation to Japan is one.
Since every channel is used, a plurality of discontinuous channels are used collectively. However, since this is technically difficult, a single channel must be used.

The frequency band of a single channel is 27 MHz
When z is calculated back, the baseband signal needs to have a frequency band of about 8 MHz in order to transmit a high-definition signal by FM. Therefore, the band compression technology MUSE (Mult
The frequency band of the Hi-Vision signal is compressed to about 8 MHz using an iple sub-Nyquist Sampling Encoding method.

Hereinafter, an outline of the MUSE compression technique will be described with reference to FIGS. 8 and 9. FIG. FIG. 8A shows an original sample signal having a sampling rate of 48.6 Ms / s.
−- ○ is a sampling signal of an even field,
− ● is a sampling signal of an odd field. This original sample signal is subjected to inter-field offset sampling to obtain 1/1 of the original sample signal shown in FIG.
A sampling signal of 24.3 Ms / s. Inter-field offset sampling is to invert the phase for each field and perform sampling every other sample. When this sampling is performed, every other sample point is thinned out as shown in FIG. In the odd field and the even field, the sampling points and the thinning points are reversed.

Then, after passing this signal through a low-pass filter (LPF) having a cutoff frequency of about 12 MHz,
The sampling rate is returned to the original 48.6 Ms / s as shown in FIG. And this 48.
The sampling rate of 6 Ms / s is converted to 32.4 Ms / s, as shown in FIG. Next, this signal is subjected to frame / line offset sampling, and the sampling rate is reduced to の of 16.2 Ms / s as shown in FIG. 9B.

[0007] Offset sampling between frames / lines is to invert the phase of sampling for each frame and each line and to perform sampling every other sample. When this sampling is performed, FIG. As shown, every other sample point at a different position is sampled every line, and every other sample point is shifted in the next frame as shown in FIG. Is done.

In this way, the digital signal whose sampling rate is reduced to 1/3 of the original sample signal as a whole is converted into an analog signal by the digital-analog converter, and the frequency bandwidth of the Hi-Vision signal is reduced to about 8M.
The MUSE method of compressing to Hz is adopted. The compressed Hi-Vision signal is FM-modulated and transmitted from a satellite as a Hi-Vision broadcast. To receive the Hi-Vision broadcast, a MUSE decoder that restores the compressed signal is required.

Although the details of the MUSE decoder are omitted, the MUSE decoder first returns the transmitted signal to the baseband, and then sets the sampling rate to 16.2 Ms /.
In s, analog-digital conversion is performed to convert the digital signal. Next, interpolation between frames is performed to double the sampling rate to 32.4 Ms / s. The frame interpolation means that the sampling signal of the current frame and the sampling signal of the immediately preceding frame are alternately sampled at a double sampling rate, so that the sampling signal of the immediately preceding frame is added to the current sampling signal. Is the process of interpolating

The frame interpolation is a process performed to restore the above-described frame / line offset sampling performed by the encoder, and this process will be briefly described with reference to FIGS. As described above, FIG.
(B) and (c) are examples in which two consecutive frames are offset-sampled between frames / lines. When the sampling points of the two frames shown in FIG. It can be seen that the state shown in FIG.

The inter-frame interpolation process is a process for performing such a process. As shown in FIG. 10, the sampling signal of the current frame is converted to A10 as shown in FIG.
, A108, A109, A110,..., And B107, B108, B109,... As shown in FIG. , B107 is sampled in the next sampling, A108 is sampled in the next sampling, and B108 is sampled in the next sampling.
Are sampled one after another, and the sampling rate 32.4 is sampled as shown in FIG.
This is a process for obtaining a sampling signal of Ms / s.

The signal subjected to the frame interpolation processing is then converted to a sampling rate of 48.6 Ms / s, and further subjected to the field interpolation processing to obtain a signal of 48.6 Ms / s.
The signal is restored to a signal having a sampling rate of s / s. The inter-field interpolation process is a process performed to interpolate a sample signal thinned out by inter-field offset sampling performed by an encoder.

The transmission signal format of the MUSE signal is shown in FIG. As shown in this figure, a sampling frequency of 16.2 MHz samples one line at 480 points. These are numbered as sample numbers 1 to 480 as shown in the figure, and 12 samples are assigned to the horizontal synchronization (HD) period, 94 samples are assigned to the C image (color difference signal), and 347 samples are assigned to the Y image (luminance signal).

In the vertical direction, the lines on which the frame pulse is multiplexed are designated as line number 1 and line number 2 and numbered up to line number 1125 hereinafter. The MUSE transmission signal includes the following signals in addition to the Y video, C video, and HD signals, which are multiplexed in the vertical blanking period. (A) Frame pulse signal (b) Control signal (c) Clamp level signal (d) VIT signal (e) Voice / independent data signal

The frame pulse corresponds to a vertical synchronizing signal,
The frame pulse of the line number 1 and the frame pulse of the line number 2 are inverted in phase, and the correlation between the two lines is a correlation that is not present in the video signal, so that the frame pulse can be detected. The clamp level signal is
This signal is used to clamp the neutral level of the color signal in the A / D converter of the MUSE decoder or as an AFC key signal in FM modulation / demodulation. This clamp level signal changes the level of sample numbers 107 to 480 to 128 /
256.

The VIT signal is a vertical interval tast signal, and is a reference signal inserted to equalize the transmission path so as to satisfy the distortion-free condition of the sample value transmission. This VIT signal inserts a single 32.4 MHz pulse into the line with the frame pulse. A negative pulse is inserted into the line number 1 and a positive pulse is inserted into the line number 2. Further, the position of the pulse is set to 32.4 MH for each frame.
Change by one clock of z. Line number 1 of a certain frame
If the pulse is on the left side, line number 1 of the next frame
Then, the position is alternately changed to the right side, and to the left side in line number 1 of the next frame.

By detecting this single pulse, the MUS
The characteristics of the transmission path through which the E signal has passed can be measured. Further, in the sample value transmission, it is necessary to resample at the receiving side at the same phase as that at the time of sampling at the transmitting side in addition to satisfying the distortion-free condition of the transmission path. For this reason,
The positive horizontal sync (HD) signal waveform is set to fall within the video signal amplitude range so that clock reproduction can be performed with high accuracy. Such a synchronous waveform is called a positive-polarity synchronous waveform. By using the positive-polarity synchronous waveform, the entire dynamic range of the transmission path can be allocated to the video signal. Therefore, the S / N ratio of the video signal can be improved by 3 dB.

The control signal is 16.2 MHz 2
The clock width is set to 1 baud and multiplexed as a binary signal. The code format is an extended Hamming (8, 4) code. The control signal is 32 bits in total, and when divided into 4 bits, it becomes 8 blocks. These eight blocks are indicated by numerals 1 to 8 in FIG. 12, and the eight blocks 1 to 8 are transmitted three times. The control signal is line number 5
59 to 563 and line numbers 1121 to 1125. The contents of the 32-bit control signal include inter-field sub-sample phase information, horizontal motion vector information, vertical motion vector information, Y sub-sample phase information (YSS), and C sub-sample phase information. . By the way, the above-described frame interpolation processing has been conventionally performed by a circuit as shown in FIG.

Referring to FIG. 1, reference numeral 100 denotes a frame memory which operates at 32 Ms / s and performs motion vector correction based on motion vector information; 101 denotes a current sample value of an AD converted sampling rate of 16.2 Ms / s; , A frame interpolation switch for interpolating frames by alternately sampling a sample signal of a sampling rate of 32.4 Ms / s delayed by one frame by the frame memory 100.

A timing circuit 102 detects a horizontal synchronizing signal and generates a timing signal. An inverter 103 inverts the output of the timing circuit 102.
4 is a switch 1 for decoding the control signal YSS and
A control decoder 105 for switching 05 selects a timing for sampling by the switch 101 in order to interpolate at a position of the sample signal thinned out by the frame / line offset sampling processing of the encoder.

The operation of the frame interpolation processing circuit shown in FIG. 13 will be described with reference to FIG. The signal shown in FIG. 14 is, for example, a signal of 47 lines. At this time, the control signal YSS is set to “0”. The fact that the YSS is "0" means that the sample point is on the left side in the odd-numbered line. Therefore, the signal at the sample point on the right side of the 47 lines is thinned out and transmitted, and this frame interpolation processing circuit performs interpolation processing on the right side, which is the sampled-out sample point.

16.2M by an A / D converter (not shown)
The current signals A107, A108, 109, and A110 of 47 lines digitized at a sampling rate of s / s.
Is applied to one contact a of the switch 101.
Also, 32.4M output from the frame memory 100
Signals with a sampling rate of s / s are C107, B10
7, C108, B108, C109, B109,... Are applied to the other contact b of the switch 101.

Since the YSS is "0", the switch 101 performs sampling at the timing selected by the switch 105 so as to interpolate the sample signal one frame before to the right of the current signal. The output is A107, B107, A108, B108, A10
9, B109... Are interpolated, and the interpolated signal is extracted from the output of the switch 101.

Note that the timing circuit 102
The switching timing frequency applied to 01 is 16.2M
Hz. Further, one of the illustrated two-frame difference signals is a signal two frames before, and is used for detecting a motion area and removing noise. Also, the frame memory 100
In the signal output from, the signal of the previous frame is interpolated on the left side as described above.
Since the line-to-line offset sampling is performed at a phase inverted for each frame, B107, B10
When the signal of 8... Is the current signal, YSS is “1”, the switch 105 is inverted by the output of the control decoder 104, and the sampling timing of the switch 101 is inverted. .

FIG. 14 shows a case where there is no motion vector, and FIG. 15 shows a case where the motion vector is "1". When the motion vector is 1, the signal of one frame before may be delayed by one sample at a sample rate of 32.4 Ms / s. In the case shown in FIG. 15A, YSS is “0”,
A 47-line signal whose motion vector is "1", and a 47-line current signal A1 digitized at a sampling rate of 16.2 Ms / s by an A / D converter (not shown).
07, A108, 109, A110,... Are applied to one contact of the switch 101.

Further, since the motion vector is corrected and delayed by one sample from the frame memory 100, the output signal of the sampling rate of 32.4 Ms / s is output from C ----, B107, C107, B108, C
.., B109...
01 is applied to the other contact. Switch 101 is YS
Since S is “0”, sampling is performed at the timing selected by the switch 105 to interpolate the sample signal one frame before to the right of the current signal.
The output of 1 (SW1) is A107, B107, A108,
B108, A109, B109..., And the signal subjected to the normal motion compensation and the frame interpolation processing is the switch 1
01 is taken from the output.

As described above, since the motion vector correction is performed in the MUSE system, when interpolating frames by the decoder, the signal of the previous frame is corrected by correcting the sample position using the motion vector in the control signal. . In this case, when the correction amount of the motion vector becomes an odd multiple of 32.4 Ms / s, the left and right sides of the sample point at 32 Ms / s are reversed before and after the correction, so that the current input of the interpolation partner is If the signal inverts the YSS phase as in a normal sequence, it becomes a signal at the same sample point, and cannot be interpolated alternately.

Therefore, the correction amount is 32.4 Ms.
When / s is an odd multiple, the current signal is subjected to frame / line offset sampling without inverting the YSS phase on the encoding side, and motion vector correction is performed on the decoder side as shown in FIG. By doing
It is possible to interpolate alternately with the signal of one frame before the left and right sides of the sample point are reversed. Since such a correction is performed, the case 1 shown in FIG.
The YSS before the frame is also “0”, and the frame memory 1
Signal C107, C1 one frame before output from 00
08,..., The signal of the previous frame is interpolated on the right side.

Next, FIG. 15B shows a case where the motion vector is "1" and the YSS is "1". The signal shown in this figure is also a 47-line signal, and the 47-line current signal A107, A108, 10 digitized at a sampling rate of 16.2 Ms / s by an A / D converter (not shown).
9, A110... Are applied to one contact of the switch 101. In addition, since the frame memory 100 outputs the signal having a sampling rate of 32.4 Ms / s with a delay of one sample so as to correct the motion vector amount “1”, the signal having the sampling rate of 32.4 Ms / s is B −−−, C107, B107, C
, B108, C109,..., And this signal is applied to the other contact of the switch 101.

Since the YSS is "1" in the switch 101, sampling is performed at the timing selected by the switch 105 so as to interpolate the sample signal one frame before to the left of the current signal. The output is B ---, A107, B107, A108, B10
8, A109, B109,..., And the signal subjected to the normal motion correction and the frame interpolation processing is applied to the switch 101.
From the output of Also in the case shown in this figure, since the correction is performed on the encoder side, the control signal YSS of the previous frame is also “1”, and the frame memory 1
00 is the signal C10 of the previous frame.
7, C108... Are interpolated on the left side.

[0031]

However, based on the currently transmitted control signal YSS, it is determined whether the current signal to be written to the frame memory 100 is to be inserted into the left sample point or the right sample point.
For example, if the control signal YSS is fixed for some reason, according to the frame interpolation processing circuit shown in FIG. 13, only the current signal is written to one sample point and the other signal is written to the other sample point. Is the frame memory 100
, The previous signal of the output is repeatedly written, so that the previous signal remains every other sample signal and the previous image remains in the form of dots.

This will be described with reference to FIGS. FIG. 16 shows that the control signal YSS is "1".
Shows the interpolating process when the frame is fixed to.
For example, current signals A107, A108, 109, A110,... Of 47 lines digitized by an A / D converter (not shown) at a sampling rate of 16.2 Ms / s.
Is applied to one contact of the switch 101. Also,
32.4 Ms / s output from the frame memory 100
C107, B107, C1 at the sampling rate of
08, B108, C109, B109... Are applied to the other contact of the switch 101.

Since the YSS is "1", the switch 101 alternates the signal applied to both contacts at the timing selected by the switch 105 so as to interpolate the sample signal from the frame memory 100 to the left of the current signal. And the sampling output of the switch 101 (SW1) is C107, A107, C108, A108, C
109, A109... Looking at the result of this frame interpolation processing, the signal B107,
B108,... Indicate that the interpolation processing has not been performed.

Further, when the control signal YSS is "1"
FIG. 16 shows the operation of the frame interpolating circuit when 47 lines of the next frame are transmitted while being fixed to
It is shown in (b). In this case, the current signal Z107 of the 47th line of the next frame digitized by an A / D converter (not shown) at a sampling rate of 16.2 Ms / s.
Z108, Z109, Z110 ... are switches 101
Is applied to one of the contacts. Also, the frame memory 10
The signals having a sampling rate of 32.4 Ms / s output from 0 are C107, A107, C108, A108,
Are applied to the other contact of the switch 101.

The switch 101 receives the control signal YSS
Is still “1”, and the sampling is performed at the timing selected by the switch 105 so as to interpolate the sample signal output from the frame memory 100 on the left side of the current signal. Therefore, the output of the switch 101 (SW1) is C107, Z107, C108, Z108, C109,
Z109 ... Looking at the result of this frame interpolation processing, the signals A107, A108,
.. Indicate that no interpolation processing has been performed, and that the previous sample signals C107, C108,.

Although the control signal YSS is not fixed as a MUSE signal as described above, it is not normal for the MUSE signal to be actually interrupted or a special reproduction such as a one-frame still of the MUSE signal recorded on the laser disk. And so on. Therefore, an object of the present invention is to provide a frame interpolation processing circuit in which dot-shaped interference does not occur even when the control signal YSS is fixed.

[0037]

In order to achieve the above object, the present invention does not use a frame memory cyclically. Alternatively, according to the present invention, an input signal and a signal read from the frame memory are multiplexed and read into the frame memory at a constant cycle, and only the signal two frames before is output to the output side of the frame memory, and one frame is output. The previous signal is provided with a demultiplexer for returning to the input of the frame memory.

[0038]

According to the present invention, it is possible to provide a frame interpolation processing circuit in which dot-shaped interference does not occur even when the control signal YSS is fixed. Further, it is possible to realize a frame interpolating circuit in which dot-shaped interference does not occur due to components that are not much different from the number of components of the conventional processing circuit.

[0039]

FIG. 1 shows a first embodiment of the present invention. In this figure, reference numeral 1 denotes a first frame memory including a frame memory 1-1 operating at a sample rate of 16 Ms / s and a motion vector correction unit 1-2, and 2 denotes a 16 Ms / s cascaded to the first frame memory. The second frame memory 3 composed of a frame memory 2-1 operating at a sample rate of s and a motion vector correction unit 2-2 has a clock of 32.4 MHz applied thereto, and has an odd number of motion vectors. This is a latch circuit that performs correction.

Further, 4 is a frame interpolation switch (SW2) whose sampling timing is switched according to a control signal, 5 is a switch (SW3) which is switched to the latch 3 output side when the motion vector amount is an odd number,
6 is a timing circuit for detecting a horizontal synchronizing signal to generate a timing signal, 7 is a control decoder for decoding the control signal YSS and switching the switch 9,
8 is an inverter for inverting the phase of the timing output by the timing circuit 6, 9 is an output of the timing circuit 6,
This is a switch (SW0) for selecting whether the output is inverted.

The operation of this circuit will be described with reference to FIG. FIG. 2A shows that the control signal is “0”.
Shows the state of operation by exemplifying a signal of 47 lines when there is no motion vector amount. 47-line current signals A107 and A10 digitized by an A / D converter (not shown) at a sampling rate of 16.2 Ms / s
8, 109, A110... Are switches 4 (SW2).
And the input of the first frame memory 1.

The signal B1 having a sampling rate of 16.2 Ms / s output from the first frame memory 1
07, B108, B109... Are signals one frame before the current signal, are applied to the input of the second frame memory 2, and one contact of the switch 5 (SW3) and the latch circuit 3 Is applied to The output of the switch 5 is applied to the other contact of the switch 4,
(SW2) includes the sample signal B10 one frame before the current signal on the right side of the current signal because the control signal YSS is “0”.
7, B108... To be interpolated.
The two signals applied at the timing selected in 0) are alternately sampled. As a result, switch 4 (SW2)
Are A107, B107, A108, B108, A
109, B109..., And the signal subjected to the frame interpolation processing is extracted from the output of the switch 4 (SW2).

The output of the first frame memory 1 is input to the second frame memory 2 and further delayed by one frame to produce a two-frame difference signal between the output signal of the second frame memory 2 and the current signal. Can be obtained. Since the clock applied to the latch circuit 3 is 32.4 MHz output from the timing circuit 6, the latch circuit 3 can delay one sample signal having a sample rate of 32.4 Ms / s. This latch circuit 3
Can be configured by connecting, for example, eight D-type flip-flops in parallel.

Next, FIG. 2B shows a state of the operation by exemplifying a signal of 47 lines when the control signal is "0" and the motion vector amount is "2". In this case, a 47-line current signal A1 digitized by an A / D converter (not shown) at a sampling rate of 16.2 Ms / s
., 07, A108, 109, A110... Are connected to one contact of the switch 4 (SW2) and the first frame memory 1.
Is applied to the input.

The first frame memory 1 outputs a signal one frame before the motion vector corrected, but since the motion vector correction is in units of 32.4 Ms / s, one signal is output.
At the sampling rate of 6.2 Ms / s, the motion vector “2” corresponds to “1”, so the signal corrected as the delay amount “1” of the frame memory 1 by the motion vector correction unit 1-2 is shown in FIG. B as shown in FIG.
---, B107, B108... This signal is applied to the input of the second frame memory 2 and to one contact of the switch 5 (SW3) and the latch circuit 3.

The output of the switch 5 is applied to the other contact of the switch 4, and the switch 4 (SW2) switches the corrected sample signal one frame before to the right of the current signal because the control signal YSS is "0". B ---, B10
7, B108... To be interpolated.
The signal applied at the timing selected in 0) is sampled. Therefore, the output of the switch 4 (SW2) is A107, B ---, A108, B107, A109,
B108..., And the signal subjected to the normal motion compensation and subjected to the frame interpolation processing is extracted from the output of the switch 4. No interference occurs in which the previous image remains in the form of a dot.

Next, FIG. 2 (c) shows the operation state of a 47 line signal when the control signal is "0" and the motion vector amount is "1". In this case, a 47-line current signal A1 digitized by an A / D converter (not shown) at a sampling rate of 16.2 Ms / s
., 07, A108, A109, A110,... Are applied to one contact of the switch 4 (SW2) and the input of the first frame memory 1.

When there is a normal motion vector correction amount, the signal of one frame before the motion vector correction is output from the first frame memory 1. In this case, the motion vector correction amount is "1". Therefore, the motion vector correction unit 1-2 of the first frame memory 1 outputs the data as it is without performing the correction, and the latch circuit 3 outputs the motion vector amount “1”.
Is corrected. Therefore, the output signal of the latch circuit 3 selected by the switch 5 (SW3) is B--, B107, B107 as shown as the latch 3 output in FIG.
108.

This signal is applied to the other contact of the switch 4. Then, since the control signal YSS is “0”, the switch 4 (SW2) outputs the corrected sample signals B ----, B10 one frame before to the right of the current signal.
7, B108... To be interpolated.
The signal applied at the timing selected in 0) is sampled. Therefore, the output of the switch 4 (SW2) is A107, B107, A108, B108, A109,
B109..., And a signal that has been normally motion-corrected and subjected to frame interpolation processing is extracted from the output of the switch 4.

Next, the control signal YSS becomes "1".
FIG. 3A shows an example of a signal of 47 lines when the motion vector amount is “1”. In this case, the current signals A107, A108, 109, A110,... Of 47 lines digitized at a sampling rate of 16.2 Ms / s by an A / D converter (not shown) are:
The voltage is applied to one contact of the switch 4 (SW2) and the input of the first frame memory 1.

Also, since the motion vector correction amount is "1" from the first frame memory 1, the motion vector correction unit 1-2 of the first frame memory 1 outputs the correction without performing the correction. Then, the latch circuit 3 corrects the motion vector amount “1”. The outputs of the latch circuit 3 selected by the switch 5 (SW3) are B ---, B107, B108,... Shown as the latch 3 outputs in FIG.

This signal is applied to the other contact of the switch 4. Then, since the control signal YSS is "1", the switch 4 (SW2) outputs the corrected sample signals B ---- and B10 one frame before to the left of the current signal.
7, B108... To be interpolated.
The signal applied at the timing selected in 0) is sampled. Therefore, the output of the switch 4 (SW2) is B--, A107, B107, A108, B10
8, A109, B109,..., And the signal subjected to the frame interpolation processing by the signal whose motion vector has been normally corrected is extracted from the output of the switch 4.

Next, the control signal YSS becomes "0".
FIG. 3A shows an example of a signal of 47 lines when the motion vector amount is “−1”. In this case, an A / D converter (not shown) uses 16.2 Ms / s
The current signals A107, A108, 109, A110,... Of 47 lines digitized at the sampling rate of
Is applied to one contact of the switch 4 (SW2) and the input of the first frame memory 1.

Since the motion vector correction amount is "-1", the first frame memory 1 outputs a signal advanced by one sample from the first frame memory 1 by the motion vector correction unit 1-2. That is, the corrected signal is 3
When converted to a sampling rate of 2.4 Ms / s, as shown in FIG.
2 "is corrected, and the signal corrected in this manner is further applied to the latch circuit 3 so that the motion vector amount" 1 "
Is corrected. Then, the output signal of the latch circuit 3 taken out from the switch 5 (SW3) eventually becomes “−”.
1 "has been corrected, and B107, B108, B109... Shown as latch 3 outputs in FIG.
Becomes

This signal is applied to the other contact of the switch 4. Then, since the control signal YSS is “0”, the switch 4 (SW2) outputs the corrected sample signals B107 and B10 one frame before to the right of the current signal.
8, B109... To be interpolated.
The signal applied at the timing selected in 0) is alternately sampled. For this reason, the output of the switch 4 (SW2) is B107, A107, B10 as shown in the figure.
8, A108, B109, A109, B110..., And the signal subjected to the frame interpolation processing by the signal whose motion vector has been normally corrected by “−1” is extracted from the output of the switch 4.

Further, it will be described with reference to FIG. 3D that the previous signal is not circulated even if the control signal YSS is fixed in the frame interpolation processing circuit shown in FIG. In this figure, the current signal is A as shown in the figure.
107, A108, A109,...
B107, B108, B10 from the frame memory 1
9 are output. Since the first frame memory 1 is not connected so that the signal is circulated, the signal of one frame before is output from the first frame memory 1 regardless of the control signal YSS.

Therefore, the control signal YSS is "1".
, The output of the switch 4 (SW2) is B107, A107, B108, A10 as shown in FIG.
8, B109, A109,..., And the interpolated output is obtained temporarily, and the interference that the previous image remains in a dot shape as in the related art does not occur.

Next, a second embodiment of the present invention is shown in FIG.
In this figure, reference numeral 20 denotes a frame memory including a frame memory 20-1 operating at a sample rate of 32 Ms / s and a motion vector correction unit 20-2;
Hz, a latch circuit for performing correction when the motion vector amount is an odd number, a frame interpolation switch (SW2) 4 for sampling at a timing corresponding to the control signal YSS, and a motion for correction 5 A switch (SW3) that is switched to the output side of the latch 3 when the vector amount is an odd number, 6 is a timing circuit that detects a horizontal synchronizing signal and generates a timing signal, and 7 is a control decoder that decodes the control signal YSS and switches the switch 9. It is.

Further, 8 is an inverter for inverting the phase of the timing output of the timing circuit 6, 9 is a switch (SW0) for selecting the output of the timing circuit 6 or the inverted output, and 21 is the output of the frame memory 20. A latch circuit for latching only the signal one frame before,
2, a latch circuit for latching the current signal; 23, a switch for multiplexing the current signal and the signal returned to the frame memory 20 by sampling them at a predetermined timing;
Reference numeral 4 denotes a switch that operates as a demultiplexer that selectively outputs only a signal two frames before the multiplexed signal output from the frame memory 20.

The frame interpolating circuit according to the second embodiment multiplexes the current signal and the signal of the previous frame one by one in a time-series manner by the switch 23 to obtain a sample signal of 32.4 Ms / s. Is written in. Therefore, the switch 23 (SW4) and the switch 24 (SW
Switching is performed by a constant output timing signal output from the timing circuit 6 in synchronization with 5). The current signal and the output of the frame memory 20 have a timing relationship as shown in FIG. 5, and the switch 23 (SW4)
The signal multiplexed by sampling both signals is shown as SW4 output in FIG. The output of the switch 24 is written to the frame memory 20.

On the other hand, the output of the frame memory 20 is 16.
The signal is latched by the latch circuit 21 with a clock of 2 MHz, and is output at the timing shown as the output of the latch circuit 21 in FIG. In this case, assuming that there is no motion vector amount, the output of the latch circuit 21 is taken out of the switch 5 as it is and applied to one contact of the switch 4 for performing frame interpolation.

The current signal is also applied to the latch circuit 22 to adjust the timing to the output of the latch circuit 21.
The switch is connected to the other contact of the switch 4 at the timing shown as the output of the latch 22 in FIG. now,
When the control signal YSS is "0", the switch 4
(SW2) alternately samples the signal applied so as to interpolate the signal one frame before to the left of the current signal, so that A107 and B10 are output as shown in the SW2 output shown in FIG.
7, A108, B108, A109, B109,..., And signals interpolated normally between frames are obtained.

In this embodiment, the frame memory 20 is configured to feed back a signal. However, the switching timing of the switch 23 (SW4) and the switch 24 (SW5) is always constant regardless of the control signal TSS. , Only the signal one frame before is fed back, and the signal before that does not go around the frame memory 20. Therefore, the interference that the previous image remains on the dot does not occur.

The signal two frames before is shown in FIG.
As shown as an output, the signal is output from the switch 24 at a predetermined cycle and used as a two-frame difference signal together with the current signal. Note that 16.2 MHz and 32.4 supplied to the latch circuits 3, 22, and 23 are provided.
Both MHz clocks are supplied from the timing circuit 6, and the clocks are synchronized. In this example, the case where there is no motion vector amount is shown. However, the operation when there is a motion vector amount is the same as that of the frame interpolation processing circuit shown in FIG.

Next, FIG. 6 shows a frame interpolation apparatus according to a third embodiment. In this figure, 31 is 32 Ms /
s field memory operating at s sample rate, 32
Is a field memory consisting of a field memory 32-1 operating at a sample rate of 32 Ms / s and a motion vector correction unit 32-2, 3 is supplied with a 32.4 MHz clock, and is corrected when the motion vector amount is an odd number. , A frame interpolating switch (SW2) for sampling at a timing corresponding to the control signal, a switch (SW3) for switching to the latch 3 output side when the motion vector amount to be corrected is an odd number, 6
Is a timing circuit for detecting a horizontal synchronizing signal and generating a timing signal, and 7 is a control signal decoder for decoding the control signal YSS and switching the switch 9-1.

Further, 8 is an inverter for inverting the phase of the timing output of the timing circuit 6, 9-1 is a switch for selecting between the output of the timing circuit 6 and the inverted output, and 9-2 is a switch for one field before. A switch for selecting a timing signal based on the output of a latch circuit 36 for outputting a control signal, 21 is a latch circuit for latching only the signal of one frame before in the output of the field memory 32, 22 is a latch circuit for latching the current signal, 23 Is a switch for multiplexing by sampling the current signal and the signal returned to the field memory 31.

A switch 24 operates as a demultiplexer for selecting and outputting only a signal two frames before the signal output from the multiplexed field memory 32, and a switch 33 outputs one output from the switch 37 with an inverted clock. A latch circuit for latching; 34, a latch circuit for latching the other output from the switch 37; 35, a latch circuit for latching the output of the latch circuit 33 in synchronization with the latch circuit 34; 36, a control signal YS one field before;
A latch circuit for latching S, a switch 37 is switched in synchronization with the switch 23, and a switch for separating the output signal of the field memory 31 for each sample, and a 38 is field-delayed at a timing corresponding to the control signal YSS one field before. A frame interpolation switch for sampling a signal.

The third embodiment is a circuit for obtaining an interpolated frame-delayed signal which is field-delayed. The present signals A107, A108, A109... And the outputs C ---, B107 of the field memory 32 are used. , C107, B
.. Have the timing relationship shown in FIG. 7, and the switch 24 (SW4) samples these signals and multiplexes them into the SW4 output A shown in FIG.
107, B107, A108, B108,... The output of the switch 4 is written to the field memory 31.

On the other hand, the signal of one frame before output from the field memory 32 is latched by the latch circuit 21 by a clock of 16.2 MHz.
Are output from the latch circuit 21 at timings indicated as outputs B107, B108,... In this case, assuming that there is no motion vector amount, the output of the latch circuit 21 is taken out of the switch 5 without correction by the latch circuit 3 and applied to one contact of the switch 4 for performing frame interpolation.

The current signal is also applied to the latch circuit 22 to adjust the timing to the output of the latch circuit 21.
The latch 22 is connected to the other contact of the switch 4 at timings shown as outputs A107, A108,... In FIG. Now, the current control signal YS
If S is "0", the switch 4 (SW2) samples the signal applied so as to interpolate the signal one frame before to the right of the current signal, so that the output of the switch 4 is the SW2 output A107 shown in FIG. , B107, A108, B10
8, A109, B109,..., And a signal interpolated between frames can be obtained.

Further, the signal delayed by one field, which is the output of the field memory 31, is demultiplexed by a switch 37 which is switched in synchronization with the switch 23, and one of the signals is applied to a latch circuit 33 operated by an inverted clock. The output a10 of the latch 33 shown in FIG.
., And the other signal is applied to the latch circuit 34 and b107, b10 shown in FIG.
8... And the latch circuit 3
The output of No. 3 is further applied to the latch circuit 35, and the timing of a107, a108,... Shown in FIG.

Here, assuming that the control signal YSS one field before is "0", the control signal YSS is latched by the latch circuit 36 supplied with a field pulse as a clock signal. The output from the latch circuit 36 is delayed by one field, the switch 9-2 is switched by this output, and the signal to which the switch 38 is applied is alternately sampled by the timing signal from the selected timing circuit 6.

At this time, since the control signal YSS is "0", the signal a1 delayed by one field
., The right sampling timing is set so that signals b107, b108,... One frame before this signal are interpolated. As a result, the output of the switch 38 (SW7) becomes a107, b107, a108, b108,.
・ It becomes. According to the third embodiment, a frame interpolation signal delayed by one field can be obtained from the output of the switch 38, and this signal is thereafter applied to a field interpolation filter to thereby perform field interpolation. Can be used.

The clocks supplied to the latch circuit 3, the latch circuit 21, the latch circuit 22, the latch circuit 33, the latch circuit 34, the latch circuit 35, and the latch circuit 36 are supplied from the timing circuit 6, and these clocks are supplied. Synchronized with each other. In this example, the case where there is no motion vector amount is shown. However, the operation when there is a motion vector amount is the same as that of the frame interpolation processing circuit shown in FIG.

[0075]

Since the present invention is constructed as described above, M
When the sub-sample sequence is disturbed due to interruption of the USE signal or special reproduction such as one-frame still of a laser disk, the previous sample signal is not circulated and remains in the frame memory for inter-frame interpolation. No interference on the dots occurs. Further, the frame interpolation processing circuit of the present invention can be configured without much difference from the number of circuit elements configuring the conventional circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frame interpolation processing circuit according to the present invention.

FIG. 2 is a diagram illustrating an operation state of a frame interpolation processing circuit;

FIG. 3 is a diagram illustrating an operation state of a frame interpolation processing circuit;

FIG. 4 is a block diagram of another frame interpolation processing circuit according to the present invention;

FIG. 5 is a diagram illustrating an operation state of a frame interpolation processing circuit;

FIG. 6 is a block diagram of another interpolating circuit according to the present invention;

FIG. 7 is a diagram illustrating an operation state of a frame interpolation processing circuit;

FIG. 8 is a diagram showing the principle of the MUSE system.

FIG. 9 is a diagram showing the principle of the MUSE system.

FIG. 10 is a diagram illustrating the principle of frame interpolation processing.

FIG. 11 is a diagram illustrating a transmission format of a MUSE signal.

FIG. 12 is a diagram illustrating a transmission format of a control signal.

FIG. 13 is a block diagram of a conventional frame interpolation processing circuit.

FIG. 14 is a diagram illustrating the operation of a conventional frame interpolation processing circuit.

FIG. 15 is a diagram illustrating the operation of a conventional frame interpolation processing circuit.

FIG. 16 is a diagram illustrating the operation of a conventional frame interpolation processing circuit.

[Explanation of symbols]

1, 1-1, 2-2, 20, 100 Frame memory 1-2, 2-2, 20-2, 32-2 Motion vector correction unit 3, 21, 22, 33, 34, 35, 36 Latch Circuit 4, 101 Frame interpolation switch 5, 9, 9-1, 9-2, 23, 24, 37, 38,
105 Switch 6, 102 Timing circuit 7, 104 Control signal decoder 8, 103 Inverter 31, 32, 32-1 Field memory SW0, SW1, SW2, SW3, SW4, SW5, S
W6, SW7 switch

Claims (6)

(57) [Claims] An A / D converter for converting a transmitted MUSE signal into a digital signal, and a cascaded first to which an output of the A / D converter is applied.
And a second frame memory, by alternately sampling a sample signal of one frame output from the A / D converter and a sample signal of one frame delayed by one frame by the first frame memory. A frame interpolating switch for making a sample signal of one frame at a double sampling rate, wherein a sampling phase of the frame interpolating switch is
The inverted signal is inverted according to the control signal YSS representing the decoded luminance signal sub-sampling phase.
A MUSE decoder for preventing a residual image from being obtained, wherein a sample signal of two frames before is obtained from the frame memory of (1). 2. A motion vector correction section is provided in the first and second frame memories, and one contact of the interpolating switch is connected to the first and second frame memories.
A motion vector correction latch circuit is provided between the output of the frame memory and the even number portion of the motion vector correction amount is corrected by the motion vector correction section, and the odd portion of the motion vector correction amount is corrected by the latch circuit. 2. The MUSE decoder according to claim 1, wherein the remaining image is prevented. 3. An A / D converter for converting a transmitted MUSE signal into a digital signal, and alternately sampling a current sample signal output from the A / D converter and a sample signal one frame before. A first switch means for multiplexing at a sampling rate twice as high as the current sample signal, a frame memory for reading the output of the first switch means, a sample signal one frame before the output of the frame memory and two frames Second switch means for separating a previous sample signal from the previous sample signal; and alternately sampling the current sample signal of one frame and the sample signal of one frame before one frame outputted from the frame memory to thereby obtain the current sample. A frame interpolating switch for making a sample signal of one frame at a sampling rate twice as high as the signal The sample signal of one frame before separated by the second switch means is supplied to one contact of the first switch means, and the sampling phase of the frame interpolation switch is
A MUSE decoder in which image reversal is prevented by performing inversion control according to a control signal YSS representing a decoded luminance signal sub-sampling phase and obtaining a sample signal two frames before from the second switch means. 4. A motion vector correction unit is provided in the frame memory, and a motion vector correction latch circuit is provided between one contact of the interpolating switch and an output of the frame memory. 4. The motion vector correction section corrects an even number portion of the motion vector, and corrects an odd number portion of the motion vector correction amount by the latch circuit.
A MUSE decoder that prevents the described image remaining. 5. An A / D converter for converting a transmitted MUSE signal into a digital signal, and alternately sampling a current sample signal output from the A / D converter and a sample signal one frame before. A first switch means for multiplexing at a sampling rate twice as high as the current sample signal, a first field memory for reading an output of the first switch means, and a second cascade-connected to the first field memory. Second field memory; second switch means for separating the sample signal of one frame before and the sample signal of two frames before from the output of the second field memory; the current sample signal of one frame; The current sample is obtained by alternately sampling the sample signal of one frame before one frame output from the second field memory. A first frame interpolating switch for making a sample signal of one frame at a sampling rate twice as high as that of the signal, a sample signal one field before the output of the first field memory, and one frame before the sample signal. A third switch means for separating the signal of the first switch from the first switch, and a sample signal of one frame outputted from the third switch and a sample signal of the other frame outputted from the third switch alternately. And a second interpolating switch that converts the current sample signal into a sample signal of one frame at a sampling rate twice as high as that of the current sample signal. A signal is supplied to one contact of the first switch means, and a sampler of the first frame interpolation switch is provided. The grayed phase, and inversion control according to the control signal YSS representative of the decoded luminance signal subsampling phase, the sampling phase of the interpolating switch in between said second frame,
The control signal Y immediately before the decoded field
A MUSE decoder in which image retention is prevented, wherein inversion control is performed in accordance with SS and a sample signal two frames before is obtained from the second switch means. 6. A motion vector correction unit is provided in said second field memory, and one contact of said frame interpolation switch is connected to said second field memory.
A latch circuit for motion vector correction is provided between the latch circuit and the output of the field memory, and the even number portion of the motion vector correction amount is corrected by the motion vector correction section, and the odd portion of the motion vector correction amount is corrected by the latch circuit. 6. The method according to claim 5, wherein
A MUSE decoder that prevents the described image remaining.