JP2557474B2 - Static display control circuit of MUSE decoder - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a static display control circuit of a MUSE decoder installed in a MUSE type television receiver.

(Prior art) MUSE (Multiple Sub), which is currently the most promising candidate for high-definition television (HDTV) systems that use broadcasting satellites
-Nyquist Sampling Encoding) television broadcasting experiments have started.

With this MUSE method, a luminance signal with a bandwidth of 22 MHz and a bandwidth of 7
In order to frequency-modulate a baseband signal including a color signal of MHz and to transmit this by using one channel of a satellite broadcasting bandwidth of 27 MHz, the baseband signal is band-compressed to about 8 MHz. This band compression is performed by thinning out a complete sampling point group extracted from the original video signal according to a predetermined rule. At the time of thinning out the sampling points, the inter-field offset sampling is performed by utilizing the physiological characteristic of the viewer that the resolution in the diagonal direction on the screen is lower than that in the vertical and horizontal directions. In addition, the physiological characteristic of the viewer that the image quality is not so deteriorated even if the resolution is slightly lowered in a moving area is also used.

In the decoder on the receiving side, the sampling points thinned out by the encoder on the transmitting side are reproduced based on the sampling point groups before and after actually transmitted and received, and are inserted in the missing portions. The process of reproducing and inserting this missing sampling point is
This is called interpolation processing. The interpolation processing includes field interpolation performed by using adjacent sampling point groups in the same field and interfield interpolation performed by using sampling point groups at corresponding positions of adjacent fields. In this interpolation process, a moving area and a still area are detected from the reception screen, field interpolation is performed on the moving area, and interfield interpolation is performed on the still area. Interframe interpolation processing is also used as a special type of interfield interpolation.

The paper of the present inventors entitled "MUSE Decoder" published in NEC Technical Report Vol.41 No.3 / 1988 describes the MUSE decoder shown in the block diagram of FIG.

In the MUSE decoder of FIG. 3, the video signal input to the input terminal IN is converted into a digital video signal by the A / D conversion unit 1, and pre-processing such as de-emphasis is performed by the pre-processing unit 2. Interpolation unit 4 performs interframe interpolation and noise reduction processing. The video signal for which the inter-frame interpolation and the noise reduction processing have been completed is processed by the luminance signal processing unit 10
Then, after undergoing various processing such as interpolation processing, frequency conversion, and filtering for each of the luminance signal and the color signal in the color signal processing unit 20, the matrix signal is converted into the three primary color signals of R, G, B, The D / A converters 9a to 9c convert the analog R, G, B signals and output them to the output terminals O _{1 to} O ₃ .

As shown in FIG. 4, the inter-frame interpolating unit 4 in FIG.
A frame memory including two-stage field memories 41 and 42, arithmetic circuits 43 and 44, a non-linear circuit 45, and a switch 46 are provided.

The signal output from the adder circuit 44 to the output terminal O is the fifth signal.
As shown in FIG. 3A, the pixel signal “0” of the current field whose noise has been reduced and the pixel signal “−2” two fields before (one frame before) the current field are in pixel (dot) units. It is interpolated between frames by being arranged on the line while alternating with. This signal (A) is supplied to the field memory 41 connected in two stages in cascade.
As shown in FIG. 5 (C), the signal C further delayed by 2 fields (1 frame) is supplied to one input terminal of the subtraction circuit 43 and the other input terminal by passing through 42 and 42. Is subtracted from the signal of the current field supplied to. As a result, the subtraction circuit 43 subtracts the signal of four fields before (two frames before) from the signal of the current field and the signal of two fields before (one frame before) from the signal of the current field. A signal in which the generated signal is alternately arranged in the pixel direction in the line direction is output.

The switch 46, which is switched for each pixel, passes the non-linear circuit 45 for the output of the subtraction circuit 43, which is obtained by subtracting the signal of four fields before from the signal of the current field,
Further, the signal obtained by subtracting the signal two fields before from the signal of the current field is directly supplied to one input terminal of the adder circuit 44 without passing through the non-linear circuit 45. switch
The signal supplied to one input terminal of the adder circuit 44 via 46 is added to the signal of the current field supplied to the other input terminal. The non-linear circuit 45 regards the output of the subtraction circuit 43 as a noise component included in a static area in the screen, and selectively passes only a small amplitude component. Therefore, the adder circuit 44 outputs the current field signal "0" from which the noise component extracted by the nonlinear circuit 45 is removed from the current field signal. From the adder circuit 44, one pixel is deviated from the output "0" by one pixel, and it is returned to the signal at the time of reading from the field memory 42 through subtraction and addition with the current field signal in the arithmetic circuits 43 and 44 (two fields before ( The signal "-2" of one frame before) is also output.

The output of the interframe interpolating unit 4 is the luminance signal processing unit in the subsequent stage.
10 and the color signal processing unit 20. Luminance signal processor 10
Is a static area processing system including a low-pass filtering circuit 11, a frequency conversion circuit 12 and an inter-field interpolation circuit 13, and a motion area processing system including a sampling switch 14, a field interpolation circuit 15 and a frequency conversion circuit 16. Is separated into.
The outputs of the still area processing system and the moving area processing system in the luminance signal processing unit 10 are combined by the adaptive combining unit 17 at a combining ratio according to the result of motion detection by the motion detection circuit 5.

The sampling switch 14 that opens and closes at the pixel frequency
By blocking passage of the pixel signal of two fields before (one frame before) interpolated by the inter-frame interpolating unit 4 at the previous stage, the noise reduction processed signal “0” as shown in FIG. 6 (A) is obtained. Is supplied to the inter-field interpolation unit 15.

(Problems to be Solved by the Invention) In the above-mentioned conventional MUSE decoder, the frame memory of the interframe interpolating unit 4 (the field memories 41 and 42 having a two-stage configuration)
It has been planned to add a still display function of making the display screen stand still at a desired time by forming a loop between the input and output.

However, when a loop is formed between the input and output of the frame memory of the inter-frame interpolating unit 4 to make the display screen stationary, if there is motion between adjacent fields, flicker of the field cycle occurs in the still image. There is a problem.

That is, the stationary display mode is entered by fixing the sampling switch 46 of the inter-frame interpolating unit 4 of FIG. 4 to the lower side and removing the non-linear circuit 45. At this point, the signal as shown in FIG. 5 (A) is written in the field memory 41, and the field memory 42 is delayed by one field as shown in FIG. 5 (B). The signal is written. The signals shown in FIGS. 5A and 5B are passed through the sampling switch 14 and are repeatedly supplied to the field interpolator 15 as signals shown in FIGS. 6A and 6B, respectively. , A still image that has been subjected to field interpolation processing.

Therefore, if there is a change between the signal "0" of the current field and the signal "-1" of the previous field, flicker of the field period occurs on the still display screen, which causes a problem of image quality deterioration.

Also, if a field memory dedicated to still display is added, the amount of hardware increases, which raises the price of the MUSE decoder.

(Means for Solving the Problem) The static display control circuit of the MUSE decoder according to the present invention is
It is used as a memory for the temporal filter during periods other than the static display period, and is output from the field interpolation unit in the motion region processing system common to the luminance signal processing unit and the chrominance signal processing unit immediately before the start of static display, or there Latest 1 entered in
A memory for holding a screen for fields and reading and outputting the latest one-field screen held immediately before the start of the still display for each field within the still display period, and a luminance signal only by the output of the motion area processing system. And means for instructing the adaptive synthesizing unit to synthesize the color signals.

(Operation) The still display control circuit of the present invention accumulates the latest one-field screen output from the field interpolation circuit in the memory, and periodically reads out the screen, so that the motion between fields can be prevented. Even if it exists, a high-quality still image without flicker can be displayed.

In addition, since the latest one-field screen output from or input to the field interpolation unit is stored in the memory of the temporal filter, which is always unnecessary during still display, it is dedicated to still display. No memory is needed, and the MUSE decoder is cheaper.

 Hereinafter, further details of the present invention will be described together with examples.

(Embodiment) FIG. 1 is a block diagram showing an example of a configuration of a main part of a MUSE decoder including a still display control circuit according to an embodiment of the present invention.

In this MUSE decoder, IN is an input terminal for a received analog video signal, 1 is an A / D converter, 2 is a preprocessor, 4 is an interframe interpolator, 5 is a motion detector, 6 is a sync detector, 7
Is a control signal detection unit, 8 is a matrix unit, and 9 is D /
An A conversion unit, OUT _{1 to} OUT ₂ are output terminals for processed R, G, B video signals, 10 is a luminance signal processing unit, and 20 is a color signal processing unit.

The MUSE video signal appearing at the input terminal IN is the A / D converter 1
Is converted into a 10-bit wide digital signal at a sampling frequency of 16.2MHz. The A / D converted digital video signal is subjected to pre-processing such as non-linear de-emphasis and inverse gamma correction in the pre-processing unit 2.
The sync detector 6 extracts various sync signals from the A / D-converted digital video signal, and extracts the sync signals from the extracted sync signals.
Regenerates 16.2MHz, 32.4MHz, 48.6MHz clock signals and supplies them to each part. The control signal extraction unit 7 extracts a control signal including a motion vector signal and sub-sample phase information from the A / D converted digital video signal, and extracts these control signals from the inter-frame interpolation unit 4, the luminance signal processing unit 10,
It is supplied to the color signal processing unit 20 and the like. Although not shown, the MUSE decoder is also provided with an audio signal separating / decoding unit and the like.

The video signal output from the preprocessor 2 is interframe interpolated by the interframe interpolator 4 having the configuration shown in FIG. The motion detection unit 5 detects the magnitude of motion in the screen from the magnitude of the inter-frame difference signal of one frame or two frames before for the video signal before and after the inter-frame interpolation processing,
Adaptive synthesis circuit 17 in the luminance signal processing unit 10 and the color signal processing unit 20
And supply to 25.

The static area of the luminance signal included in the video signal interpolated between frames is a low-pass filtering circuit 11 having a pass band of 0 to 12 MHz.
, A frequency conversion circuit 12 for converting 32.4 MHz to 48.6 MHz, and an inter-field interpolation circuit 13 for processing. The motion area included in the inter-frame interpolated video signal is processed in the motion area processing system including the sampling switch 14, the field interpolation circuit 15, and the frequency conversion 16. Therefore, the still display control circuit 30 is configured to allow the output of the field interpolation circuit 15 to pass through the frequency conversion circuit 16 as it is during normal operation other than the still image display mode. Also,
The sampling switch 14 and the field interpolation circuit 15 in the motion area processing system of the luminance signal processing section 10 form a common part with the motion area processing system of the color signal processing section 20.

The inter-field interpolated luminance signal and the inter-field interpolated luminance signal are combined in the adaptive synthesizing circuit 17 in accordance with a synthesizing ratio adaptively controlled according to the magnitude of the motion detected by the motion detecting section 5. It The synthesized luminance signal is subjected to low-frequency replacement processing by the low-frequency replacement section 18, and then supplied to the temporal filter 19.

The temporal filter 19 is for reducing a change in resolution at a change point between a still area and a moving area, and includes a high frequency component of a signal of the current frame and a high frequency component of a signal of a frame before. Of these average values, the one having the smallest absolute value is added to the reduction component of the signal of the current frame. Therefore, a memory for holding the high frequency component of the signal one frame before is provided. Further, as will be described in detail later, since signals of only the processing system in the moving area are used during the still display, the processing of the temporal filter, and therefore its memory, is absolutely unnecessary. The output of the temporal filter 19 is supplied to the matrix section 8 except during the stationary display period.

Similarly, the inter-field interpolation circuit 22 and the field interpolation circuit 23 each have a stationary area for color signals whose time axis is expanded four times in the time axis expansion circuits 21 and 23 in the color signal processing unit 20. And interpolation processing is performed according to the motion area. The interpolated color signals are combined in the adaptive combination circuit 25 according to a combination ratio adaptively controlled according to the magnitude of the motion detected by the motion detection circuit 5. The combined color signal is subjected to data compression in which the (RY) signal and the (BY) signal alternately appear every other line. This color signal is converted into a line continuous color signal by line interpolation in a line sequential decoder 26, and then frequency converted from 16.2 MHz to 48.6 MHz in each of the frequency conversion circuits 27 and 28, and supplied to the matrix unit 8. To be done.

The matrix unit 8 includes a luminance signal processing unit 10 and a color signal processing unit.
The luminance signal Y and the color signals (RY), (B) supplied from 20
-Y) and R, G, B _three primary color signals are generated and supplied to the output terminals OUT ₁ , OUT ₂ , OUT ₃ via the D / A converter 9.

As shown in FIG. 2, the stationary display control circuit 30 has an input terminal connected to a high frequency component extraction section in the temporal filter 19.
It is provided with I ₁ , an input terminal I ₂ connected to the output terminal of the field interpolation circuit, an input terminal I ₃ for receiving a command for static display, switches S ₁ , S ₂ , S ₃ and a memory M. . The stationary display control circuit 30 further includes an output terminal O ₁ connected to the high frequency component detection unit of the previous frame signal in the temporal filter 19,
The output terminal O ₂ connected to the frequency conversion circuit 16 and the time axis expansion circuit 23, the adaptive synthesis units 17 and 25 at the time of still display, and the low frequency replacement circuit
A command output terminal O ₃ for supplying a control command to the temporal filter 19 and a control circuit C are provided.

In the normal operation mode in which the command signal for still display operation does not appear at the input terminal I ₃ , the contact of any of the switches S ₁ , S ₂ , and S ₃ is switched to the A side. Along with this, the high frequency component of the low frequency replaced signal generated in the temporal filter 19 and supplied to the input terminal I ₁ is switched to the switch S ₁
The data is written into the memory M via the switch, read out one frame from here, and supplied to the high-frequency component detecting unit of the previous frame signal in the temporal filter 19 via the switch S ₃ and the output terminal O ₁ . The write / read address for the memory M and the control signals such as the line / read command and the memory enable are supplied from the temporal filter 19 via the switch S ₂ whose contact is switched to the A side. As described above, the memory M in the static display control circuit 30 is used by the temporal filter 19 when the static display command is not issued.

On the other hand, when a static display command appears at the input terminal I ₃ , the control circuit C that detects this command switches the contacts of the switches S ₁ and S ₂ from the A side to the B side, and also the contact B side of the switch S ₂ A write address of a signal for one field and a control signal are supplied to the. As a result, the latest field-interpolated signal for one field output from the field interpolating circuit 15 at the previous stage is written in the memory M.

When the writing of the signal for one field is completed, the control circuit C switches the contact of the switch S ₃ from the A side to the B side, and at the contact B side of the switch S ₂ the read address and control of the signal for one field. Send a signal.
As a result, the latest one-field interpolated signal output from the field interpolating circuit 15 at the preceding stage and written in the memory M is read from the memory M, and the switch S ₃ and the output terminal O ₂ are read. And is supplied to the frequency conversion circuit 16 and the time axis expansion circuit 23. The reading of the signal for one field from the memory M is repeated in the field cycle. At the same time when the switch S ₃ is switched, the control circuit C supplies a control command to the output terminal O ₃ . Upon receiving this control command, the adaptive synthesizing units 17 and 25 start synthesizing signals using only the signals of the motion region processing system. In addition, the low-frequency replacement circuit 18 and the temporal filter 19 that have received the control command
Stops each processing within the still display period.

In this way, the screen for one field already stored in the memory M in the still display control circuit 30 is repeatedly read every field. Therefore, even if the signal between adjacent fields changes due to the movement, a stable field still screen without flicker is displayed.

The configuration in which the stationary display control circuit 30 is installed after the field interpolation circuit 15 in the motion region processing system common to the luminance signal processing unit and the color signal processing unit has been exemplified above. However,
The static display control circuit 30 may be installed before the field interpolation circuit 15.

Further, the configuration in which the output of the interframe interpolation circuit 4 is supplied to the field interpolation circuit 15 via the sampling switch 14 is illustrated. However, the signal on the input terminal of the interframe interpolation circuit 4 may be supplied to the cascade connection circuit of the field interpolation circuit 15 and the still display control circuit 30 via the sampling switch 14.

(Effect of the Invention) As described in detail above, the still display control circuit of the MUSE decoder according to the present invention stores the latest one-field screen output from the field interpolation circuit of the motion area processing system in the memory. Since it is configured to be stored in and read out periodically, a high-quality still image without flicker can be displayed even when there is motion between fields.

Also, the latest 1 output from the field interpolation circuit
Since the screen for fields is stored in the memory of the temporal filter that is not always needed during static display, the memory dedicated for static display is not required, and the MUSE decoder can be made inexpensive.

[Brief description of drawings]

FIG. 1 is an MU including a static display control circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram showing an example of the configuration of the SE decoder.
FIG. 3 is a block diagram showing the configuration of the still display control circuit, FIG. 3 is a block diagram showing the configuration of a conventional MUSE decoder, and FIG. 4 is a block diagram showing the configuration of the interframe interpolating unit 4 of FIG. FIG. 6 and FIG. 6 are conceptual diagrams for explaining the operation of the inter-frame interpolation block 4 and the problem of still display control using the same. IN: Input terminal for received video signal, 1 ... A / D converter, 2
...... Pre-processing unit, 4 …… Interpolation unit between frames, 5 …… Motion detection unit, 10 …… Luminance signal processing unit, 20 …… Color signal processing unit, 30
...... Still display control unit, 31 ...... Field memory, 32 ......
Control circuit, I ₁ …… Internal frame interpolated video signal input terminal, I ₂ …… A / D converted video signal input terminal, I ₃ …… Still display command input terminal, O ₁ …… Video signal Output terminal of O ₂
...... Control signal output terminal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiro Omura 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Broadcasting Research Institute of Japan Broadcasting Corporation (72) Inventor Yoshiaki Kanoku 1-10-11 Kinuta, Setagaya-ku, Tokyo Issue Broadcasting Technology Institute, Japan Broadcasting Corporation

Claims (1)

(57) [Claims] 1. A field interpolation process in a motion region processing system which is used as a memory of a temporal filter during a period other than a still display period and which is common to a luminance signal processing unit and a chrominance signal processing unit immediately before the start of still display. A memory for holding the latest one-field screen after or before the field interpolation processing, and for reading and outputting the latest one-field screen held immediately before the start of the still display during each still display period. A static display control circuit for a MUSE decoder, comprising: a control means for instructing an adaptive synthesizing unit to synthesize a luminance signal and a chrominance signal only by the output of the motion area processing system.