JP2648382B2 - Still image playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] With regard to a still image reproducing apparatus, a still image reproducing apparatus capable of simplifying the configuration of a decoder and reducing costs by removing a field memory after interpolating frames is provided. At least three cascade-connected field memories and the MUSE signal before entering the first-stage field memory
A first interpolation circuit for interpolating the MUSE signal extracted from the output of the field memory of the first stage between the frames, and the MUSE signal extracted from the output of the field memory of the first stage and the output of the field memory of the third stage A second interpolation circuit for interpolating the extracted MUSE signal between frames, and a third interpolation for inter-field interpolation based on signals from the first and second interpolation circuits.
And a luminance signal processing system and a chrominance signal processing system perform interpolation between frames with the first and second interpolation circuits of the two systems, and a third interpolation circuit. A still image reproduction of a MUSE video signal is performed by performing interpolation between fields.

[Industrial applications]

The present invention relates to a still image reproducing apparatus, and more particularly, to MUSE
The present invention relates to a still image reproducing apparatus that performs a still image reproducing process of a video signal in a transmission method.

High-definition television (high-definition television) has been developed as a next-generation television, and scheduled experimental broadcasting by satellite broadcasting has also started. MUSE system (Multiple Sub-Nyquist-Sampling Encoding system) is the center of HDTV technology
This is a band compression technology that enables satellite broadcasting.
This is 1125 scanning lines, field frequency 60Hz, band 22
This is to band-compress the RGB 3-channel signals of MHz into a band of 8.1 MHz and a signal of one channel.

The background art of the present invention is a still image reproducing method in the decoding processing of the band-compressed MUSE signal.

[Conventional technology]

In FIG. 4, reference numeral 1 denotes an encoder on the transmitting side in high-definition broadcasting, and 2 denotes a decoder on the receiving side. The encoder 1 includes a still image compression processing circuit 3 that performs a still image compression process,
A moving image compression processing circuit 4 for compressing a moving image, a motion detecting circuit 5 for detecting a moving area of an image, and a mixer 6 for mixing a still image and a moving image based on a mixing ratio from the motion detecting circuit 5. Is done. Note that motion detection is
This is to detect a moving area of an image, and this is performed based on a temporal change amount of the image, that is, a difference for each image.

In the MUSE system, the method of band compression differs between still images and moving images. Since the still image does not change with time, the image is divided into four fields (field offset subsample, frame / frame) as shown in FIG. 5 (a) showing the luminance signal and FIG. 5 (b) showing the chrominance signal. (Line offset subsample) and transmit one picture. On the other hand, a moving image is completely compressed in one field and transmitted after being compressed, so that the picture is coarser than a still image. Then, the motion amount of each pixel is detected by the motion detection circuit 5, and the MUSE signal is generated while changing the mixture ratio of the still image and the moving image. The above is the basic operation of the MUSE encoder 1.

The MUSE decoder 2 includes a still image reproduction processing circuit 7 for performing reproduction processing of a still image, a moving image reproduction processing circuit 8 for performing reproduction processing of a moving image, a motion detection circuit 9 for detecting a moving area of the image from the MUSE signal, and a motion detection circuit. A mixer 10 for mixing for reproduction of still and moving images based on the mixing ratio from
It consists of. The MUSE decoder 2 performs the reverse process of the encoder 1. Since the moving picture reproduces the picture only in the current field, no field memory is required. A still image requires information for four fields to reproduce one picture, and requires memory for three fields. That is, information up to three fields before the current field is required. Also, motion detection requires a memory for four fields. This is because in the MUSE signal, the method of thinning out the pixels to be transmitted changes for each field, and the period is four fields. Therefore, in order to determine whether the pixel is moving or stationary, information four fields before the pixel transmitted at the same position is needed. In this way, the decoder detects the amount of motion for each pixel and creates a picture while changing the mixture ratio of the still picture and the moving picture. The above is the basic operation of the MUSE decoder 2.

Next, a conventional configuration of a still image reproduction system on the decoder side is shown in FIG. In the figure, 11 and 12 are frame memories (memory for two fields), 13 is a subtractor, 14
Is an interpolation circuit for performing interpolation between frames, 15 is an interpolation circuit for performing interpolation between fields, and 16 is a field memory.
In the reproduction process of a still image, first, frame interpolation is performed using the frame memories 11 and 12 for motion detection, and the picture S1 [Z- ^0V ] of the current field and the picture S2 [Z- ^2V ] two fields before are ^extracted . ^Create a synthesized picture S3 [Z- ^0V + Z- ^2V ]. After that, the signal S4 is passed through the field memory 16 and delayed by one field time, so that the signal S4 (corresponding to the picture S4) is [Z- ^1V + Z- ^3V ].
Is output. By combining the signals S4 and the picture S3 [Z ^{-0 V} + Z ^{-2 V]} (inter-field interpolation), synthesized still image four fields in signal S5 ^{[Z -0V + Z -1V + Z -2V} + Z -3V ]
Is output.

[Problems to be solved by the invention]

However, in such a conventional still image reproducing apparatus, a one-field memory 16 is required for synthesizing the picture S3 [Z- ^0V + Z- ^2V ] and the picture S4 [Z- ^1V + Z- ^3V ]. Therefore, there is a problem that the memory peripheral circuit becomes complicated, and the configuration of the decoder becomes complicated and the cost increases.

That is, the MUSE signal is transmitted at 16 MHz in the first place,
One field memory 16 for one frame operates at 16 MHz. However, in the picture S3 [Z- ^0V + Z- ^2V ], the inter-frame signal is interpolated, so that the operation clock is doubled to 32 MHz. Then, a process unique to the MUSE system, in particular, a process of performing clock rate conversion on a luminance signal to generate a signal of 24 MHz is performed. Since the field delay processing is performed after this processing, the operation clock of the luminance memory becomes 24 MHz, which has become a factor of complicating the memory peripheral circuit.

In addition, this field delay processing requires a large-scale memory of 3 Mbit in the luminance signal processing unit and 1 Mbit (the above is approximate) in the chrominance signal processing unit, and a large percentage of all memories used in the MUSE decoder. Occupy.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a still image reproducing apparatus capable of simplifying the configuration of a decoder and reducing costs by eliminating a field memory after interpolating frames.

[Means for solving the problem]

In order to achieve the above object, a still image reproducing apparatus according to the present invention has a storage means 21 having at least three cascade-connected field memories 25 to 27 as shown in FIG. MUSE before entering field memory 25
A first interpolation circuit 22 for interpolating the signal and the MUSE signal extracted from the output of the second-stage field memory 26 between frames.
From the output of the field memory 25 of the first stage
A second interpolation circuit for interpolating the MUSE signal and the MUSE signal extracted from the output of the third-stage field memory 27 between frames
23, and a third interpolation circuit 24 for interpolating between fields based on signals from the first and second interpolation circuits 22 and 23,
In both the luminance signal processing system and the color signal processing system, interpolation between frames is performed by the first and second interpolation circuits 22 and 23 of the two systems, and interpolation between fields is performed by the third interpolation circuit 24. To reproduce the still image of the MUSE video signal. In this principle, the storage means 21 has four one-field memories 25 to 28. Also,
A subtractor 29 outputs a difference between four fields (two frames) to extract a motion detection signal.

[Action]

In the present invention, an inter-frame interpolation signal is extracted from each of the first interpolation circuit 22 and the second interpolation circuit 23, and the interpolation of these two inter-frame interpolation signals is performed from the third interpolation circuit 24. A signal, that is, an interpolated signal is extracted. Here, the clock rates of the two frame interpolation signals are the same. Then, by passing these two interpolated signals through the third interpolation circuit 24, an interpolated signal having a double clock rate is easily generated.

Therefore, the field delay memories having different operation clocks for inter-field interpolation can be deleted from both the luminance signal processing system and the chrominance signal processing system, so that the configuration of the MUSE decoder is simplified and the cost is reduced.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIG. 2 is a diagram showing an embodiment of a still image reproducing apparatus according to the present invention. FIG. 2 is a block diagram of the present apparatus. In this figure, reference numeral 31 denotes storage means corresponding to a two-frame memory for motion detection, which is constituted by four one-field memories 32-35. Since the amount of change between two frames for motion detection is, in other words, the amount of conversion between four fields, this configuration is adopted. Reference numeral 36 denotes a subtracter which outputs a difference between four fields (two frames) to extract a motion detection signal. Reference numerals 37 and 38 denote interpolation circuits for performing frame interpolation (corresponding to the first and second interpolation circuits). ) And 39 are a luminance processing circuit, and 40 is a color processing circuit.

The luminance processing circuit 39 includes low-pass filters (LPF) 41, 42,
It has clock converters 43 and 44 and an interpolation circuit (corresponding to a third interpolation circuit) 45 for performing field interpolation on luminance. The color processing circuit 40 performs interpolation for performing field interpolation on color. A circuit (corresponding to a third interpolation circuit) 46 is provided. The low-pass filters 41 and 42 perform a 12-MHz band limitation on the output signals S5 and S6 of the interpolation circuits 37 and 38, respectively, and the clock converters 43 and 44 output the 32-MHz rate signals output from the low-pass filters 41 and 42, respectively. Convert to 24MHz rate signal. The interpolation circuit 45 reproduces a luminance still image based on the output signals from the clock converters 43 and 44. The interpolation circuit 46 reproduces a color still image based on the output signals of the interpolation circuits 37 and 38. S1 to S10 are signals corresponding to the picture.

In the above-described configuration, in the reproduction process of the still image, the current field S1 and the signal S3 two fields before are interpolated by the interpolation circuit 37 according to the current inter-frame sub-sample phase, and at the same time, the signals S2 and three signals one field before are interpolated. The signal S4 before the field is interpolated by the interpolation circuit 38 in accordance with the sub-sample phase between frames one field before. However, it can be switched by luminance and color.

In the luminance signal processing, the signals S5 and S6 are passed through low-pass filters 41 and 42, which perform a band limitation of 12 MHz, and then are converted to 32 MHz signals by the clock converters 43 and 44, respectively.
The signals S7 and S8 are obtained by being converted into the signals of the rate. These low-pass filters 41 and 42 and clock converters 43 and 44
This is a unique method of still image processing of a luminance signal in the MUSE system. Output signals S7 and S8 from the two low-pass filters 41 and 42 and the clock converters 43 and 44 are interpolated between fields by an interpolation circuit 45 in accordance with an inter-field subsample phase, and a still image S9 of a luminance signal is obtained. Will be played.

On the other hand, the color signal processing does not require a low-pass filter or a clock converter unlike the luminance signal. The output signals S5 and S6 of the interpolation circuits 37 and 38 are interpolated by the interpolation circuit 46 according to the inter-field sub-sample phase for the color signal, thereby reproducing the still image S10 of the color signal.

As described above, in this embodiment, the memory for reproducing a still image is replaced with the memory for motion detection (four one-field memories 32 to 35).
This makes it possible to eliminate a field memory having a different operation clock which has been independently provided in a still image system (both luminance and color) as in the related art. As a result, a field delay memory having a different operation clock for inter-field interpolation can be deleted in both the luminance signal processing system and the chrominance signal processing system, and the configuration of the MUSE decoder can be simplified and the cost can be reduced. it can.

Next, FIG. 3 is a view showing another embodiment of the present invention.
In the present embodiment, the configuration of the luminance processing circuit 51 is different.
That is, a clock converter is not separately provided in the luminance processing circuit 51, and a clock conversion / interpolation circuit (a clock conversion / interpolation circuit) that simultaneously performs clock conversion and interpolation of a luminance signal between fields is provided downstream of the two low-pass filters 41 and 42. (Corresponds to the third interpolation circuit)
52 are arranged. Therefore, low-pass filter 4
The two signals of 32 MHz rate, which are the outputs of 1 and 42, are output by the clock conversion / interpolation circuit 52 as a signal S9 that has been interpolated between fields at a rate of 48 MHz. In particular, the process of clock conversion can be realized by substantially the same process when converting to a 24 MHz rate, and has the advantage that the circuit scale can be further reduced as compared with the above embodiment.

〔The invention's effect〕

According to the present invention, the field memory after frame interpolation can be deleted, the configuration of the MUSE decoder can be simplified, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a view for explaining the principle of the present invention, FIG. 2 is a block diagram showing one embodiment of a still image reproducing apparatus according to the present invention, and FIG. 3 is another embodiment of the still image reproducing apparatus according to the present invention. 4 to 6 are diagrams showing a conventional still image reproducing apparatus, FIG. 4 is a diagram showing a configuration of the MUSE encoder / decoder, and FIG. 5 is a diagram for explaining a MUSE pixel transmission method. FIG. 6 is a diagram showing the configuration of the still image reproduction system. 21, 31 ... storage means 22, 23 ... first and second interpolation circuits, 24 ... third interpolation circuit, 25 to 28, 32 to 35 ... one field memory, 29, 36 ... Subtractors, 37, 38 ... interpolation circuits (first and second interpolation circuits), 39, 51 ... luminance processing circuits, 40 ... color processing circuits, 41, 42 ... low-pass filters, 43, 44 ... … Clock converter, 45… interpolation circuit (third interpolation circuit), 46… interpolation circuit (third interpolation circuit), 52… clock conversion / interpolation circuit (third interpolation circuit) circuit).

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor ▲ Yoshi ▼ Masahiro Tadashi 1015 Ueodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Yuichi Ninomiya 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Within the Broadcasting Corporation Broadcasting Research Institute (72) Inventor Izumi ▲ Yoshi ▼ No. 1-110 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Seiichi Koshi 1-10 Kinuta, Setagaya-ku, Tokyo No. 11 Japan Broadcasting Corporation Broadcasting Research Institute (56) References JP-A-1-317080 (JP, A) JP-A-3-16488 (JP, A)

Claims (1)

(57) [Claims] A frame memory interpolating a cascade-connected at least three-stage field memories, a MUSE signal before entering a first-stage field memory, and a MUSE signal extracted from an output of a second-stage field memory. A first interpolation circuit, a MUSE signal extracted from the output of the first-stage field memory, and an MU extracted from the output of the third-stage field memory
A second interpolation circuit for interpolating an SE signal between frames; and a third interpolation circuit for interpolating between fields based on signals from the first and second interpolation circuits. In both the processing system and the color signal processing system, interpolation between frames is performed by the first and second interpolation circuits of the two systems, and interpolation between fields is performed by the third interpolation circuit.
A still image reproducing apparatus configured to reproduce a still image of an SE video signal.