JPH1098696A - Reference phase detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reproduce a high definition picture even when a receiving level is low by averaging transmission distortion due to a ghost, etc., level fluctuation due to noise, etc., and detecting a reference phase which is strong against the noise. SOLUTION: An analog video signal SV based on a second generation EDTV broadcasting method inputted in a terminal T1 is added to an A/D converter 2 and synchronizing separator 3. The synchronizing separator 3 separates a color burst signal S3C, a vertical synchronizing signal S3V and a horizontal synchronizing signal S3H from the video signal SV, outputs the color burst signal S3C to a clock generator 4, outputs the vertical synchronizing signal S3V and the horizontal synchronizing signal S3H to a line number counter 5B of a discriminating control signal extracting device 5. A gate device 5A outputs the discriminating control signal S5A to a sample value line interpolation device 7 via a band pass filter 6, interpolates a sampling and detects the reference phase 8 when a sampling phase is different from a systematic rule.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a second generation EDTV.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference phase detection device for a video signal conforming to a broadcasting system, and more particularly to a reference phase detection device for extracting reference phase information from a confirmation signal which is a part of an identification control signal.

[0002]

2. Description of the Related Art An identification control signal of the second generation EDTV broadcasting system is superimposed and transmitted for one horizontal scanning line period (22 lines and 285 lines) for each field in order to distinguish it from the current NTSC television signal. FIG. 5 shows the waveform of the identification control signal.

As shown in FIG. 5, a discrimination control signal is configured by dividing a horizontal (effective) video period of a scanning line into 27 bits and superimposing three different types of signals on each of them.
Bit positions B1 to B5 are NRZ waveforms, B6 to B2
Reference numeral 3 denotes a carrier waveform formula having a frequency of the color subcarrier fsc (3.58 MHz), and B25 to B27 each represent a carrier waveform formula having a frequency of 4 fsc / 7.

[0004] Control (phase) information necessary for demodulating the reinforcement signal included in the discrimination control signal and synthesizing with the main screen video signal, that is, correspondence between the absolute pixel position and the main image portion / upper and lower non-image portion reinforcement signals. A reference phase device for obtaining a reference phase from pixel position information, reference phase information of a modulation frequency of a horizontal reinforcement signal, and vertical-time reference phase information of a horizontal / vertical (resolution) reinforcement signal has already been proposed.

In the first conventional example, a switching position of a reference signal between a bit position B1 and a bit position 2, which is a waveform in the NRZ format, that is, an edge is obtained by a level comparing means and used as a reference phase.

A second conventional example is a color subcarrier fsc (3.
The switching position of bit position B6 to bit position 23, which is a carrier waveform formula of 58 MHz), is obtained by the level comparing means and used as a reference phase.

In the third conventional example, the zero-cross point of the confirmation signal waveform at bit positions B25 to B27, which is a carrier waveform having a frequency of 4 fsc / 7, is obtained by a level comparing means and used as a reference phase. . The signal level of bit position B25 to bit position 27 is slightly smaller than that of bit position B1, bit position 2 and bit position B6 to bit position 23. The S / N ratio can be improved, and there are a plurality of target zero-cross points, and the accuracy can be statistically improved by a plurality of detection results.
Since the bit position B24 has several advantages such as being advantageous for a ghost because it is blank, the third conventional example is the first prior art.
In addition, a reference phase with higher accuracy can be obtained as compared with the second conventional example.

[0008]

However, in the first prior art example already proposed, since the waveforms at the bit position B1 and the bit position 2 are in the NRZ format, the switching position is determined by a simple level comparing means. Although it is required, there is a problem that the waveform is easily distorted due to transmission distortion such as a ghost or noise due to a gentle edge gradient, and it is difficult to accurately specify a switching position.

In the second conventional example, the waveforms at bit positions B6 to 23 are more susceptible to transmission distortions and noises such as ghosts than in the first conventional example, and are switched according to the contents of the bits. However, there is a problem that it is difficult to detect the switching position with a temporally constant process.

[0010] Further, a third conventional example includes a first and a second.
Although it is possible to obtain a reference phase with higher accuracy than the conventional example, the detection of the zero-cross point by the simple level comparing means cannot essentially avoid the influence of transmission distortion such as ghost, noise, and the like. There is a problem that when the level of the zero-cross point changes, another sample point is erroneously detected.

The present invention has been made to solve the above-mentioned problems of the prior art, and is an improvement of the third conventional example in terms of circuit configuration.
The reference phase information is extracted by the reference phase detecting means from the confirmation signal which is a part of the identification control signal of the video signal conforming to the broadcasting system, and even when the reception level is low or the SN ratio of the transmission line is not good However, it is an object of the present invention to provide a reference phase detection device that enables reproduction of a high-definition image.

[0012]

In order to achieve the above object, a reference phase detector (1) according to the present invention comprises a band-pass filter for extracting a confirmation signal (S6) from an extracted identification control signal (S5A). (6) is provided, and the reference phase detecting means (8) performs a convolution operation on a plurality of continuous sample values of the confirmation signal (S6) with a predetermined in-phase coefficient value sequence to obtain a new data value sequence. An in-phase operation signal (S11) is generated, and the magnitude relationship between the in-phase operation signal (S11) and the confirmation signal (S6) is individually examined. The in-phase operation signal (S11) becomes a local maximum value and the confirmation signal (S6) The in-phase determining means (1) detects a confirmation signal when the predetermined condition is satisfied as a zero-cross point serving as a reference phase and outputs a timing pulse (S12) corresponding to the zero-cross point.
0) and a plurality of continuous sample values of the acknowledgment signal (S6) are subjected to a convolution operation with a predetermined sequence of orthogonal coefficient values to perform a quadrature operation signal (S
14) is generated, a confirmation signal when the absolute value of the orthogonal operation signal (S14) becomes a minimum value is detected as a zero-cross point serving as a reference phase, and a timing pulse (S15) corresponding to the zero-cross point is output. An AND which outputs a reference phase signal (S8) by performing a logical AND operation of the timing pulse (S12) from the means (13) and the timing pulse (S12) from the in-phase determining means (10) and the timing pulse (S15) from the orthogonal determining means (13)
D means (16).

A reference phase detecting device (1) according to the present invention comprises:
Bandpass filter (6) and reference phase detecting means (8)
In-phase determining means (10) and quadrature determining means (13)
And the AND means (16), level fluctuations due to transmission distortion due to ghosts or the like and noises are averaged, and a reference phase resistant to noise can be detected.

Further, the reference phase detecting device (1) according to the present invention comprises a band pass filter (6) for extracting a confirmation signal (S6) from the identification control signal (S5A) extracted by the identification control signal extracting means (5). And the reference phase detection means (8) performs a level comparison with respect to the three successive sample values of the confirmation signal, namely, the previous sample value, the current sample value, and the subsequent sample value. A difference value obtained by subtracting the previous sample value from the subsequent sample value is detected, and when the level of the sample value satisfies the relationship of the previous sample value <the current sample value <the next sample value, and when the difference value has a maximum value, First level comparing means (21) for outputting a comparison signal (S21), and adding means (22) for adding three sample values and outputting an addition signal (S22);
The absolute value of the addition signal (S22) is converted to the absolute value signal (S22).
23) for outputting an absolute value signal (S);
The second level comparing means (2) which detects the current sample point when (23) is minimum as a zero-cross point serving as a reference phase and outputs a timing pulse (S24) corresponding to the zero-cross point.
4) and the comparison signal (S) of the first level comparing means (21).
21) and AND means (25) for performing an AND operation of the timing pulse (S24) of the second level comparing means (24) and outputting a reference phase signal (S8B). I do.

A reference phase detecting device (1) according to the present invention comprises:
Bandpass filter (6) and reference phase detecting means (8)
First level comparing means (21) for detecting the maximum value of the difference value and outputting a comparison signal of logical value 1, and adding means (2)
2), an absolute value means (23), a second level comparing means (24) for outputting a timing pulse corresponding to a zero crossing point, and an AND means (25). Level fluctuations due to noise or the like are averaged, and a reference phase that is strong against noise can be detected.

[0016]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is an overall block configuration diagram of a reference phase detection device according to the present invention. In FIG.
The reference phase detector 1 is an A / D (Analog to Digital)
It comprises a conversion means 2, a synchronization separation means 3, a clock generation means 4, an identification control signal sampling means 5, a band pass filter 6, a sample value interpolation means 7, and a reference phase detection means 8. The identification control signal extracting means 5 includes a gate means 5A and a line number counting means 5B.

The analog video signal SV conforming to the second generation EDTV broadcasting system, which is input to the terminal T1, is applied to the A / D conversion means 2 and the synchronization separation means 3. The synchronization separation means 3 separates the color burst signal S3C, the vertical synchronization signal S3V, and the horizontal synchronization signal S3H from the video signal SV, controls the color burst signal S3C to the clock generation means 4, and controls the vertical synchronization signal S3V and the horizontal synchronization signal S3H. The signal is output to the line number counting means 5B of the signal sampling means 5.

The clock generation means 4 outputs the I of the carrier chrominance signal based on the color burst signal S3C (fSC = 3.58 MHz).
Clock signal SCK (4fS
C), and outputs the clock signal SK1 (4fSC) to the A / D conversion means 2, the sample value interpolation means 7, and the reference phase detection means 8.

The line number counting means 5B of the identification control signal extracting means 5 counts the horizontal synchronizing signal S3H based on the vertical synchronizing signal S3V and discriminates the identification control signal S5A superimposed on lines 22 and 285 (FIG. 5). ) Is generated, and the gate signal S5B is output to the gate means 5A.

The A / D converter 2 converts the analog video signal Va input to the terminal T1 according to the second generation EDTV broadcasting system into digital based on the clock signal SK1, and identifies the digital video signal S2. It outputs to the gate means 5A of the control signal extracting means 5.

Gate means 5 of identification control signal extracting means 5
A extracts the identification control signal S5A superimposed on lines 22 and 285 of the digital video signal S2 based on the gate signal S5B, and outputs the identification control signal S5A to the band-pass filter 6. The band-pass filter 6 shown in FIG.
From the identification control signal S5A shown in FIG.
7) Bit position B25 to bit position B2 which are sine waves
7 and outputs a confirmation signal S6 to the sample value sequence interpolation means 7.

The sample value sequence interpolating means 7 determines whether the sampling phase is specified in the system of the discrimination control signal (I.multidot.
If it is different from (Q axis) (for example, when the phase is the same as the color burst), interpolation processing of the sample value sequence at the phase specified in the method is performed, and the interpolation confirmation signal S7 is output to the reference phase detection means 8
Output to If the sampling phase coincides with the specification (the I and Q axes of the carrier color signal) of the identification control signal, the sample value sequence interpolation means 7 does not perform the interpolation process of the sample value sequence and outputs the input confirmation signal. S6 is the interpolation confirmation signal S7
Is output to the reference phase detecting means 8.

The reference phase detecting means 8 outputs the interpolation confirmation signal S7
, Two sets of coefficient sequences determined in advance for a plurality of continuous sample values of, for example, (-1, -1, -1,0,1,1,1),
By performing a convolution operation with a coefficient sequence such as (-1, -1, 1, 1, 1, -1, -1), two new data value sequences are generated, and the data values of the two new data value sequences are generated. The magnitude relation is individually examined, a point meeting the condition is detected as a zero cross point, and a timing pulse corresponding to the zero cross point is output as a reference phase signal S8A.

FIG. 2 is a block diagram of a main part of the reference phase detecting means of the reference phase detecting device according to the present invention. FIG. 3 is an explanatory diagram of the operation of the reference phase detection means of the reference phase detection device according to the present invention. The operation of the reference phase detecting means will be described with reference to FIGS.

In FIG. 2, the reference phase detecting means 8A includes an in-phase judging means 10, a quadrature judging means 13, and an AND means 16. The in-phase determining means 10 includes a convolution calculating means 11 and a level determining means 12. The orthogonality determining means 13 includes a convolution calculating means 14 and a level determining means 15.

An interpolation confirmation signal S7, which is separated from the identification control signal S5A and interpolated, is input to a terminal T11.
The interpolation confirmation signal S7 is output from the convolution operation means 11 and the level judgment means 12
And the convolution operation means 1 of the orthogonality judgment means 13
4. The clock signal SCK from the clock generating means 4 is input to the terminal T12, and the convolution calculating means 11 and the level determining means 12 of the in-phase determining means 10 and the convolution calculating means 14 and the level of the quadrature determining means 13 via the terminal T12. It is supplied to the judgment means 15.

In FIG. 3, (1) is a clock signal S having a frequency (4 fsc) synchronized with the phase of the I and Q axes of the color signal.
CK is shown. (2) shows the interpolation confirmation signal S7 in which one cycle sampled by the clock signal SCK is composed of seven samples, and the zero cross point is located on the I axis, -Q axis, -I axis, and Q axis every seven samples. It is indicated by a black circle.

(3) is an in-phase coefficient value sequence, (4) is an in-phase operation signal S11 obtained by performing a convolution operation of the interpolation confirmation signal S7 and the in-phase coefficient value sequence, (5) is an orthogonal coefficient value sequence, and (6)
Denotes an orthogonal operation signal S14 obtained by performing a convolution operation of the interpolation confirmation signal S7 and the orthogonal coefficient value sequence, and (7) denotes a reference phase signal S8A.

The convolution operation means 11 of the in-phase determination means 10 outputs the clock signal SCK (4, 5,
6, 0, 1, 2, 3,...), And a sample value {4, 5, 6, 0, 1, 1,... With respect to 2, 3,..., For example, seven in-phase coefficient value sequences (-1,-
(1, -1, 0, +1, +1, +1, +1), and outputs the in-phase operation signal S11 shown in (4), which is the result of the convolution operation, to the level determination means 12.

The in-phase coefficient sequence of (3) in FIG. 3 is centered on S7 (0) of the interpolation confirmation signal S7 shown in (2) as the current sample point, and is in phase with the confirmation signal S7 (0) of the current sample point. (0) of the coefficient sequence, (-1) of the in-phase coefficient sequence for the first three samples {S7 (4), S7 (5), S7 (6)}, and three samples {S7 (1), S7
(2), S7 (3)} are given the in-phase coefficient sequence (+1), and a convolution operation is performed between the seven sample point data.
This shows the phase relationship between the interpolation confirmation signal S7 and the in-phase coefficient sequence when S11 (0) of the in-phase operation signal S11 shown in (4) is obtained.

The orthogonal coefficient sequence of (5) in FIG.
S7 (0) of the interpolation confirmation signal S7 shown in (2) is centered as the current sample point, and the confirmation signal S7 (0) of the current sample point and the samples {S7 (6), S7 (1)} before and after it are included in The (+1) of the orthogonal coefficient sequence is converted to the remaining four samples {S7 (4), S7 (5), S7 (2),
The orthogonal coefficient sequence (-1) is given to S7 (3)｝, a convolution operation is performed between the seven sample point data, and interpolation for obtaining S14 (0) of the orthogonal operation signal S14 shown in (6) is performed. This shows the phase relationship between the confirmation signal S7 and the orthogonal coefficient sequence.

The level judging means 12 outputs an in-phase operation signal S11.
In addition, the magnitude of the interpolation confirmation signal S7 composed of seven samples for one cycle of the sine wave is individually examined, and a sample value of the interpolation confirmation signal S7 closest to the zero-degree phase is detected from the interpolation confirmation signal S7. A zero-cross point is set, and a timing pulse corresponding to the zero-cross point {S7 (0)} is output to the AND means 16 as the in-phase reference signal S12.

The first function of the level judging means 12 is to compare the level of the current in-phase operation signal S11 (t) with the previous in-phase operation signal S11 (t-1), and to determine the local maximum value S11 (0) of the in-phase operation signal S11. ) Is detected.

The second function of the level judging means 12 is that when the in-phase operation signal S11 has the maximum value S11 (0), the in-phase coefficient value sequence (-
The level of the interpolation confirmation signal S7, which is the multiplication signal of (1, 0, +1), is compared, and the interpolation confirmation signal S7 (1), which is the multiplication signal of the in-phase coefficient value sequence (+1), has a positive value. And an interpolation confirmation signal that is a multiplied signal of the in-phase coefficient value sequence (0) that satisfies the condition that the interpolation confirmation signal S7 (6), which is the multiplied signal of the in-phase coefficient value sequence (-1), is a negative value. S7 (0) is defined as a zero cross point, and an in-phase reference signal S12, which is a timing pulse corresponding to the interpolation confirmation signal S7 (0), is output to the AND means 16.

The convolution operation means 14 of the orthogonal judgment means 13 outputs the clock signal SCK (4, 5,
6, 0, 1, 2, 3,...), And a sample value {4, 5, 6, 0, 1, 1,... With respect to 2, 3,..., For example, the seven orthogonal coefficient value sequences (-1,-
(1, +1, +1, +1, -1, -1), and the result of the convolution operation is (6).
Is output to the level determination means 15.

The level judging means 15 outputs the orthogonal operation signal S14.
The minimum value is detected by examining the magnitude relationship between the absolute values of the absolute value of the orthogonal reference signal S15 (0), which is a timing pulse corresponding to the zero-cross point. Is output to the AND means 16.

In FIG. 3, since the orthogonal operation signal S14 shown in (6) has the same phase as the interpolation confirmation signal S7 shown in (2), the interpolation confirmation signal S7 is input to the level judgment means 15, The magnitude of the absolute value of the interpolation confirmation signal S7 is checked to detect the minimum value S7 (0), and the interpolation confirmation signal S7
The interpolation confirmation signal S7 (0) satisfying the condition that (1) is a positive value and the interpolation confirmation signal S7 (6) is a negative value is defined as a zero cross point, and the timing corresponding to the interpolation confirmation signal S7 (0) The pulse orthogonal reference signal S15 may be output to the AND means 16.

The AND means 16 performs a logical product operation of the in-phase reference signal S12 output from the level determination means 12 and the quadrature reference signal S15 output from the level determination means 15, and a reference phase signal S8A shown in (7). Is output to T2.

As described above, the present invention utilizes the concept of synchronous demodulation for its detection and discrimination, and provides two sets of coefficient value sequences corresponding to two demodulated carriers having phases shifted by 90 degrees, A convolution operation is performed with the sequence to obtain an in-phase demodulation component and a quadrature demodulation component at each sample point, and these take the maximum value and the minimum value at the zero-cross point in seven samples, respectively. Is to be determined.

In synchronous demodulation, in order to obtain an in-phase component,
The demodulated carrier of the same frequency as the demodulated signal is multiplied and smoothed, and the magnitude of the component in phase with the demodulated carrier is obtained. Since one cycle of the interpolation confirmation signal (S7) is composed of seven samples, a coefficient sequence corresponding to a demodulation carrier for obtaining an in-phase component is set around the current sample.
(0) for the current sample point, (-1) for the previous three samples
Is given to the last three samples, and convolution operation is performed with the seven sample point data, and the result is used as the in-phase component at the phase of the sample point.

To obtain the orthogonal component, a coefficient sequence of (+1) is given to the three samples before, present, and after, and a coefficient sequence of (-1) is given to the remaining four samples. A volume operation is performed, and the result is used as a quadrature component at the phase of the sample point.

As described above, when the in-phase component and the quadrature component are defined, at the zero cross point of the interpolation confirmation signal (S7),
The in-phase component has a maximum value, the previous sample value is negative, the post-sample value is positive, and the absolute value of the quadrature component has a minimum value. The in-phase component value is negative at the previous sample point, 0 at the current sample point, The value becomes positive at the subsequent sample point, and the zero-cross point can be extracted by imposing this determination condition on each component.

FIG. 4 is a block diagram of a main part of the reference phase detecting means of the reference phase detecting device according to the present invention. In FIG. 4, the reference phase detecting means 8B of the reference phase detecting device 1
Level comparing means 21, adding means 22, absolute value means 23,
A level comparison unit 24 and an AND unit 25 are provided.

The interpolation confirmation signal S7 inputted to the terminal T21 is inputted to the level comparing means 21 and the adding means 22, and the clock signal SCK inputted to the terminal T22 is outputted to the reference phase detecting means 8.
Added to all blocks in B.

The level comparing means 21 calculates a continuous sample value S7 (t-1), a current sample value S7 (t0) and a subsequent sample value of three consecutive sample values of the interpolation confirmation signal S7 shown in (2) of FIG. The level of the sample value S7 (t1) is compared, and the difference value is obtained by subtracting the previous sample value S7 (t-1) from the subsequent sample value S7 (t1). The result is S7 (t-1) <S7 (t0) <
When S7 (t1) and the difference value is the maximum, the comparison signal S21 of the logical value 1 is output to the AND means 25.

The level comparing means 21 outputs, for example, the level of three successive sample values {S7 (4), S7 (5), S7 (6)} of the interpolation confirmation signal S7 shown in FIG. A comparison is made and then a level comparison is made with {S7 (5), S7 (6), S7 (0)}, and thus {S7 (6), S7 (0), S7 (1)},
The levels are compared with {S7 (0), S7 (1), S7 (2)},..., And the first comparison result is {S7 (4)> S7 (5), S7 (5) <S7
(6) Since｝, a comparison signal S21 (5) having a logical value of 0 is output, and
Since the next comparison result is {S7 (5) <S7 (6) <S7 (0)}, a comparison signal S21 (6) having a logical value of 1 is output, and the next comparison result is {S7 (6) < Since S7 (0) <S7 (1)｝, logical value 1
Is output, and the next comparison result is S7 (0).
<S7 (1) <S7 (2)}, so the comparison signal S21 of the logical value 1
(1) is output to the AND means 25.

The adding means 22 outputs three consecutive sample values {S7 (t-1), S7 (t0), S7 (t1)} of the interpolation confirmation signal S7.
And an addition signal S22 (t0) ｛= S7 (t-1) + S
7 (t0) + S7 (t1)} is output to the absolute value means 23.

For example, the adding means 22 outputs three consecutive sample values {S7} of the interpolation confirmation signal S7 shown in (2) of FIG.
(4), S7 (5), and S7 (6)}, and an addition signal S2
2 (5) ｛= S7 (4) + S7 (5) + S7 (6)｝ and then {S
7 (5), S7 (6), S7 (0)}, and an addition signal S
22 (6) = S7 (5) + S7 (6) + S7 (0)}, and thus {S7 (6), S7 (0), S7 (1)}, {S7 (0), S7
(1), S7 (2)｝,...
(0), S22 (1),... Are output to the absolute value means 23.

The absolute value means 23 converts the sum signal S22 (t0) to an absolute value and outputs an absolute value signal S23 (t0) ｛= | S22 (t0) │｝ to the level comparing means 24. The level comparing means 24 detects the minimum value of the absolute value signal S23 by comparing the levels of three consecutively input absolute value signals S23, and samples the sampled value S7 (0) of the interpolation confirmation signal S7 giving the minimum value. Is a zero-cross signal, and a comparison signal S24, which is a timing pulse of the zero-cross signal, is output to the AND means 25.

The level comparing means 24 outputs, for example, absolute value signals S23 (6) ｛= | S22 (6) |｝ and S23 (0) ｛= | S22 (0).
|｝ And S23 (1) ｛= | S22 (1) |｝ are compared and {S23 (6)> S23 (0)}, and {S23 (1)> S23 (0)}.
At this time, the absolute value signal S23 (0) is the minimum value, and the sampling point S7 (0) of the interpolation confirmation signal S7 giving the minimum value is defined as a zero-cross signal.
Is output to the AND means 25.

The AND means 25 performs an AND operation on the comparison signal S21, the comparison signal S24 and the clock signal SCK, and outputs a reference phase signal S8B to the terminal T2. That is, AN
The D means 25 outputs the logical value 1 together with the clock signal SCK only when the comparison signal S21 and the comparison signal S24 satisfying the condition for detecting the sample point S7 (0) of the interpolation confirmation signal S7 as a zero-cross signal are output. And outputs the reference phase signal S8B as a single pulse.

As described above, the present invention detects the sample point closest to the zero-degree phase of the sine wave waveform among the seven samples constituting one cycle of the sine wave waveform of the interpolation confirmation signal. When the sine wave waveform is sampled at equal intervals using the concept of linear regression for discrimination, the three points, the zero-degree phase sample point and the sample points before and after it, are the center zero-degree phase point and the zero-cross point. As a countermeasure against the case where noise is superimposed, linear regression is performed on the coordinate values (time, level) of these three points, and the gradient of the obtained regression line, that is, The regression coefficient is positive, and the "y-slice" is the absolute minimum at the zero-cross point, and the sample point of the zero-degree phase is determined.

In the present invention, individual sample point data as described in the description of the conventional example is not treated as a detection target as it is, and first, the size of sample points separated by one is compared to facilitate determination. Then, find the data on which the effect of noise was smoothed by adding three consecutive points,
As a result, it is possible to detect a zero-cross point excellent in noise resistance.

The above embodiment is an example of the present invention, and the present invention is not limited to the above embodiment.

[0055]

According to the present invention, the following effects are exhibited by the above configuration. According to the present invention, a band pass filter (6) for extracting a confirmation signal (S6) from the extracted identification control signal (S5A) is provided, and a plurality of consecutive confirmation signals (S6) are provided to a reference phase detecting means (8). Convolution operation with a predetermined in-phase coefficient value sequence on the sample values to generate an in-phase operation signal (S11) which is a new data value sequence;
The magnitude relationship between the in-phase operation signal (S11) and the confirmation signal (S6) is individually examined, and confirmation is made when the in-phase operation signal (S11) has a local maximum value and the confirmation signal (S6) satisfies a predetermined condition. A signal is detected as a zero-cross point serving as a reference phase, and a timing pulse corresponding to the zero-cross point (S12)
And a confirmation signal (S6).
Is subjected to a convolution operation with a predetermined sequence of orthogonal coefficient values to generate a new orthogonal data signal (S14), which is a new data value sequence. A quadrature determining means (13) for detecting a confirmation signal at the time of the minimum value as a zero-cross point serving as a reference phase and outputting a timing pulse (S15) corresponding to the zero-cross point; and a timing pulse from the in-phase determining means (10) (S12) and an AND means (16) for performing a logical product operation of the timing pulse (S15) from the orthogonal judging means (13) and outputting a reference phase signal (S8) are provided. And so on, and a reference phase that is resistant to noise can be detected. Therefore, even when the reception level is low, the S
Even if the N ratio is not good, it is possible to provide a reference phase detection device (1) capable of reproducing a high-definition image.

The present invention also provides a band-pass filter (6) for extracting a confirmation signal (S6) from the identification control signal (S5A) extracted by the identification control signal extracting means (5), and a reference phase detecting means ( 8) In the confirmation signal, a level comparison is performed with respect to three temporally continuous sample values of the previous sample value, the current sample value, and the subsequent sample value, and the previous sample value is subtracted from the subsequent sample value. The difference value is detected, and when the level of the sample value satisfies the relationship of the previous sample value <the current sample value <the next sample value and the difference value has a maximum value, a comparison signal (S21) of a predetermined value is output. 1 level comparison means (21), an addition means (22) for adding three sample values and outputting an addition signal (S22), and an absolute value signal for the addition signal (S22). (S23) Absolute value means to force (23)
A second level comparing means (24) for detecting a current sample point when the absolute value signal (S23) is minimum as a zero-cross point serving as a reference phase and outputting a timing pulse (S24) corresponding to the zero-cross point; , First level comparing means (2
1) and the second level comparing means (2)
AND means (2) for performing an AND operation with the timing pulse (S24) of 4) and outputting a reference phase signal (S8B)
5) are provided, and level fluctuations due to noise and the like due to transmission distortion due to ghosts and the like are averaged, and a reference phase resistant to noise can be detected. Therefore, even when the reception level is low, or when the SN ratio of the transmission path is low. Even if it is not good, it is possible to provide a reference phase detection device which enables reproduction of a high-definition image.

[Brief description of the drawings]

FIG. 1 is an overall block configuration diagram of a reference phase detection device according to the present invention.

FIG. 2 is a block diagram of a main part of a reference phase detection unit of the reference phase detection device according to the present invention.

FIG. 3 is an operation explanatory diagram of a reference phase detecting means of the reference phase detecting device according to the present invention.

FIG. 4 is a block diagram of a main part of a reference phase detection unit of the reference phase detection device according to the present invention.

FIG. 5 is a waveform of an identification control signal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Reference phase detection device, 2 ... A / D conversion means, 3 ... Synchronization separation means, 4 ... Clock generation means, 5 ... Identification control signal extraction means, 5A ... Gate means, 5B ... Line number counting means, 6 ... Bandwidth Pass filter, 7 ... sample value interpolation means,
8, 8A, 8B: reference phase detecting means, 10: in-phase determining means, 11: convolution calculating means, 12: level determining means, 13: orthogonal determining means, 14: convolution calculating means, 15: level determining means, 16 ... AND means, 21 ... level comparing means, 22 ... adding means, 23 ... absolute value means, 24 ... level comparing means, 25 ... AND means,
S2, SV: video signal, S3C: color burst signal, S
3H: horizontal synchronization signal, S3V: vertical synchronization signal, S5A: identification control signal, S5B: gate signal, S6: confirmation signal, S7: interpolation confirmation signal, S8: reference phase signal, S11: in-phase calculation signal,
S12: In-phase reference signal, S14: Quadrature operation signal, S15: Quadrature reference signal, S21, S24: Comparison signal, S22: Addition signal, S
23 ... absolute value signal, SCK ... clock signal, T1, T2, T1
1, T12, T21, T22 ... terminals.

Claims (2)

[Claims] A second method for transmitting a high-definition wide image while being compatible with the current NTSC television broadcasting system.
Clock generating means for generating a clock phase-synchronized with a fixed phase difference with respect to a burst signal of a video signal conforming to the generation EDTV broadcasting system; and sampling the video signal with the clock of the clock generating means to produce a digital video signal Analog / digital converting means for converting, identification control signal extracting means for extracting an identification control signal superimposed on a specific scanning line from the digital video signal converted by the analog / digital converting means, and extracting the identification control signal A reference phase detecting device for detecting a reference phase from the identification control signal extracted by the means, wherein a band-pass filter for extracting a confirmation signal from the extracted identification control signal is provided; The detecting means includes a plurality of consecutive sample values of the confirmation signal, A convolution operation with a coefficient value sequence is performed to generate an in-phase operation signal which is a new data value sequence, and the magnitude relationship between the in-phase operation signal and the confirmation signal is individually examined. The in-phase operation signal has a local maximum value, and In-phase determination means for detecting a confirmation signal when the confirmation signal satisfies a predetermined condition as a zero-cross point serving as a reference phase and outputting a timing pulse corresponding to the zero-cross point, and a plurality of continuous samples of the confirmation signal A convolution operation with a predetermined sequence of orthogonal coefficient values is performed on the value to generate an orthogonal operation signal as a new data value sequence, and a confirmation signal when the absolute value of the orthogonal operation signal becomes a minimum value becomes a reference phase. A quadrature determining means for detecting a zero-cross point and outputting a timing pulse corresponding to the zero-cross point; and a timing pulse from the in-phase determining means. And an AND means for performing a logical product operation of the timing pulse from the quadrature determining means and outputting a reference phase signal. 2. A second method for transmitting a high-definition wide image while being compatible with the current NTSC television broadcasting system.
Clock generating means for generating a clock phase-synchronized with a fixed phase difference with respect to a burst signal of a video signal conforming to the generation EDTV broadcasting system; and sampling the video signal with the clock of the clock generating means to produce a digital video signal Analog / digital converting means for converting, identification control signal extracting means for extracting an identification control signal superimposed on a specific scanning line from the digital video signal converted by the analog / digital converting means, and extracting the identification control signal A reference phase detecting means for detecting a reference phase from the identification control signal extracted by the means; and a band-pass filter for extracting a confirmation signal from the identification control signal extracted by the identification control signal extracting means. At the same time, the reference phase detecting means outputs a time-continuous The three sample values, ie, the previous sample value, the current sample value, and the subsequent sample value, are compared with each other, and a difference value obtained by subtracting the previous sample value from the subsequent sample value is detected. First level comparison means for outputting a comparison signal of a predetermined value when the sample value <the current sample value <the later sample value and the difference value has a maximum, and adding the three sample values And an absolute value means for converting the sum signal to an absolute value and outputting an absolute signal, and a zero-crossing point at which the current sample point when the absolute signal is minimal is used as a reference phase. A second level comparing means for detecting and outputting a timing pulse corresponding to the zero crossing point; a comparison signal of the first level comparing means;
And AND means for performing a logical product operation of the level comparison means with the timing pulse and outputting a reference phase signal.