JPS63224492A - Regenerating circuit for subcarrier signal - Google Patents

Regenerating circuit for subcarrier signal

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Publication number
JPS63224492A
JPS63224492A JP5652387A JP5652387A JPS63224492A JP S63224492 A JPS63224492 A JP S63224492A JP 5652387 A JP5652387 A JP 5652387A JP 5652387 A JP5652387 A JP 5652387A JP S63224492 A JPS63224492 A JP S63224492A
Authority
JP
Japan
Prior art keywords
subcarrier
circuit
signal
fsc
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5652387A
Other languages
Japanese (ja)
Other versions
JP2550053B2 (en
Inventor
Yasuhiro Hirano
裕弘 平野
Hiroshi Yoshiki
宏 吉木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62056523A priority Critical patent/JP2550053B2/en
Publication of JPS63224492A publication Critical patent/JPS63224492A/en
Application granted granted Critical
Publication of JP2550053B2 publication Critical patent/JP2550053B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To reduce the influence of transmission distortion, etc., and to prevent malfunction by regenerating the reference phase of a subcarrier according to the phase relation of a chrominance subcarrier when the subcarrier has a maximal or minimal value. CONSTITUTION:When digital signal processing is performed at the time of sampling a received signal at 4fsc four times as high as the chrominance subcarrier, a received television signal is converted by an A/D converting circuit 1 into a digital signal of 4fsc. A timing extracting circuit 8, on the other hand, extracts fsc and 4fsc, and horizontal and vertical synchronizing signals HD and VD necessary for signal processing. A line control circuit 4 specifies scanning lines of the HD and VD signal where the subcarrier mu0 is inserted and a mu0 regenerating circuit 5 generates a subcarrier mu0 in said period according to the phase relation between the maximal point of the subcarrier mu0 and fsc. A decoder circuit 3 uses those signals to generate a luminance signal Y and color difference signals I and Q by demodulation.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は副搬送波信号の再生回路に係り、特に現行テレ
ビジョンと両立性を有する高精細テレビジョンの高精細
情報の再生に好適な副搬送波信号の再生回路な関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a subcarrier signal reproducing circuit, and in particular, to a subcarrier signal reproduction circuit suitable for reproducing high definition information of a high definition television that is compatible with current televisions. Related to signal regeneration circuits.

〔従来の技術〕[Conventional technology]

現行テレビジョンと伝送路両立性、受像機両立性を有す
る高精細テレビジョンは、特願昭58−044238号
に記載の方゛法がある。この方法では、現行テレビジョ
ンのビデオ信号帯域を越えた信号成分、例えば輝度高域
成分YH(4,2MHz以上)を、副搬送波μoにより
搬送波抑圧振幅変調により低域成分Y)l’  (4,
2MHz以下の周波数成分)に変換して周波数インタリ
ーブの手法で現行テレビジョン信号に重畳して伝送する
There is a method described in Japanese Patent Application No. 58-044238 to create a high-definition television that is compatible with current televisions, transmission paths, and receivers. In this method, a signal component exceeding the video signal band of current televisions, for example, a brightness high frequency component YH (4.2 MHz or more), is converted to a low frequency component Y)l' (4,2 MHz or more) by carrier suppression amplitude modulation using a subcarrier μo.
(frequency components of 2 MHz or less) and is transmitted by superimposing it on the current television signal using a frequency interleaving method.

受像側では、低域成分Y H/  を分離し、同期検波
により、元の輝度高域成分Y■を復調する。受像側では
、伝送された副搬送波μoより、同期検波に必要な副搬
送波を再生する。ただ、μoは例えばフレーム毎の特定
走査線の一部に挿入されるため送られる情報が少なく、
この情報をもとに高精度な副搬送波を再生にするものと
して、特願昭61−30829号に記載のものがある。
On the image receiving side, the low frequency component Y H/ is separated and the original luminance high frequency component Y■ is demodulated by synchronous detection. On the image receiving side, subcarriers necessary for coherent detection are reproduced from the transmitted subcarrier μo. However, since μo is inserted into a part of a specific scanning line in each frame, less information is sent.
Japanese Patent Application No. 61-30829 discloses a method for reproducing subcarriers with high accuracy based on this information.

この方法は、副搬送波fscの周期毎に副搬送波μoの
振幅値の大小比較から基準位相の再生を行なうものであ
る。
In this method, a reference phase is recovered by comparing the amplitude values of the subcarrier μo every period of the subcarrier fsc.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述の如き従来技術では、伝送歪などの影響について配
慮がされておらず、例えば色副搬送波f scと副搬送
波μoの間に伝送歪に起因した位相誤差が発生した場合
には、誤った位相再生を行なうなどの問題があった。ま
た、雑音等の影響も配慮されておらず、S/Nの悪い状
態では誤動作を行なうなどの問題があった。
In the conventional technology described above, no consideration is given to the influence of transmission distortion, etc., and for example, if a phase error due to transmission distortion occurs between the color subcarrier fsc and the subcarrier μo, an incorrect phase may occur. There were problems with playback, etc. Further, the influence of noise and the like is not taken into account, and there are problems such as malfunctions in poor S/N ratios.

本発明の目的は、伝送歪、雑音などの影響を受けに<<
、構成も容易な副搬送波信号の再生回路を提供すること
にある。
The purpose of the present invention is to reduce the influence of transmission distortion, noise, etc.
Another object of the present invention is to provide a subcarrier signal regeneration circuit that is easy to configure.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、副搬送波μoが極大値、あるいは極性値を
取るときの色副搬送波f scの位相関係により、μo
の基準位相を再生することにより達成される。
The above purpose is based on the phase relationship of the color subcarrier fsc when the subcarrier μo takes a local maximum value or a polar value.
This is achieved by regenerating the reference phase of

〔作用] 副搬送波μoが315fscの場合を例に1本発明の詳
細な説明する。
[Operation] The present invention will be explained in detail using an example in which the subcarrier μo is 315 fsc.

第3図(a)は色副搬送波f sc、(b)は、色副搬
送波μoより生成される極大値検出ゲート信号である。
FIG. 3(a) shows the color subcarrier fsc, and FIG. 3(b) shows the maximum value detection gate signal generated from the color subcarrier μo.

一方、(c)は位相歪のない場合の副搬送波μoである
。同図の点X1.Xz、Xa。
On the other hand, (c) is the subcarrier μo when there is no phase distortion. Point X1 in the same figure. Xz, Xa.

X s’ 、 Xx’は極大値を取る点を示す。これら
の極大値を取る点は、極大値検出ゲート信号によりXL
 、 Xl’  の極大点が選択され、Xt 、 XI
’に対応する時刻a、a’ がμoの基準位相π/2の
点として位相再生を行なう。
X s' and Xx' indicate points that take local maximum values. The points that take these maximum values are determined by the maximum value detection gate signal.
, Xl' is selected, and Xt, XI
Phase recovery is performed with time a corresponding to ', a' as a point at the reference phase π/2 of μo.

一方、(d)に示すように、伝送歪等の影響により位相
歪を受けた副搬送波μoにおいては、極大値は、それぞ
れ、X 1 、 X2 、 Xs + Xt’ +Xx
’  の点となる。そして、極大値検出ゲート信号によ
りXz、 Xz’の極大点が選択され、これらの極大点
を基準位相としてμoの位相再生を行なう。
On the other hand, as shown in (d), in the subcarrier μo that has undergone phase distortion due to the influence of transmission distortion, the local maximum values are X 1 , X 2 , Xs + Xt' + Xx, respectively.
' is the point. Then, the maximum points of Xz and Xz' are selected by the maximum value detection gate signal, and the phase of μo is recovered using these maximum points as the reference phase.

すなわち、本発明では、上述したμo極大値の選択によ
る基準位相の設定を行なうことにより。
That is, in the present invention, the reference phase is set by selecting the maximum μo value described above.

伝送歪等の影響を受けにくい副搬送波再生ができる。Subcarrier regeneration that is less susceptible to transmission distortion, etc. is possible.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図により説明する。本実
施例では、受信信号を色副搬送波の4倍の4fscで標
本化した場合のディジタル信号処理の場合を示す。
An embodiment of the present invention will be described below with reference to FIG. This embodiment shows a case of digital signal processing in which a received signal is sampled at 4 fsc, which is four times the color subcarrier.

受信テレビジョン信号は、A/D変換回路1で4fsc
のディジタル信号に変換される。一方、タイミング抽出
回路已においては、信号処理に必要なfsc=4fsc
、ならびに水平、垂直同期信号HD。
The received television signal is converted to 4fsc by A/D conversion circuit 1.
is converted into a digital signal. On the other hand, in the timing extraction circuit, fsc=4fsc required for signal processing.
, as well as horizontal and vertical synchronization signals HD.

VDを抽出する。HD、VD信号は、ライン制御回路4
において、副搬送波μoの挿入されている走査線を特定
し、この期間において、μo再生回路5では前述の手法
に従った副搬送波μoの極大点、ならびにJ scとの
位相関係によって、再生副搬送波μoを生成する。
Extract the VD. The HD and VD signals are sent to the line control circuit 4.
In this period, the scanning line in which the subcarrier μo is inserted is specified, and during this period, the μo reproducing circuit 5 detects the reproduced subcarrier μo based on the maximum point of the subcarrier μo according to the method described above and the phase relationship with J sc. Generate μo.

デコーダ回路3においては、これらの信号を用いて、も
との輝度信号Y2色色差分T、Qに復調する。この機能
に関しては、本発明とは特に関係がないため、説明は省
略する。
The decoder circuit 3 uses these signals to demodulate the original luminance signal Y into two color differences T and Q. Since this function has no particular relation to the present invention, a description thereof will be omitted.

第2図は、第1図のμo再生回路5の具体的な一実施例
を示す。A/D変換回路1のデータ系列は、ラッチ回路
6により、4 f scのクロックによって隣接する3
画素のデータA、B、Cをラッチする。一方、大小比較
回路7では、BとA、あるいはCとの大小比較を行ない
、BAA、あるいはB>Cの場合には1、それ以外の時
にはOを出力する。したがって、大小比較回路7の出力
がいずれも1の場合には、Bが極大値を取ることに相当
する。
FIG. 2 shows a specific embodiment of the μo regeneration circuit 5 shown in FIG. The data series of the A/D conversion circuit 1 is converted into three adjacent data by a latch circuit 6 using a clock of 4 fsc.
Latch pixel data A, B, and C. On the other hand, the magnitude comparison circuit 7 compares B and A or C, and outputs 1 if BAA or B>C, and O otherwise. Therefore, when the outputs of the magnitude comparison circuit 7 are all 1, this corresponds to B taking the maximum value.

判定回路8では、f scよりつくられた極値検出ゲー
ト信号、副搬送波μo挿入のライン情報、ならびに大/
J%比較回路7の出力信号より、再生副搬送波の基準位
相点を判定する。副搬送波μoが第3図(c)に示すよ
うな位相歪のない場合における基準位相点の判定のタイ
ムチャートを第4図に示す。
The determination circuit 8 uses the extreme value detection gate signal generated from fsc, the line information for subcarrier μo insertion, and the large/
The reference phase point of the reproduced subcarrier is determined from the output signal of the J% comparison circuit 7. FIG. 4 shows a time chart for determining the reference phase point when the subcarrier μo has no phase distortion as shown in FIG. 3(c).

第4図に示した様に、基準位相点は20クロック周期で
発生するが、雑音等の影響によってこの基準位相点が誤
判定される可能性がある。このため、20クロツク遅延
回路9でそれぞれ基準位相点を20クロツク遅延させた
ものとをAND回路10でとり、基準位相点の周期が3
回連続して一致した場合にかぎり、位相情報発生回路1
1の初期値をπ/2に設定する。この処理によって、雑
音等による誤動作を大幅に低減できる。位相情報発生回
路11は、第5図に示すように位相情報AOに対応する
π/2を基準に、4fscクロツク毎に位相が3π/1
0づつ進んだ位相に相当するアドレスを20クロック周
期で発生し、μo生成回路12では、このアドレスに従
って第5図に併せて示した副搬送波信号を生成する。な
お、この機能はROMなどで簡単に実現することができ
る。
As shown in FIG. 4, the reference phase point occurs every 20 clock cycles, but there is a possibility that this reference phase point will be erroneously determined due to the influence of noise and the like. Therefore, the reference phase point delayed by 20 clocks by the 20 clock delay circuit 9 is taken by the AND circuit 10, and the period of the reference phase point is 3.
The phase information generating circuit 1
Set the initial value of 1 to π/2. This processing can significantly reduce malfunctions caused by noise and the like. As shown in FIG. 5, the phase information generating circuit 11 changes the phase to 3π/1 every 4 fsc clocks based on π/2 corresponding to the phase information AO.
An address corresponding to a phase advanced by 0 is generated at 20 clock cycles, and the μo generation circuit 12 generates the subcarrier signal shown in FIG. 5 in accordance with this address. Note that this function can be easily implemented using a ROM or the like.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、簡単な構成で、伝送歪の影響を受けに
くく、また、雑音等による誤動作の少ない高精度の副搬
送波の再生回路を簡単な構成で実現でき、効果は大きい
According to the present invention, a highly accurate subcarrier regeneration circuit that is less susceptible to transmission distortion and less likely to malfunction due to noise etc. can be realized with a simple configuration, and the effects are great.

なお、本発明においては、副搬送波μoが色副搬送波f
 scの315倍の場合について説明したが、一般にμ
oがQ/m  fsc(Q、m整数)の比例関係のもの
でも有効なことは明らかである。
Note that in the present invention, the subcarrier μo is the color subcarrier f
Although we have explained the case of 315 times sc, in general μ
It is clear that it is also valid even if o is proportional to Q/m fsc (Q, m integer).

また、本発明では、ディジタル信号処理の場合を示した
が、アナログ信号処理に対しても同様に本発明が適用可
能なことは明らかである。
Further, although the present invention has been described in the case of digital signal processing, it is clear that the present invention is similarly applicable to analog signal processing.

さらに1本発明では、極大値を例に説明等を行なってい
るが、極小値であっても同様なことが成立することも明
らかである。
Furthermore, in the present invention, explanations are given using local maximum values as an example, but it is clear that the same thing holds true even for local minimum values.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図は、μ
Oの再生回路部の一実施例の構成図、第3図は、本発明
の概念説明図、第4図はμoの再生回路部のタイムチャ
ート図、第5図は再生搬送波の位相情報である。 1・・・A/D変換回路、2・・・タイミング抽出回路
。 3・・・デコーダ回路、4・・・ライン制御回路、5・
・・μo再生回路、6・・・ラッチ回路、7・・・大小
比較回路、8・・・判定回路、9・・・20クロック遅
延回路、10・・・AND回路、11・・・位相情報発
生回路、12・・・μo生成回路、         
  7−代理人 弁理士 小用勝h ′) \3./ 第2図
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a conceptual diagram of the present invention; FIG. 4 is a time chart of the μo regeneration circuit; and FIG. 5 is phase information of the regenerated carrier wave. . 1... A/D conversion circuit, 2... Timing extraction circuit. 3... Decoder circuit, 4... Line control circuit, 5...
... μo regeneration circuit, 6 ... latch circuit, 7 ... magnitude comparison circuit, 8 ... judgment circuit, 9 ... 20 clock delay circuit, 10 ... AND circuit, 11 ... phase information Generation circuit, 12...μo generation circuit,
7-Agent, Patent Attorney, Masaru Koyōh') \3. / Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1、有意情報を副搬送波μoで振幅変調して多重伝送を
行なう際、副搬送波μoを色副搬送波fscと比例関係
になる如く設定し、副搬送波μoの極大値、あるいは極
小値の発生位置と色副搬送波fscとの位相関係より副
搬送波μoの位相再生を行う手段を有してなることを特
徴とする副搬送波信号の再生回路。
1. When performing multiplex transmission by amplitude modulating significant information with a subcarrier μo, the subcarrier μo is set to be in a proportional relationship with the color subcarrier fsc, and the position of the maximum value or minimum value of the subcarrier μo is 1. A reproducing circuit for a subcarrier signal, comprising means for regenerating the phase of a subcarrier μo based on its phase relationship with a color subcarrier fsc.
JP62056523A 1987-03-13 1987-03-13 Subcarrier signal regeneration circuit Expired - Lifetime JP2550053B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62056523A JP2550053B2 (en) 1987-03-13 1987-03-13 Subcarrier signal regeneration circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62056523A JP2550053B2 (en) 1987-03-13 1987-03-13 Subcarrier signal regeneration circuit

Publications (2)

Publication Number Publication Date
JPS63224492A true JPS63224492A (en) 1988-09-19
JP2550053B2 JP2550053B2 (en) 1996-10-30

Family

ID=13029473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62056523A Expired - Lifetime JP2550053B2 (en) 1987-03-13 1987-03-13 Subcarrier signal regeneration circuit

Country Status (1)

Country Link
JP (1) JP2550053B2 (en)

Also Published As

Publication number Publication date
JP2550053B2 (en) 1996-10-30

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