JPH0349234B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a digital television receiver that performs baseband video signal processing digitally, and particularly to a digital television receiver that can normally receive signals other than standard mode signals. [Technical background of the invention and its problems] Conventionally, all signal processing in television receivers has been performed by analog signal processing, but the following improvements should be made especially in the analog signal processing after the video stage. There was a problem. In other words, in terms of performance, it is a problem caused by the processing performance on the time axis, which is considered to be a general weakness of analog signal processing.Specifically, it is a problem caused by the processing performance on the time axis, which is considered to be a general weakness of analog signal processing. These include separation performance, various image quality improvement performance, and synchronization performance. On the other hand, cost and manufacturing issues are that even if the circuit is integrated into an IC, there are still many external components and adjustments to be made. In order to solve these problems, it is being considered to completely digitalize the signal processing involved in color signal demodulation after the video stage. In such so-called digital television receivers, there is no problem with normal broadcast signals, especially regarding separation of luminance signals and chromaticity signals (Y-C separation), but some signal generators, Y-C separation becomes difficult for video signals other than standard mode, in which color subcarrier frequencies and horizontal synchronization frequencies do not have a corresponding relationship, which come from video game devices, etc., and there is a risk that image quality may deteriorate. . [Object of the Invention] An object of the present invention is to provide a digital television receiver that operates normally without requiring any switching operation even for signals other than standard mode video signals such as broadcast signals. There is a particular thing. [Summary of the Invention] The present invention accurately detects whether an incoming video signal is in the standard mode or not, and switches the separation method in the Y-C separation circuit based on the detection. That is, the present invention provides means for detecting a horizontal synchronization signal from a digital video signal, a horizontal period memory circuit for storing the period value of the horizontal synchronization detection signal obtained by this means, and an incoming video signal based on the output of this memory circuit. a horizontal standard mode detection circuit for detecting whether or not the is in the standard mode; and a circuit for separating a luminance signal and a chromaticity signal from the digital video signal, the circuit being controlled by a standard mode detection signal from the horizontal standard mode detection circuit, When the incoming video signal is detected as standard mode, it is separated by configuring a filter using vertical correlation, and when it is not detected as standard mode, it is separated by configuring a filter using horizontal sample points. The present invention is characterized in that it is equipped with a Y-C separation circuit that performs the following. [Effects of the Invention] According to the present invention, it is automatically detected whether or not the incoming video signal is in the standard mode, and based on that, the Y
Since the -C separation circuit is automatically switched to a state suitable for the incoming video signal, it is compatible with all video signals other than broadcast signals, and can perform good image reproduction. [Embodiment of the invention] FIG. 1 shows a digital TV according to an embodiment of the invention.
A block diagram of the main parts of the receiver is shown. In the figure, an AC-coupled analog video signal 1 is input to a buffer circuit 2 .
The output 3 of the buffer circuit 2 is guided to a low pass filter (LPF) 4 for band limitation. LPF4
The cutoff frequency of this system is NTSC,
It is set to 5.5MHz because it is shared by PAL. The band-limited video signal output 7 is guided to a buffer amplifier circuit 8. The buffer amplifier circuit 8 is adjusted so that when the analog video signal 1 is input at 1 V _pp , the input signal 9 to the A/D converter (ADC) 10 at the subsequent stage becomes approximately 2 V _pp .
The ADC 10 samples the input signal 9 using a sampling clock (φ _S ) 12, quantizes it to, for example, 8 bits, and outputs it. The frequency _S of the sampling clock (φ _S ) 12 is _S = 4 _SC ( _SC = color subcarrier frequency). φ _S 12 is led to a digital circuit section 62 . _φS 1
An 8-bit digitized video signal 11 (hereinafter referred to as a DVS signal) synchronized with DVS 2 is also led to the digital circuit section 62 in the same manner. Digital circuit section 6
All blocks within 2 are constructed of digital circuits. The DVS signal 11 is guided to a synchronization detection/timing generation circuit 27. The synchronization detection/timing generation circuit 27 detects a synchronization pulse from the DVS signal 11 and generates various timing signals 28, 29, 30, 31, and 32 according to the synchronization pulse detection signal. The pedestal clamp circuit 19 is a circuit for DC reproduction of the video signal 1, and the timing signal 3.
2 detects the pedestal level of the DVS signal 11, and outputs a control signal 20 so that the pedestal level becomes a predetermined value. The output 20 of the clamp circuit 19 is guided to a D/A converter (DAC) 21 and converted into an analog signal. The output 22 of the DAC 21 is superimposed on the input of the buffer amplifier circuit 8 as a clamping voltage via a resistor to control its DC level. The timing signal 31 is a PLL (Phase Locked
Loop) This is a timing signal necessary for the control circuit 23. The PLL control circuit 23 is a circuit for controlling the frequency and phase of the sampling clock (φ _S ) 12. That is, ADC 10 ~ synchronization detection/timing generation circuit 27 ~ PLL control circuit 23 ~ DAC
A PLL circuit is formed by a loop of 16 to VCXO13 to ADC10. In this example, basically
In the case of NTSC input, the PLL is applied so that one of the phases of φ _S 12 coincides with the I-axis, and in the case of PAL input, so that it coincides with the U-axis.
NTSC and PAL input switching information is signal 15 (hereinafter referred to as
NTSC/PAL switching signal). The control signal output 24 of the PLL control circuit 23 is a DAC
16 and converted into an analog signal 14.
This analog control signal 14 is guided to a voltage controlled crystal oscillator (VCXO) 13, which causes the VCXO
A sampling clock φ _S 12 is obtained at the output of 13. The crystal oscillator of the VCXO 13 is switched by the NTSC/PAL switching signal 15, so that a predetermined φ _S can be obtained. Note that the PLL in this example
A principle implementation of the control system is described in US Pat. No. 4,291,332. In Figure 1, control data 17 is digital.
This is digital data that controls the TV receiver, and is obtained from, for example, a remote control receiving circuit (not shown). The control data 17 is decoded by a decoder 47 to control each part. This decoded control signal is
It consists of a color saturation and contrast/brightness control signal 48 and a hue control signal 49. Hue control signal 49 is PLL
Through the control circuit 23, the sampling clock φ _S 1
By changing the phase of 2, the hue is controlled. A horizontal flyback signal (hereinafter referred to as _HFB signal) 18 is also input to the PLL control circuit 23, and a well-known PAL Ident signal (hereinafter referred to as PID signal) 25 at the time of PAL input.
occurs. The timing signal output 29 of the synchronization detection/timing generation circuit 27 is connected to the horizontal countdown circuit 32.
guided by. Horizontal countdown circuit 32 is _HFB
Horizontal synchronized playback is performed from the timing signal 29 using the signal 18, and the horizontal drive signal ( _HD out) 34
Output. The horizontal countdown circuit 32 also determines the relationship between the sampling clock (φ _S ) 12 and the horizontal synchronization signal, and in the case of an NTSC signal input, determines the relationship between the sampling clock (φ _S ) 12 and the horizontal synchronization signal.
When ≒910 _H ( _H ; horizontal frequency), φ _S for PAL
Horizontal synchronization standard mode (HMOD) when ≒1135 _H
A signal 35 is output. The timing output 30 of the synchronization detection/timing generation circuit 27 and the output 33 of the horizontal countdown circuit 32 are led to a vertical countdown circuit 36 that performs vertical synchronization reproduction.
The vertical countdown circuit 36 outputs a reproduced vertical synchronization signal ( _VD out) 37. _HD out signal 34 is a driver circuit (H driver)
After being amplified at 50, the signal is guided to a horizontal deflection system (not shown) via a signal line 51. On the other hand, _{the VD} out signal 37 is a V ramp height circuit 5 including a vertical ramp generation and vertical height control circuit.
2, whose output 53 is a vertical deflection system (omitted)
guided by. The DVS signal 11 also includes a luminance signal Y and a chromaticity signal C.
The signal is guided to a Y-C separation circuit 38 that separates the signal. Y
The -C separation circuit 38 consists of a separation circuit (known as a comb filter) that performs Y-C separation using vertical correlation, and a filter that uses horizontal sample points without using vertical correlation and uses only horizontal correlation. HMOD signal 35 selects the separating circuit. That is, when HMOD="1", a comb filter performs Y-C separation, and when HMOD="0", a bandpass filter is used to perform Y-C separation. The Y-C separation circuit 38 has
An NTSC/PAL switching signal is introduced, and one horizontal delay amount is switched according to this switching signal. This delay amount is 910 bits of delay for NTSC and 1135 bits of delay for PAL (known as the 1H delay line). The separated color signal (C signal) 39 and the pulse (φ _C 26 and PID signal 2
5. The control signal 48 and burst flag pulse BFP 28 are guided to the color processing circuit 41. The color processing circuit 41 includes an automatic color saturation control (ACC) circuit, a color killer circuit, and 2-axis synchronous detection using φ _C 26 as a reference pulse to generate color signals (I and Q signals for NTSC, U and V signals for PAL).
It consists of a color demodulation circuit that demodulates the signal (signal). A control signal 48 input to the color processing circuit 41 controls the ACC circuit to control color saturation, that is, color density. As the output 42 of the color process circuit 41, demodulated outputs I/U and Q/V are obtained. The luminance signal (Y' signal) 40 separated by the Y-C separation circuit 38 is guided to the Y process circuit 43. The other input of the Y process circuit 43 is a control data signal 48, and brightness and contrast are controlled by this signal. This Y process circuit 43 is composed of a circuit for obtaining horizontal and vertical contour correction signals of a brightness and contrast control circuit, and outputs a controlled or corrected Y signal 44. The color demodulated signal 42 and the Y signal 44 are led to an RGB matrix circuit 45, and are converted into signals 46 of the three primary colors R, G, and B by a predetermined matrix calculation. The R, G, and B signals 46 are converted back into analog signals by the DAC 54. The DAC 54 is composed of three 8-bit DACs for R, G, and B, and its output 55 is led to a buffer amplifier 56. A buffer amplifier 56 amplifies the input signal and outputs R, G, and B outputs 57, 58, and 59 to a color output circuit (not shown).
lead to. The color output circuit is connected to the CRT60. Next, a detailed explanation will be given of the specific configuration of the main parts shown in FIG. First, FIG. 2 is a diagram for explaining notation regarding the following detailed explanation. Note that positive logic will be used in the following explanation. Figure 2a shows an adder. It is shown that the A+B output 73 becomes L bits with respect to the A input 70 consisting of N bits and the B input 71 consisting of M bits. Co72 indicates a carry input added to the lowest bit. As shown in Figure a, signals consisting of multiple bits will be expressed as N'b, M'b, L'b. Figure b shows a subtracter. A input 75, B
The inputs 77 are added by an adder 78, and the A-B outputs 7
It becomes 6. As shown in the figure, the input to be subtracted from among the inputs of the adder 78 is given the symbol 1. Figure c shows an N-bit latch circuit.
Input 80 is led to latch 83 and latched at the rising edge of clock 79, resulting in output 84. In the figure, a signal 82 indicates an input to the reset terminal R, and when the signal 82 is "1", the latch output 84 becomes all "0". Further, the signal 81 in the figure indicates input to the preset terminal Pr, and this signal 81 is "1".
At this time, the output 84 becomes all "1". d in the figure shows a shift register. signal 8
5 indicates an input, a signal 86 is a shift clock (φ), and a signal 88 is an output. Signal 87 is the input of reset terminal R, and when this is "1", output 8
8 becomes all "0". Figure e shows a synchronous M-bit counter. The input clock is 90, the clock synchronous reset signal is 91, and the output is 92. N in the diagram
indicates a counter number, and j=1 to M indicate M counter stages. Note that for a counter having a reset terminal asynchronous to the clock 90, the reset terminal is expressed as R ^* . Figure f in the figure shows a clock synchronized presettable counter. That is, 96 indicates a preset data input, and 95 indicates a preset timing signal input. Figure g in the figure shows a NAND type set-reset (RS) flip-flop, in which the terminal input 99 is "0".
At this time, the Q output 101 becomes "1". h in the figure shows the data selector, A input 10
4. B input 105 is set to 1 according to selection signal S109
Output as 08. The logic of output 108 is S・A
It becomes +B. That is, when S="1", the output 108
The information of the A input 104 is output, and S="0"
At this time, the information of the B input 105 is output to the output 108. In addition, in the following explanation, when multiple stages of counters and count states are expressed in units of input clocks, the counter outputs are expressed as Q _N , Q N-1, Q _N-1 ,
…When Q ₃ , Q ₂ , Q ₁ , “000…000” is zero,
“000…001” is 1, “000…010” is 2, “000…011”
will be expressed as 3. (Synchronization detection/timing generation circuit) In Figure 1, the DAC for pedestal clamp
When output 22 of 21 is 0V, output 7 of buffer 6
An analog video signal with a DC clamp voltage of 0V can be obtained. Now, when the DC clamp voltage is 0V, APL (Average Picture
When the lowest signal (Level) is input, the ADC 10 dynamic ranges 3-1 and 3-2 are adjusted so that the input of the ADC 10 has a waveform like 3-3 as shown in Figure 3. Buffer 2, LPF 4, buffer 6, and buffer amplifier 8 in Figure 1 have been adjusted. In Figure 3, the pedestal level (PDL)
Set 3-4 to the value “00101111” and set horizontal synchronization signal separation level (SDLH) 3-5 to (PDL) 3-4.
Select approximately 1/2 level “00001111”. A pedestal clamp control loop in an embodiment of the present invention clamps the pedestal level of the input video signal 1 to a value of (PDL) 3-4.
This clamp circuit will be described later. Figure 4 shows a signal 4-1 with a pedestal clamp voltage of 0V regarding the dynamic range of ADC10.
This shows the signal 4-2 with normal clamping. In Fig. 4, (SDLV) 4-3 indicates the vertical synchronization signal separation level, and in order to ensure vertical synchronization reproduction especially against disturbances such as ghosts,
It is closer to (PDL) 3-4 than (SDLH) 3-5. In this example, (SDLV)4-3 is set to "00011111". In this way, the digital video signal DVS1 is connected to the pedestal clamp.
1 is led to the synchronization detection/timing generation circuit 27. FIG. 6 shows the configuration of the synchronization detection/timing generation circuit 27. This circuit 27 is broadly divided into a synchronization separation/horizontal synchronization pulse width detection circuit system 120, a horizontal synchronization periodicity/continuity detection circuit system 121, and a timing generation circuit system 122. First, the input DVS signal 11 is for horizontal synchronization,
The signals are guided to a horizontal synchronization separation circuit 123 and a vertical synchronization separation circuit 125 for separating the synchronization signals for vertical synchronization, respectively, and the synchronization separation signals 124 and
CSV signal 126 is separated. Synchronous separation signal 1
24 is filtered by an LPF 127 that removes high frequency components, that is, color frequency components. LPF1
The output 128 of 27 is a composite synchronization signal (CSH), and a horizontal synchronization pulse width detection counter circuit 129
guided by. The output 130 of the counter circuit 129 is input to the width detection circuit 131, and when this count value reaches a predetermined value, that is, when the pulse width of the horizontal synchronization signal reaches a predetermined width, the first horizontal synchronization detection signal (H _S ' signal ) 132 is output from the width detection circuit 131. Width detection counter control gate circuit 133,
When the H _S ' signal 132 is output from the width detection circuit 131, the counter circuit 129 is controlled so as not to accept the CSH signal 128 input for a certain period of time, thereby preventing horizontal synchronization malfunction due to cracking of the CSH signal 128 due to a signal input with a large ghost. This is to prevent CSH signal 128 and counter circuit output 1
30 is led to a horizontal synchronization timing control circuit 135 that controls the fall timing of the CSH signal 128. This horizontal synchronization timing control circuit 135
If the CSH signal 128 does not fall within a certain period from the output timing of the H _S ' signal 132,
Signal RS4136 for inactivating the timing generation circuit system 122 that generates various timing signals for burst clamp pulses, PLL, and clamping.
occurs. In this way, the given conditions are met.
Since the PLL, clamp, etc. are operated only when the CSH signal 128 arrives, a very stable PLL and clamp circuit (resistant to external disturbances) can be constructed. The horizontal synchronization periodicity/continuity detection circuit system 121 is
Detects the periodicity and continuity of the horizontal synchronization signal (actually H _S ' signal) and detects the periodicity and continuity of the horizontal synchronization signal (actually H S ' signal).
Only the H _S ' signal is obtained as the second horizontal synchronization detection signal (H _S signal) 139. The period detection counter 141 is an 11-stage counter that counts φ _S as a reference clock, and its 11-bit output 143 is led to a period memory circuit 144 that can store count values for two periods. now,
When the H _S signal 139 with predetermined periodicity and continuity is obtained at the output of the horizontal synchronization periodicity/continuity detection circuit 138, the signal is output from the latch pulse generation circuit 146.
The SR6Q ₁ out signal 147 is generated, which causes the output 143 of the counter 141 to be output from the periodic memory circuit 1.
44. The difference detection circuit 148 detects the difference between the values for two periods in the periodic memory circuit 144, and the determination circuit 151 outputs a determination signal (DCK signal) 152 from the output 150 of the difference detection circuit 148 when this difference is less than a predetermined value. Output. Next, in the timing generation circuit system 122,
The H _S signal 13 is detected by the horizontal synchronous fall detection circuit 153.
9 and the RS4 signal 136, and when the falling edge is detected, the counter reset flip-flop 156 is controlled so that the counter 158 starts counting, and a reset signal 157 is generated. The counter 158 has a six-stage configuration.
Output 159 and output SR9 of the PLL control circuit described later
PLL by _Q1 signal 161 and _SR9Q1 signal 162,
Various timing signals required for clamp circuit operation 1
63 to 169 and a burst flag pulse (BFP) 28 are generated from a burst flag/PLL/clamp timing generation circuit 160. The synchronization detection/timing generation circuit 27 shown in FIG. 6 will be explained in more detail. 6 in Figure 7
A specific circuit diagram of the synchronization separation/horizontal synchronization width detection circuit system 120 and the horizontal synchronization periodicity/continuity detection circuit system 121 shown in the figure is shown. In FIG. 7, the DVS signal 11 is a comparison circuit (Comp1) 1 serving as a horizontal synchronization separation circuit 123.
80 as an X ₁ input, and is compared with a horizontal sync separation level (SDLH) 181 which is an X ₂ input, and an output satisfying X ₂ ≧X ₁ is obtained as a separated signal 124 . Similarly, a vertical synchronization separation signal (CSV) 126 is obtained from a comparison circuit (Comp2) 182 serving as a vertical synchronization separation circuit 125. Horizontal and vertical synchronization separation level (SDLH) 181, (SDLV)
183 is as explained in Figures 3 and 4.
Since SDLH="00001111" and SDLV="00011111", each of the comparison circuits 180 and 182 can be realized with one simple gate. The output 124 of the comparison circuit 180 is guided to a shift register 184 having four stages. This is the shift clock φ _S of the shift register 184. The output of each bit of this shift register 184 is given to a 4-input NAND gate 185,
CSH (the inverse of CSH) is obtained as output 128. Shift register 184 and gate 185
The LPF 127 is configured to remove components below _{the SC} period, that is, color frequency components. On the other hand, the counter circuit 129 and the width detection circuit 13
1. In the gate circuit 133 and the horizontal synchronization timing control circuit 134, as shown in the time chart in FIG. 8, when CSH="1", the counter 1
87 starts counting, and the "48" count output of this counter 187 (output of AND gate 190)
is guided to a shift register 191, and a width detection pulse (HS') 132 is obtained through an AND gate 192. When the HS' signal is obtained, the RS flip-flop 193 is set, and its output 195 forces the reset signal 189 of the counter 187 to "0" through the gate 188. The OR gate 196 is a gate that obtains the horizontal synchronization timing control output, and the count value of the counter 187 is from "48" to
Outputs “1” during “128”. Now gate 196
When the CSH signal falls (signal 128 rises) during the period when the output of the NAND gate 197 is "1", the waveform shown as RS4 in FIG.
It can be seen that the falling timing of the CSH signal is given. NAND gate 194 is counter 18
When the count value of 7 is "239", the Q output 195 of the flip-flop 191 is inverted. As a result, after the H _S ' signal 132 is output, "240" - "48"
= “192” (φ _S unit), the counter 187 is CSH
Operates so as not to accept signal input. The AND gate 132-2 outputs the logic output of Q18 and RS4Q (described later) as 132-1. The H _S ' signal 32 is guided to a horizontal synchronization periodicity/continuity detection circuit system 121. Before explaining the detection circuit system 121, let us first explain the digital TV receiver of this embodiment.
Horizontal frequency range and period detection counter 141 when receiving NTSC and PAL signals
The operation of is described below. The NTSC signal defined by broadcast waves is 4 _SC = 910 _H
( _H : horizontal frequency, _SC : color subcarrier frequency, 4 _SC = 14.3MHz). On the other hand, signals such as 4 _SC ≠ 910 _H also exist in some color bar signal generators, video games, etc. That is, the color subcarrier frequency _SC
There is a signal that has no relationship between the horizontal frequency H and the horizontal frequency _H. Now, if we assume that the corresponding horizontal frequency range is _H = 15.73±0.5kHz to avoid any practical problems, the sample clock φ _S (=4 _SC ) will be "880" at the counter 187 within one horizontal period corresponding to this range. ~“944”
It can be counted. For PAL, 4 _SC ≒1135 _H (4 _SC ≒17.73MHz)
Similarly, if _H = 15.625kHz±0.5kHz,
The number of φ _S that can be counted in one horizontal period is “1099”
~ “1173”. Periodicity detection of the horizontal synchronization signal must cover the above-mentioned horizontal frequency range. Therefore, the period detection counters 141 and 213 shown in FIG. 7 that detect periodicity are counters that can count one horizontal period with φ _S as a reference, and have an 11-stage configuration. When the H _S ' signal 132 arrives, the counter 213 counts "144" in NTSC.
By presetting the count to "64" in PAL, the timing of periodicity detection can be determined easily, and at the same time, such a preset also allows the circuit configuration of the horizontal countdown circuit 32 in FIG. 1 to be adjusted as described later. It can be simplified. FIG. 9 shows the H _S ' signal 132, the gate signal (HM _as R) indicating the horizontal period corresponding range, and the counter 213.
shows the relationship between the count values of As shown in the figure, only the H _S ' signal 132 which is obtained continuously at a predetermined period is obtained as the horizontal synchronization detection signal H _S by the product logic shown as H _S =H _S '·HM _as R. SR6Q ₁ is this H _S signal 1
39 and _S as a shift clock. 9- in Figure 9
1 and 9-2 indicate the counting status of the counter 213 when receiving each of the NTSC and PAL signals. FIG. 10 shows a time chart for detecting periodicity and continuity of the H _S ' signal 132. HM _as R signal is
When receiving an NTSC signal, the signal rises when the counter 213 counts "1024" as shown by 10-1, and falls in synchronization with the fall of the H _S ' signal. Also, 10-
If the H _S ' signal is missing as shown in 3, HM _as R
The signal falls at “1088” count, counter 2
13 remains preset to “144” count,
Wait for the arrival of the next H _S ′ signal. When the H _S ' signal is obtained again as shown at 10-4, the signal shown at 10-5
The H _S signal is obtained from the H _{S '} signal. The basic operation is the same when receiving a PAL signal. As shown in FIG. 10, it will be understood that the horizontal synchronization detection signal H _S is obtained as a highly accurate signal that is resistant to external disturbances. In FIG. 7, the HM _as R signal is obtained as the output of the OR gate 207, and the H _S signal 139 is obtained as the output of the AND gate 208. H _S 'signal 1
It is reset by the inversion of 32, and the NOR gate 211
The RS flip-flop 21 is set by the output of
The Q output of 2 is the control signal when the H _S ' signal is missing (10th
RS3Q) in the figure is given. The preset signal of counter 213 is obtained as output 203 of OR gate 204. As mentioned above, the preset data generation circuit 201 controlled by the NTSC signal generates the digital value "00010010000" corresponding to the "144" count when receiving the NTSC signal, and generates the digital value "00010010000" corresponding to the "64" count when receiving the PAL signal. The value “00001000000” is generated respectively. H _S signal 139 is directed to shift register 215 . _Q1 output 14 of this shift register 215
7 provides the timing for latching the 11-bit output 214 of the counter 213 into the latch 216. The output 149 of latch 216 is directed to latch 217. These two stages of latches 216 and 217 constitute a first horizontal period memory circuit 144, which stores data for two periods from the counter 213. A subtracter 219 serving as a difference detection circuit 148 detects the difference between the values of the latches 216 and 217, and outputs a difference output 220 to the determination circuit 151. In the determination circuit 151, 11 of the difference output 220
The upper 9 bits of the bit data are input to a NAND gate 221 and an AND gate 222, and the outputs of the gates 221 and 222 are input to an OR gate 223 to obtain a DCK signal 152 as an output. That is, if the difference between the output 149 of the latch 216 and the output 218 of the latch 217 is within ±"3", the DCK signal 152 becomes "1". The H _S signal 139, the output 149 of latch 216, the DCK signal 152, and the output 147 of shift register 215 are directed to horizontal countdown circuit 32 of FIG. FIG. 11 shows a more specific configuration of the burst flag/PLL/clamp timing generation circuit system 122. The inverted signal 232 of the H _S signal 139 is
Set the RS flip-flop 234 and RS4
Signal 136 resets flip-flop 234. Output 23 of flip-flop 234
5 is a signal that rises in synchronization with the falling edge (trailing edge) of the horizontal synchronizing signal, and is guided to the shift register 236. ₁ output 154 of shift register 236
is a one-stage counter (flip-flop) 23
Guided by 7. Now Q ₁ output 1 of shift register
54 changes from “0” to “1”, the counter 237
The Q41 output 157 becomes "0", whereby the counter 238 is released from the reset state and starts counting. The counter 238 has a 6-stage configuration, and uses the logic of outputs Q ₃₆ , Q ₃₅ , and Q ₃₃ to connect NAND gate 2.
Self-resetting is applied via 39. The operation of the timing generation circuit 160 is shown in FIG. In Figure 12, the CHS signal (LPF in Figure 7)
127 output), H _S signal 139, φ _S , Q ₁ output 154 of shift register 236, counter 237 output
Q ₄₁ output 157, Q ₃₁ of counter 238, Q ₃₂ ...
In response to the Q ₃₆ output, various timing signals are shown along with the count value of the counter 238. These timing signal inputs, outputs 28, 163, 16
4,165,166,167,168,169,
157, 230, 161, and 162 will be explained as appropriate in the detailed explanation of the clamp circuit and the PLL control circuit, which will be described later. (Pedestel Clamp Circuit) The pedestel clamp circuit 19 in FIG.
As shown in the waveform of Figure 4-2, the incoming DVS
Pedestal level of signal 11 (PDL) 3-4
This is a circuit that clamps to the value “00101111”. FIG. 13 shows a specific circuit diagram of the pedestal clamp circuit 19. The HSD signal 280 in the figure is a signal indicating a synchronization detection state that becomes "1" when the H _S signal 139 is obtained, and the synchronization detection judgment circuit 285
If HSD is currently input to “0”, that is, synchronization detection is not being performed, timing information to apply pedestal clamping (for example, BFP
28), it is necessary to cut out the synchronizing signal part first. Therefore, HSD signal 2
80 changes from "1" to "0", the shift register 284 detects the fall of the HSD signal 280,
With this detection signal 276 (output of gate 275),
The latch 272 that stores the clamp voltage as a digital quantity is reset. When the output 20 of the latch 272 becomes all "0", the clamp voltage (output 22 of the DAC 21 in FIG. 1) becomes 0V, and the clamp control system is set to the initial state. Generally, when a video signal input exists, the relationship between the dynamic range of the ADC and the signal at the time of initial setting is as shown by 4-1 in FIG. 4. 8, which is the DVS signal 11 in FIG.
The output of the gate 252 that takes the OR logic of the bit signal becomes "0" only during the period when the input signal crosses the LSB side end of the dynamic range of the ADC 10, that is, when the DVS signal 11 becomes all "0". . The output of this gate 252 is led to an eight-stage shift register 253. NOR gate 2 which receives all outputs of shift register 253 as input
The output of the gate 252 is connected to the output 255 of the gate 54.
A signal corresponding to the signal passed through the LPF is obtained as "1". These gates 252, shift registers 253, and gates 254 control the DVS signal 11.
A level detection circuit 281 is configured. The rising timing of the output signal 255 of the detection circuit 281 is detected by the NAND gate 256, and the RS flip-flop 257 is set. The Q output 258 of this flip-flop 257 is led to the B input of a 10-bit data selector 269. In addition,
At this time, the B input data of the data selector 269 is
It is assumed that the MSB side is converted into "1111111000" by an encoder (not shown) and input. 10-bit output 270 of data selector 269
The 12-bit output 273 of latch 272 is LSB
are matched and the difference is taken by a subtracter 271. The difference signal is the timing of _Q3 output of shift register 253 (output timing of AND gate 278)
is written to latch 272 again. By repeating the above operation, the clamp level increases until the H _S signal 139 is obtained.
When the H _S signal 139 is obtained, HSD="1" and a synchronization detection state is entered. When HSD="1", the A signal 268 is guided to the output 270 of the data selector 269 constituting the switching circuit 283, and the mode becomes pedestal clamp mode. DVS signal 11 is subtracter 2
At 50, (PDL) 251 "00101111" is subtracted. Sine (sgn) of the output of the subtractor 250
The bit is the DVCS signal 286, which will be described later.
guided by the control circuit. Also, the sgn of the subtractor 250
The 8-bit output containing the bits is led to latch 263 and the first output from counter 238 in FIG.
It is sampled at the Q ₃₁ output 230, which is the 1/2φ _S period shown in FIG. Adder 265 and latch 266 constitute a digital integration circuit 282. The number of integrations is determined by the φ input 163 of latch 266. In order to perform the integration of the color burst period as shown in Fig. 12,
The number of times of this integration is 12. Of the output 267 of the latch 266, a 10-bit output 268 with the lower two bits discarded is led to the A input of the data selector 269. Note that the C ₀ input of the adder 265 is derived from the Q ₃₂ output 241 from the counter 238 in FIG. 11 and becomes a wobbling signal, thereby improving the accuracy of clamping. 12 mentioned above
When the integration is completed, the latch 266 is reset at the timing of the L ₂ R signal 164 from the timing generation circuit 160. The subtracter 271 and latch 272 are also integrated into the integration circuit 2.
84 and the input 270 of the subtracter 271
Integration is repeated so that all are “0”,
This stabilizes the pedestal level. In addition,
L ₁₂ φ signal 16 from timing generation circuit 160
9 and the output of gate 278 becomes a signal 279 that clocks latch 272, and its inverted output 2
0-1 is used for the data latch clock of the clamp DAC 21 (omitted in FIG. 1). (PLL Control Circuit) Since an example of the principle configuration of the PLL control circuit 23 is described in US Pat. No. 4,291,33230, the specific circuit configuration and characteristics of the PLL control circuit 23 will be described here. FIG. 14 is a block diagram showing a schematic configuration of the PLL control circuit 23. The error detection circuit 300 receives timing signals L ₇ φ signal 162 and L ₂ R signal 16.
4. Controlled by L ₆ R signal 165, DVS signal 1
1, _k 〓 ^j=1 (P _4j-3 −P _4j-1 ), _k 〓 ^j=1 (P _4j-2 −P _4j ) ...(1) is performed. Note that the sampling point of P _4j is shown on the color burst waveform 5-1 in FIG. 5. In FIG. 5, 5-2 indicates a period (burst period) during which calculation is performed, and in this embodiment, k=6 was used. That is, the integral calculation of the above equation (1) is performed for six burst periods. As shown in Figure 5, if the target sampling phase with respect to the color burst phase is θ, the error signal is E= ₆ 〓 ^j=1 (P _4j-3 −P _4j-1 )− _k 〓 ^{j =1} (P _4j-2 −P _4j )tanθ ……(2). An error calculation circuit 302 performs the error calculation of equation (2), and its calculation output 303 is guided to an error integration circuit 304. The output 24 of the error integrator circuit 304 is routed to the DAC 16, which applies the PLL. From equation (2), the value of θ (actually tanθ
An arbitrary sampling phase can be obtained by varying the value of . Note that the hue is controlled by varying the value of tanθ. That is, upon receiving the control signal 49, the hue control data generation circuit 305 generates tanθ according to predetermined control data.
A signal 306 indicating the selected value is output to the error calculation circuit 302. On the other hand, the integral operation result of the above equation (1), that is, the sgn bit of the output 301 of the error detection circuit 300 is led to the reference sampling phase detection gate circuit 314,
Here, a reference phase pulse 315 is generated that provides a reference sampling phase. This reference phase pulse 315 is guided to a reference pulse generation circuit 316 that continuously generates reference pulses, and the reference phase, that is, the φ _C signal 26 indicating the I axis in the case of NTSC and the U axis in the case of PAL, is the reference pulse. obtained as. For PAL, U is used as the reference phase.
Along with obtaining the axis, you need a PAL identity signal. The DVCS signal 286 consisting of 1 bit is guided to the burst detection integration circuit 308, where it is sampled by the φ _C signal 26 during six color burst cycles, and the sampling result is integrated.
The integration result 309 is a time constant circuit (equal to an integration circuit) 3 to obtain stability of the PAL identity signal.
Guided by 10. Output 3 of this time constant circuit 310
11, PID signal 25 and timing signal.
Based on the L ₁₂ φ signal 169, a PAL ident determination gate circuit 312 determines whether or not the PAL ident satisfies a predetermined relationship. If the predetermined relationship does not exist, a reset signal 313 is output.
The PAL ident generation circuit 307 uses the _HFB signal 18
It is a one-stage counter with input as input, and a PID signal is obtained as its count output. A reset signal 313 is input to the reset terminal of this counter.
The reference sampling phase is at a phase of ±45° with respect to the U axis, that is, the burst phase according to the PID signal 25 in PAL. FIG. 15 shows a more specific circuit configuration of the PLL control circuit 23. DVS signal 11 is latch 320
guided by. The reset signal for latch 320 is L ₆ R
signal 165. The output 321 of latch 320 is directed to subtractor 322. Output 3 of subtractor 322
23 is led to latch 324, and the output 325 of latch 324 is led to latch 327. Latch 32
The output 328 of 7 consists of 12 bits and the subtracter 32
This is one input of 2. MSB of this output 328
The output 330 for 8 bits from the side is the error calculation circuit 3.
Guided to 02. 12-bit output 3 of latch 320
25 is also led to the error calculation circuit 302. The L ₂ R signal 164 and the L ₇ φ signal 162 are signals that control the error calculation circuit 302, and in the integral calculation result shown in equation (1), the output 325 of the latch 324 is _k 〓 ^j=1 〓 (P _4j − The value of P _4j-2 ) controls the latches 324 and 327 so that the value of _k 〓 ^j=1 〓 (P _4j-1 −P _4j-3 ) comes to the output of the latch 327, respectively. Sign bits 326 and 329 of the integration result data are led to a reference sampling phase detection gate circuit 314. Now, if θ = 33° in NTSC, Q axis (Q-axis)
can be detected, and if θ=±45° in PAL, PID
The U-axis can be detected by controlling the signal. In FIG. 15, AND gate 338 is a Q-axis detection gate, and AND gates 339 and 340 are U-axis detection gates.
This is a gate for axis detection. Each gate 338-340
The output of is guided to OR gate 341. The output 315 of the OR gate 341 is the reference pulse generation circuit 31
6. The shift register 354 is for reference axis detection, and its _Q1 output 355 is sent to the counter 35.
Reset 6. _Q62 output 3 of counter 356
57 is input to the shift register 358, and is synchronized with _{the S} clock.
It is obtained as the φ _C signal 26 from the _Q1 output. This φ _C
The rising timing of the signal 26 indicates the Q _- axis. Figure 16 shows L ₇ φ signal 162, L ₆ R signal 165, SR9R signal 167, and shift register 35.
4 input 315 and its Q ₁ output 355, Q ₆₁ ,
Q ₆₂ output 357 of counter 356, φ _S and the first
Each waveform of the Q output of the flip-flop RSS1 in Fig. 1 is shown. Hue control was in 2-bit steps.
Control data 49 is data decoder 333
and encoded by the encoder ROM 335. In the case of NTSC, the value of θ when control data 49 is “00” is set to 33° (center value),
When “01”, θ=27°, when “10”, θ=37°, “11”
If we choose θ=41° when
Similarly, tan27°="010000",
Encoded as tan37°="011000" and tan41°="011100". In the case of PAL, the encoded value is controlled by the PID signal 25. When using PAL, control data “00” is θ=±45°, and encoded output is sgn
Approximate with 7 bits including
“0111111” is obtained as encoded output, PID=
When it is “0” (hereinafter simply referred to as “0”), “1000000” is obtained. When the control data is “01”, θ=PID gives “0110000” and “1000000” is obtained. When the control data is “10”, the PID is “0111111”,
Get “1110000” with PID. When the control data is “11”, the PID is “011111” and it is “1100000”.
get. In this way, regarding hue control,
A predetermined encoded output (output of encoder 335) 336 is obtained according to the NTSC signal and PID signal 25. The output 336 of the encoder 335 is tanθ
is guided to the error calculation circuit 302. The error calculation circuit 302 outputs the output 32 of the latch 324.
5 and the output 336 of the encoder 335, and the output 337 of this multiplier 332.
and the output 330 of the latch 327. Timing signal (φ _n 〓) 16
8 gives the multiplication timing of the multiplier 332.
The output 343 of the adder 331 is sent to the error integration circuit 304.
It is input to an adder 344 at. Adder 34
The other input of 4 is the output 352 of latch 351. Output 346 of adder 344 is coupled to latch 351. The L ₁₂ φ signal provides latch timing for latch 351 and AND gate 348,
347 and is used for overflow and underflow detection timing. The adder 344, latch 351, and AND gates 347 and 348 constitute an error integration circuit 304. The latch 351 has a 13-bit configuration,
The 9-bit output 24 from the MSB side is the PLL shown in Figure 1.
DAC16. As mentioned above, the gate 348 is an overflow detection gate, and when the output 349 is "1", the latch 3
51 and its outputs are all "1". Gate 347 is an underflow detection gate, which resets latch 351 when output 350 is "1", making its output all "0". In addition,
Output 353 of adder 344 shows the overflow output. In FIG. 15, the DVCS signal 286 is led to the adder 361, and the output 3 of the adder 361 is
62 is led to latch 363. AND gate 3
59 outputs a U-axis detection phase signal 360 during PAL and supplies it to latch 363 as a clock. These gates 359, adders 361, and latches 363
A burst detection integration circuit 308 is configured. The sgn output 365 of this integrating circuit 308 is the time constant circuit 3
10 and further integrated. The time constant circuit 310 includes an adder 366 and latches 371 and 37 that latch the sgn output 368 of this adder 366 and the other 5-bit output 367.
It is mainly composed of 2. In addition, AND gate 373, NOR gate 374
are for overflow and underflow detection, respectively, and the detection timing signal is the φ _n 〓 signal 168. Output 377 of latch 371 is directed to PAL identity determination gate circuit 379. Now PAL
₇₁ output 3 of counter 380 for ident generation
81 is "1" and the output 377 of the latch 371 is "1", the counter 380 is reset by the reset signal 313 at the timing of the _L12φ signal 169, and the U-axis detection and PAL identification are brought to predetermined conditions. Return. and counter 380 Q ₇₁
A PID signal 25 is obtained at the output. (Horizontal Countdown Circuit) A detailed block diagram of the horizontal countdown circuit 32 in FIG. 1 is shown in FIG. 17. The horizontal countdown circuit 32 consists of four large blocks 46.
It consists of 1,462,463,464. The output L ₄ out signal 149 and timing signal 147 of the periodic memory circuit 144 in FIG.
52, a second horizontal period memory circuit 461 stores the period of the incoming horizontal synchronization signal.
In addition, the horizontal period data 424 stored in this way
is input, detects the relationship between the incoming horizontal frequency _H and φ _S , and generates the HMOD signal 4 indicating the horizontal standard mode.
00 is determined by the horizontal standard mode detection circuit 46.
It is 4. The HMOD signal 400 is guided to the Y-C separation circuit 38 as shown in FIG.
When HMOD="1", as is well known, the Y-C separation circuit 38 uses line correlation to separate both Y and C signals (this is well known as a comb filter). On the other hand, when HMOD="0", if Y and C separation is performed using line correlation, the separation may become very poor in some cases (the sample points on the 1H delay line are far apart from each other on the screen). case), Y, C
Separation is done using well-known horizontal sample points.
Performed by BPF. Like this HMOD signal 400
functions to switch the operation of the Y-C separation circuit 38. The output 424 of the horizontal period memory circuit 461 is led to a horizontal synchronization regeneration circuit 462, and this regeneration circuit 46
2, a horizontal drive signal ( _HD out) 34 is obtained. The horizontal phase detection circuit 463 is a circuit that compares the phases of the _HFB signal 18 and the incoming H _S signal 139 and, if they do not have a predetermined phase relationship, outputs a signal 458 to the horizontal synchronization regeneration circuit 462 and pulls in the phase. be. Below, each block 461, 462,
463 and 464 will be explained in more detail. (a) Horizontal period memory circuit 461 L ₄ out signal 149 is guided to subtracter 401 . On the other hand, the latch pulse generation circuit 14 in FIG.
The SR ₆ Q ₁ out signal 147 from 6 is led to a horizontal period memory timing generation circuit 408, and this circuit 408 generates various timing signals 409, 41.
0,411 is generated. These timing signals 409, 410, 411 are controlled by the DCK signal 152 from the determination circuit 151 in FIG. The output 402 of the subtracter 401 is input to a difference detection gate circuit 405, and its difference value is detected. This gate circuit 405 sends a control signal 403-1,
407, and if the difference value is zero, a wobbling signal 406 is supplied to the adder 412. The time constant switching circuit 403 operates to control the time constant of the system according to the above-mentioned difference value. The output 404 of the time constant switching circuit 403 is output from the adder 41
Guided by 2. The other input of adder 412 is
It is 16 bits consisting of 11 bits on the MSB side,
An output 424 of the horizontal period value memory circuit 421;
This is a signal 425 consisting of the output 423 of 5 bits on the LSB side among the 16 bits of the horizontal period correction memory circuit 422. Of the 16 bits output from adder 412, 11 bits on the MSB side are led to switching circuit 415. An output 427 of a standard horizontal period generating circuit 426 is led to the other input of the switching circuit 415. If the horizontal period value does not satisfy a predetermined condition (for example, when the power is turned on), the abnormal value detection gate circuit 431 detects that the horizontal period is abnormal, and sends a detection signal 432 to the horizontal period value preset circuit 433. . The horizontal period value preset circuit 423 receives the signal 43
By inputting the HSD signal 280 together with 2, the signal 434 is supplied to the control signal generation gate circuit 417. As a result, the gate circuit 41
7 supplies a preset timing signal 419 to the horizontal synchronization value memory circuit 421, and also supplies a switching signal 420 to the switching circuit 415.
preset to the standard horizontal period value given by 27. FIG. 18 shows a specific circuit configuration of the horizontal periodic memory circuit 461. In FIG. 18, the horizontal period memory timing generation circuit 408 includes a six-stage shift register 484, an AND gate 485,
It consists of an RS flip-flop 491. FIG. 23 shows a time chart of each timing signal. As can be understood from Figure 23, gate 48
5 outputs a self-reset signal 487 when the DCK signal 152 is "1", and the shift register 484
The output after Q ₃ will not be output. That is,
If the detected difference is a value of ±3 or more in φ _S , the periodic memory does not perform any operation and maintains the previous state. The output of the subtracter 401 has an effective bit length of 8 bits, and the 8-bit signal 474 becomes the B input of the data selector 475. on the other hand,
Of the 8-bit signal 474, the LSB side 3-bit signal 473 becomes the A input of the data selector 475. In addition, the signal 472 has 6 bits on the MSB side of the signal 474, and the signal 4 has 2 bits on the LSB side.
71 is led to a difference detection gate circuit 405, and the difference between the two, that is, the magnitude of the output of the subtracter 401 is detected. In the difference detection gate circuit 405, each output of a 6-input AND gate 479 and a 6-input NOR gate 480 is guided to an OR gate 482. The output 478 of the OR gate 482 becomes "1" when the difference is within ±"3", and becomes "0" when the difference is within ±"3". The output 404 of the data selector 475 has an 11-bit configuration. For example, when the output of the subtracter 401 is +“2”, “010” is input to the A input 473, and the output 47 of the OR gate 482
8 becomes "1". At this time, data selector 47
The output 404 of 5 is “00000000010” from the MSB side.
becomes. On the other hand, the output of the subtracter 401 is +“8”
At this time, "00000100" is input to the B input 474, and the output 478 of the OR gate 482 becomes "0". At this time, the output 404 of the data selector 475 becomes "00000100000". That is, when the difference (signal 474) is large, the time constant is made small to speed up the convergence of the system, which will be described later, and when the difference is small, the time constant is made large to ensure the stability of the system. Therefore, the horizontal period memory circuit 461 converges quickly, and when it converges to a certain value, the time constant is increased, so that horizontal period memory values can be obtained with high performance. Output 404 of data selector 475 is directed to adder 412. The other input of the adder 412 is the 11-bit output 4 of the horizontal period value memory circuit 412.
24 and the outputs 514 and 516 of the horizontal period correction memory circuit 422 consisting of 5 bits. Both inputs 40
4,425 is added with the LSB aligned. Wobbling input 406 of adder 412
(Add “1” to the adder LSB) when the difference detection gate circuit 405 detects zero, AND
This is obtained as the output of gate 483. Output 47 of adder 412 consisting of 16 bits
Of the 6 bits, 11 bits 508 on the MSB side are led to the B input of the data selector 509. The following 3 bits 507 are the horizontal period correction memory circuit 4.
The two bits on the LSB side are led to a latch 515. The standard horizontal period value is output to the A input 427 of the data selector 509. In other words, the value “1054” is “10000111110” in NTSC, and “1199” in PAL.
The value is “10010101111”. Output 510 of data selector 509 is routed to latch 512. In FIG. 18, an abnormal value detection gate circuit 431 that detects an abnormality in the horizontal period value is a gate circuit that determines whether the period value is within a predetermined range, and in NTSC, the period value is "1024". ~
6-input AND gate 5 determines whether it is within “1088”
Detected at 17. “1160” for PAL
AND gate 519- determines whether it is within “1224”
1 to detect. If the period value 424 is not a predetermined value, the output 522 of the NOR gate 521 becomes “1” and is guided to the OR gate 503. The other input of OR gate 501 is HSD signal 280. Input 502 of shift register 503 is “1”
Then, the output 505 of the AND gate 504 becomes "1", and this output 505 controls the data selector 509. AND gate 500 outputs 499 as _{the S} clock at this time. this
The output 499 of AND gate 500 and the _Q5 output 490 of shift register 484 are directed to OR gate 497. OR gate 497 output 4
98 serves as a clock input for latches 512, 513, and 515. Output 505 of gate 504 also resets latch 513 and
Latch 515 is reset through gate 495. The signal 477 and the Q output 492 of the flip-flop 491 are connected to an AND gate 494 and an OR gate 49.
5 to reset latch 515. Second
Figure 4 shows a time chart of the horizontal period value preset circuit. (b) Horizontal standard mode detection circuit 464 FIG. 19 shows a detailed circuit diagram of the horizontal standard mode detection circuit 464. In FIG. 19, the horizontal standard mode detection gate circuit 428 detects the value of the output 424 of the horizontal period value memory circuit 421, and outputs "1" to the output 550 when it determines that the mode is the standard mode. FIG. 20 shows a diagram defining standard modes for NTSC and PAL. Now, considering the value of N=4 _SC / _H , for inputs where the value of N is "904" to "916" as shown at 560 in Figure 20,
Set HMOD="1" (indicates standard mode input),
Otherwise, HMOD is set to “0”. Reference numeral 560 indicates the output of the horizontal period value memory circuit 421 as the output value of the latch 512 in FIG. In other words, the output of the latch 512 is “1048”.
~"1060 is the range of HMOD="1". 562 and 563 are similarly shown for PAL. In the case of PAL, when looking at the output of the latch 512, for the input that is "1192" ~ "1208"
HMOD="1". In FIG. 19, gates 540, 541, 5
42 is for detecting NTSC HMOD, and gates 544, 545, and 547 are for detecting NTSC HMOD.
It is for detecting PAL HMOD.
Detection signal 550 is a timing signal
AND gate 551 with SR12Q ₆ signal 493
is input to reset the counter 555 and set the RS flip-flop 558.
Further, the inverted signal of the signal 550 is input to the AND gate 552 together with the signal 493, and becomes an input signal to the counter 555. The reset of the RS flip-flop 558 is performed by each input of the counter 555.
This is done by output 557 of NAND gate 556 which ANDs the outputs. As shown in the figure, the integration circuit 430 needs to integrate 8 consecutive horizontal synchronization inputs for the input where HMOD = "0", and by this integration, the HMOD signal 4
The stability of 00 has been improved. As a result, the stability of Y-C separation is ensured. (c) Horizontal synchronous reproducing circuit 462 In FIG. 17, horizontal synchronous reproducing circuit 462
Basically, the horizontal synchronization counter circuit 445 that reproduces the horizontal synchronization signal is operated according to the horizontal period value _L15 output 424, and the predetermined _HD out signal 3
4. FIG. 21 shows a specific circuit configuration of the horizontal synchronization reproducing circuit 462. The output 424 of the latch 512 in FIG.
-1 is added. The output 460 of the encoder circuit 495 is data for controlling the count number of the horizontal counter and drawing in the horizontal phase.
When the phases of the H _S signal 139 and _{the HFB} signal 18 match, all are "0". The output of adder 570-1 consisting of 11 bits is led to latch 570-2 and is phase-locked to _{the S} signal. The output 436 of latch 570-2 is directed to a match detection circuit 437 consisting of an 11-bit comparator 571. The other input of comparator 571 is the 11 bit output of horizontal counter 572. Comparator 57
The coincidence output 438 of 1 is applied to the preset terminal PT of the counter 572 and at the same time is guided to the shift register 576 in the horizontal drive pulse generation circuit 439. shift register 576
₁ output 577 sets RS flip-flop 578. _Q1 output 4 of shift register 576
41 is a signal indicating that a preset has been applied to the counter 572;
63. The horizontal counter 572 is a counter for _{the HD} out signal 34, and is composed of an 11-stage counter using _φS as a clock input. This counter 57
The preset data No. 2 is a count value of "145" in the case of NTSC, and "65" in PAL, and these are the preset data generation circuit 574.
More given. This preset value is one count ahead of the preset value of the horizontal period detection counter 213 in FIG. 7. Then, the count value of 573 is taken out as the _THC signal 447 through the AND gate 573. RS in horizontal drive pulse generation circuit 439
A reset signal for flip-flop 578 is provided by gates 579, 580, and 581. _HD signal 440 at the output of flip-flop 578
is obtained. _{The HD} signal 440 is a drive pulse controlled in units of φ _S clocks. Figure 25 shows the output 445 of the comparator 571, the _Q1 output 441 of the shift register 576, and _{the HD} signal 4.
40, and counter 5 in NTSC, PAL
It showed a count value of 72. Figure 26 shows a general _HD signal 440, _HFB signal 18, _THC signal 447, and NTSC and PAL signals.
The outline and phase relationship of the count value of the counter 572 in FIG. From the same figure, the 832 count, which is the rising timing of the _THC signal 447, is
It can be seen that it is located approximately in the middle of one period of _{the HFB} signal 18. The 5-bit output of the horizontal period correction memory circuit 422 in FIG. 18 (MSB side 3 bits 514, LSB
side 2 bits 516) are routed to decoder circuit 448. In FIG. 21, decoder circuits 448, 59
0 consists of a 5-bit input, 32-output decoder. When the 5-bit input of the decoder 590 is "00000", the first decode output 587 becomes "1". Also, when it is "00001", the second decode output 588 is "1". When it is "11111", the final decode output 589 becomes "1". The outputs 581, 588, ... 589 of the decoder 590 are the AND gates 583 and 589 in the selection gate circuit 444, respectively.
This is one input of 584...585. _{The HD} signal 440 is a horizontal drive pulse delay circuit 44 with taps consisting of 62 inverter rows.
At the same time as input to gate 2, it is guided to gate 583. The total delay amount of the 62 inverter arrays in the delay circuit 442 is preferably one period of φ _S , and now as φ _S
Assuming NTSC, the total delay amount is 70nsec, and the delay amount per inverter stage is approximately 1nsec.
It will be about. Output lines 582 and 586 are output from the delay circuit 442 for every two inverters, and each output is connected to the selection gate circuit 444.
It is applied to one input of AND gates 583, 584, . . . 585. AND gate 583,5
A total of 32 bits of output from 84,...585 are led to an OR gate 586, and output to the output of the OR gate 586.
_{An HD} out signal 34 is obtained. In this way, the horizontal period correction memory circuit 422
The output of the delayed _HD signal 440 is selected according to the output of _{the HD} out signal 34. As a result, _{the HD} out signal 34 has a resolution more accurate than the _φS clock unit. FIG. 29 is a diagram for explaining this effect in correspondence with a specific pattern on a TV screen. FIG. 29a shows vertical lines that should originally be displayed on the screen. FIG. 2B shows an example of display of vertical lines when _{the HD} out signal 34 is output in units of φ _S without performing the above-mentioned horizontal period correction. When φ _S ≠ N・_H (that is, when the relationship between φ _S and _H is not an integral multiple, as is the case with PAL standard signals, for example), the vertical line that should originally be displayed (broken line in the figure) 29- 4 is indicated by a solid line, and produces a gear having a width of φ _S period as shown by points 29-1, 29-2, and 29-3. φ _S period is
Since it is approximately 56nsec in PAL, this gear can be detected with the naked eye. Unless the gears on the screen are below the level of detection by the naked eye, it is not sufficient for a high-definition television receiver. In this embodiment, in order to bring this gear sufficiently below the detection limit, as described above, the output 51 of the horizontal period correction memory circuit 442 in FIG.
_HD signal 4 in Figure 21 by 4,516
By controlling the delay amount of 40, the resolution of horizontal synchronized reproduction is improved to less than φ _S unit. As a result, as shown in FIG. 29c, the gear component is theoretically reduced to 1/32 of that shown in FIG. 29b, and poses no problem in practice. (d) Horizontal phase detection circuit 463 In FIG.
detects the phase relationship between the incoming horizontal synchronization signal (the actual signal is the H _S signal 139) and _{the HFB} signal 18, controls the horizontal synchronization regeneration circuit 462 according to the detected phase information, and as a result This is a circuit for performing phase pull-in to bring the H _S signal 139 and the _HFB signal 18 into a predetermined phase relationship. In this case, the structure is such that the phase pull-in is performed continuously and the pull-in time is fast. FIG. 22 shows a specific circuit configuration of the horizontal phase detection circuit 463. In Figure 22, _HFB signal 1
8 is a shift register 60 of the _HFB detection circuit 450
0, and its rising edge is detected by the NAND gate 601. When the rising edge of _{the HFB} signal 18 is detected, the _HFB signal 451 is detected.
The RS flip flip 603 in the timing generation counter circuit 463 is set. The output 604 of the flip-flop 603 is input to a preset terminal of a counter 641 having eight stages.
The preset value of the counter 641 is "20" count for NTSC and "0" count for PAL, and the following comparison pulses are used for NTSC and PAL.
It is shared by PAL. Output 605 of counter 641 is guided to comparison pulse generation circuit 454. The comparison pulse generation circuit 454 receives the incoming H _S
Various timing signals (comparison pulses) for the _HFB signal 18 with respect to the signal 139 are generated. There are six types of comparison pulses: TP1, TP2...TP6, and gates 606, 607, 608, 60 as shown in the figure.
9,610,611 and RS flip-flops 618, 619, 620, 621, 622. Output 612 of gate 611 is TP1
and the output 624 of flip-flop 619
is TP2, the output 623 of flip-flop 618
is TP3, the output 626 of flip-flop 620
is TP4, the output 628 of flip-flop 622
is TP5, the output 627 of flip-flop 621
is TP6. FIG. 27 shows the _HFB signal 18 with the phase pulled in, counter preset timing 604
(CTR9PT), H _S signal 139, TP1, TP2,
Each time chart of TP3, TP4, TP5, and TP6 is shown together with the count value of the counter 641.
The counter values “104” to “108” of the _counter (CTR9) 541 in _FIG . You will be drawn into it. As shown in the figure, comparison pulses TP1 and TP2 are pulses located on both sides of the retracted position, and are pulses for detecting a slight shift in horizontal phase.
TP3 and TP4 are comparison pulses as shown in the _HFB signal pulse "1", and are pulses for detecting a deviation of about 60 clocks φ _S from the pull-in position. TP5 and TP6 are _HFB signal 18H _S signal 1 due to TV channel switching, etc.
This is a pulse that detects that the phase of 39 is significantly different from each other, and the _THC signal (Fig. 22
47). In FIG. 22, comparison pulse TP1612,
TP4624, TP2425, TP3623, TP46
26, TP5622, TP6627 are led to the phase comparison circuit 457, and phase comparison with the H _S signal 139,
Detection is performed. TP3623, TP4626,
TP5622 and TP6627 are led to a latch 629 consisting of 4 bits. The clock of latch 629 is coupled to H _S signal 139. For example, when TP3 is "1", the H _S signal 139 is input to the output of the latch 629 (H _S exists in TP3), and the PI-8 signal 594 becomes "1". In this way, the comparison pulse TP3,
When the H _S signal 139 arrives at TP4, TP5, and TP6, the output of the latch 629 becomes "1" in accordance with the comparison pulse input. The output of latch 629 corresponding to each comparison pulse is connected to PI-8 signal 594, PI+
8 signal 593, PI+32 signal 591, and PI+32 signal 592. The suffixes -8, +8, +32, -32 of these signals correspond to the horizontal synchronization counter 5 in Fig. 21 when the corresponding latch output is "1".
The control value of the count value of 72 is shown. For example, the PI+32 signal 591 is the horizontal synchronization counter 57
By delaying the second preset signal by 32 counts, it becomes a signal for phase pull-in. In FIG. 22, the reset terminal of latch 629 is connected to flip-flop 576 of FIG.
SR13Q ₁ signal 441 from
Launch 629 is cleared each time horizontal synchronization counter 572 is preset. Comparison pulses TP1612, TP2624 that are close to the desired phase are used as TP3, TP4,
It is handled separately from the cases of TP5 and TP6. TP1 pulse 612 is input to AND gate 630 along with H _S signal 139, and the output of gate 630 is 2
It is led to a counter 632 with a stage configuration. The logic output of _TP1.HS is led to the reset terminal R ^* of the counter 632. Setting flip-flop 634 through gate 633 and resetting it with _SR13Q1 signal 640 causes PI-2 signal 59
6 is obtained. That is, when the H _S signal 139 is present four times in succession in the TP1 signal 612, the control signal PI-2 is obtained. Similarly for the TP2 signal 624, the PI+2 signal 595 is obtained from the output of the flip-flop 639. In FIG. 21, the output of the phase comparator circuit 457
PI-2 signal 596, PI+2 signal 595, PI-
The 8 signal 594, the PI+8 signal 593, the PI-32 signal 592, and the PI+32 signal 591 are led to the horizontal counter control amount encoder circuit 459. This encoder circuit 459 is, for example, PI as shown in the figure.
When the +32 signal 591 is "1", "0100000" indicating a value of +32 is outputted, and when the PI-32 signal 592 is "1", "1100000" indicating a value of -32 is outputted to the output 460. and encoder 45
The output 460 of 9 is led to an adder 570 within the horizontal counter preset value calculation circuit 435. (Vertical Countdown Circuit) As shown in FIG. 28, the vertical countdown circuit 36 in FIG.
The synchronization establishment determination circuit 36-2 determines whether or not the H _S signal 139 is detected. Regarding the vertical reproduction circuit 36-1, a basic circuit example is described in detail in a known document: Japanese Patent Application No. 159673/1988 entitled "Vertical Synchronization Circuit", so please refer to it. The vertical reproduction circuit 36-1 in the embodiment of the present invention may be constructed by partially modifying the above-mentioned known document. Regarding this changed part, counters 651, 13, and 653 in FIG. 28 correspond to 2, respectively, corresponding to 10 and 12 in FIG.
It is a counter with a stage structure. In this example
The Q86 signal 650 is used as the input clock of the counter 651, and the _Q2 output 652 of the counter 651 is used as the input of the counter 653 _.
get the signal. In addition, the reset input of the counter 651 becomes the SR13Q ₁ signal 441, and the reset input of the counter 651 becomes the SR13Q1 signal 441.
The reset input of No. 3 is the _SR13Q1 signal +Reset1 (see FIG. 4 of the above-mentioned known document). Furthermore, the CSV signal 126 may be used instead of the CS in the above-mentioned known document. _{The VD} out signal 37 in FIG. 28 is the vertical drive signal. _VD out signal 37 is routed to counter 660. The reset input of counter 660 is H _S signal 139. The RS flip-flop 663 stores the judgment state of synchronization establishment, and is set by the _HS signal 662 and reset by the output of the NAND gate 661. That is, _VD out
When one or more H _S signals 139 are output within one signal cycle, it is determined that synchronization has been established, and the Q output of flip-flop 663 becomes "1".
This Q output is synchronized with _{the S} signal by a shift register 665, and is output from the output of the shift register 665.
An HSD signal 280 is obtained. That is, if synchronization is established, HSD="1". In reality, the Q output of flip-flop 663 is as shown in the diagram.
It is ORed as RS18Q+ _VD out·Q141 and is led to a shift register 665 as a signal 664. The signal 664 is a signal for bringing the clamp circuit 19 into the initial state once every two vertical periods of the HSD.

[Brief explanation of drawings]

The figures are for explaining one embodiment of the present invention. Fig. 1 is a block diagram of the main parts of a digital TV receiver, and Fig. 2 is a diagram for explaining the notation method of the circuit shown in the same embodiment. Figures 3 and 4 are ADC dynamic range and video signal waveform diagrams for explaining the operation of the same embodiment, and Figure 5 is a diagram of the ADC dynamic range and video signal waveforms.
A burst waveform diagram to explain the principle of the PLL circuit, Fig. 6 is a block diagram of the synchronization detection/timing generation circuit, Fig. 7 is a specific circuit diagram of the synchronization separation circuit and horizontal synchronization width detection circuit, and Figs. 10 is a time chart showing the operation of FIG. 7, FIG. 11 is a specific circuit diagram of the burst flag/PLL/clamp timing generation circuit, and FIG. 12 is a time chart showing the operation of FIG. Figure 13 is a specific circuit diagram of the digital clamp circuit, and Figure 14 is a specific circuit diagram of the digital clamp circuit.
A block diagram of the PLL control circuit, Fig. 15 is a specific circuit diagram of the PLL control circuit, Fig. 16 is a time chart showing the operation of Fig. 15, Fig. 17 is a block diagram of the horizontal countdown circuit, and Fig. 18 is a horizontal A specific circuit diagram of the periodic memory circuit, FIG. 19 is a specific circuit diagram of the horizontal standard mode detection circuit, and FIG. 20 is a specific circuit diagram of the horizontal standard mode detection circuit.
9 is a diagram for explaining the operation, FIG. 21 is a specific circuit diagram of the horizontal synchronization regeneration circuit, FIG. 22 is a specific circuit diagram of the horizontal phase detection circuit, FIGS.
Figure 4 is a time chart showing the operation in Figure 18, Figures 25 and 26 are time charts showing the operation in Figure 21, Figure 27 is a time chart showing the operation in Figure 22, and Figure 28 is a vertical time chart. A circuit diagram of the countdown circuit, FIG. 29, is a diagram for explaining the operation of FIG. 21. 11 (DVS)...Digital video signal, 27
...Synchronization detection/timing generation circuit, 32...Horizontal countdown circuit, 35,400 (HMOD)
...Standard mode detection signal, 38...Y-C separation circuit, 139 (H _S )...Horizontal synchronization detection signal, 46
1...Horizontal period memory circuit, 464...Horizontal standard mode detection circuit.

Claims (1)

[Claims] 1. In a digital television receiver that performs signal processing after digitizing a video signal, means for detecting a horizontal synchronizing signal obtained from the digital video signal; A horizontal period memory circuit that stores the period, a horizontal standard mode detection circuit that detects whether an incoming video signal is in the standard mode based on the output of this memory circuit, and a detection signal from this mode detection circuit that detects the standard mode. A digital television set comprising: a comb filter that performs Y-C separation when the detection signal from the mode detection circuit detects a non-standard mode; and a bandpass filter that performs Y-C separation when the detection signal from the mode detection circuit detects a non-standard mode. receiver.