JP2915431B2 - Automatic phase adjustment between multiple signals without special insertion reference signal - Google Patents

Description

Description: BACKGROUND OF THE INVENTION (Industrial application field) The present invention relates to a phase adjustment device that performs phase adjustment of a plurality of electric signals, and particularly relates to an HDTV (High Definition).
The present invention relates to a phase adjusting device for adjusting the phase of a parallel component signal of a broadband television such as a television.

(Prior Art) Conventionally, a television broadcast employs a composite signal obtained by interleaving a chrominance signal using a subcarrier for a luminance signal. However, in a closed circuit television requiring high image quality, a general signal is generally used. Performs various processes from the camera to the display without changing the component signals such as the three primary colors of R, G, and B signals having a wide frequency band and three circuits.
CAV (Component Analog Video) method has been adopted. In signal processing in a broadcasting station,
The encoder that creates the above composite signal is the final stage,
The stages up to that point generally have good characteristics and are easy to process.
Systems adopting the CAV method are expanding. In this case, the component signal that does not depend on the RGB system is composed of a luminance signal Y and a color signal, and the color signals include color difference signals (RY) for red and blue, in addition to the I and Q signals.
(BY), and the frequency band of the color signal is RGB.
Less than the frequency band of the signal. (RY), (B
-Y) The signal has advantages that the frequency band is narrower than the I signal and the Q signal, and the processing is simple. In recent years, for the convenience of processing (R-Y) and instead (B-Y), also used (R-Y) and (B-Y) P multiplied by a coefficient smaller than 1 in _B and P _R signals It has come to be. These P _B, there is lacking a horizontal synchronizing signal to P _R signals. In addition, the CAV method includes a method of processing each component signal in parallel and a method of processing each component signal in series, such as a MAC.
There is a method like the following.

In the present invention, each of the component signals has a horizontal synchronization signal, and is intended for a parallel processing method, and this method is hereinafter simply referred to as a “CAV method”.

Now, in such a CAV system, since each component signal is processed by an individual circuit and transmitted through a separate cable, a phase difference mainly occurs due to a difference in transmission cable length. For this reason, in the CAV system, a phase adjustment that matches the phases between the component signals is an essential condition. Conventionally, CAV in the frequency band of standard broadcasting
In the case of the system, various devices as described below are used as the phase adjusting device for performing the above-mentioned phase adjustment. However, in a recently developed wideband television signal such as HDTV, the frequency band is NTSC. 30MHz for 6 ~ 8MHz of signal
Therefore, it is an essential requirement that the characteristics of the phase adjustment device do not deteriorate over the entire region within a wide band.

Most commonly used as a phase adjustment device is a transistor using a transistor 201 as illustrated in FIG. 6A and using a phase circuit having a capacitor 202 and a resistor 203 on the output side, FIG. 6B 6C switches the delay lines 206-1 to 206-8 by the manual switches 204 and 205. In the genlock method of the synchronization signal shown in FIG. 6C, the synchronization signal is output from the output side of the own channel by the high-precision synchronization separator 207. The phase difference between the separated synchronization signal and the reference synchronization signal is detected by a phase difference detection circuit 208 to generate a phase control signal. The phase control signal controls the phase variable circuit 209 of the main line to adjust the phase. 7A, using the differential amplifier 210 illustrated in FIG. 7A, using the operational amplifier 211 illustrated in FIG. 7B, and using the single operational amplifier 212 illustrated in FIG. 7C. Equipped with a pass filter There is such as is.

FIG. 8 shows a conventional example of a phase adjusting device for component signals in digital television (SMPTE Journal, July, 1987).
The timing and amplitude reference signals (Timing and A) for correcting the amplitude, DC offset, and phase are added to the Y, P _R , and P _B component signals.
mplitude Reference Signal is abbreviated and referred to as a T & A reference signal).
H oscillator 214 (H Voltage Controlled Crys) at a rate of once per field by the synchronization signal detected from the Y signal
tal Oscillator) to generate an H signal and a clock, apply the H signal and the clock to the phase controllers 215 and 216, shift the phase by a control signal and output, and use the clock to output the A / D converter 217. , 218 for A / D conversion. As for the control signal, the H output signal is delayed 219
Signal and the reference signal separation circuit in which was fed by a predetermined time tau ₁
A phase difference from the T & A reference signal separated by 220 is detected by a phase comparator 221, and this is integrated by a sample-and-hold circuit 222 to be created. P _R and P _B signals the H
The same processing as the Y signal is performed in the phase controller 216, the delay 223, the reference signal separation circuit 224, the phase comparator 225, and the sample hold circuit 226 by the H and the clock of the output of the oscillator 214 (the predetermined transmission time of H is τ ₂ and τ ₃ ) to perform A / D conversion.

Also, the necessity of phase matching between multiple signals is due to the above CA
It may also occur in cases other than V. For example, in the case of editing or switching when a plurality of TV cameras are output, it is necessary to adjust the phase of the horizontal synchronizing signal between the signals from the cameras and the phase of the color subcarrier at the switching point within an allowable range. is there.

(Problems to be Solved by the Invention) In the phase circuit using the capacitor 202 and the resistor 203 shown in FIG. 6A, since the phase shift amount has a frequency characteristic,
A method of reducing the amount of phase shift per stage and cascading the same circuits to obtain a required amount of phase shift is used. In the NTSC system (frequency band 6 to 8 MHz), a phase amount of 54 ns (70 ゜ at 3.58 MHz) is obtained by cascading eight stages. However, if the number of stages increases, other characteristic degradation also appears. is there. In the case of HDTV, the frequency band becomes about five times, so that it is necessary to further reduce the phase shift amount per stage to increase the number of stages, but this method cannot be adopted for the above-described reason.

In the device for manually switching the delay lines 206-1 to 206-8 shown in FIG. 6B, attenuation due to mismatching occurs in the delay lines due to the influence of the extraction cable and the stray capacity to the switches 204 and 205. The signal characteristics are degraded and the usage limit is 6MHz.

The genlock method of the synchronization signal shown in FIG.
This method satisfies the required accuracy for the phase synchronization of the horizontal synchronization signal of the system, but the detection limit of the delay error between HDTV component signals is 3.5 ns (for the scan line length of 29.63 μs).
For 1.2 × 10 ^-4 ), the accuracy is insufficient and cannot be put to practical use.

Each of the circuits illustrated in FIGS. 7A, 7B, and 7C has a low frequency-phase characteristic of the currently available operational amplifier IC, and has a small number.
Especially in the frequency band of MHz, the frequency phase characteristic exceeds the permissible limit, so that it cannot be put to practical use.

The CAV method is expected to be used more and more in the future.
The AV system lacks a reference signal that is a reference for the timing of each component signal. Therefore, the method of inserting the reference signal shown in FIG. 8 cannot be used for the current CAV or HDTV lacking the reference signal, and digitizing a wideband signal without distortion is only phase adjustment. There is a disadvantage that it is expensive for the purpose of the above.

Therefore, a first object of the present invention is to perform phase adjustment between a plurality of signals of the same type without using a special insertion reference signal, and to adjust the phase over a wide band without deteriorating characteristics. It is to provide a possible phase adjustment device.

Since control of each circuit of the phase adjustment device is often performed by detecting a level change, there is a fear that a malfunction may occur due to pulse noise. A second object of the present invention is to provide a start / stop circuit which fixes a phase adjustment state after completion of phase adjustment so that a malfunction due to a pulsed nozzle does not occur.

(Means and Action for Solving the Problems) According to the first invention of the present application, one of a plurality of signals is used as a main signal and the remaining signals are used as sub-signals, and the input of these main signals and each sub-signal is performed. Delay means for delaying the phase by the electronic switch of the delay line up to the maximum shift phase in units of the minimum modulation phase, means for selecting a sub signal having the most delayed input phase, an output phase of the main signal and the input phase A comparing means for comparing the input phase of the sub-signal with the most delayed phase; and if the output phase of the main signal is ahead of the input phase of the sub-signal with the most delayed phase by the result of the comparison by the comparing means, Means for controlling the electronic switch to adjust the phase of the main signal to the phase of the sub-signal, and if the output phase of the main signal is behind the input phase of the sub-signal having the most phase delay, holding the same as before; Means for adjusting the output phase of each sub-signal to the output phase of the main signal by controlling the electronic switch after the operation of the means is completed.

A start-stop circuit according to a second aspect of the present invention is a means for sending a reset signal and a control signal in response to a start signal to an effect circuit which performs an operation for producing a predetermined effect in response to the reset signal and the control signal. Means for stopping the transmission of the control signal by the control completion signal from the effect circuit and prohibiting the transmission of the control signal until the start signal is added again.

The effect circuit controlled by the start / stop circuit may be a phase adjustment circuit as in an embodiment described later, but any circuit that performs a predetermined operation in response to a reset signal and a control signal may be used. Such a circuit may be used.

With the above configuration, it is possible to adjust the phase of the plurality of sub-signals of the main signal with the accuracy of the minimum phase adjustment unit.

In the case of a television signal such as NTSC or HDTV, the main signal is a luminance signal Y of the television, and the sub signals are I, Q; (RY), (BY); P _R , P _B of color signals. If any of the above, or the main signal is one of the three primary color signals RGB, the sub signal is another signal, and the required phase range and accuracy are selected,
The required modulation characteristics can be obtained.

As described above, since the phase difference between the components is mainly due to the difference in the cable length, once the phase adjustment is completed, there is almost no phase difference. Also, if the phase adjustment circuit is made to respond to even a slight phase change after the completion of the phase adjustment, if the phase noise or the like is generated or mixed in from the outside, the phase adjustment state is not preferable.
For this reason, in the embodiment described below, the phase is fixed after completion of the phase adjustment, and the phase adjustment state is reset only when a cause such as the replacement of the cable and the repair of the related equipment that causes a phase difference occurs, The phase was adjusted again.

(Example) Figure 1 is the inventors of the present application are intended to show the compensator circuit developed in the process leading to the present invention, the wideband Y signal such as HDTV, P _B, the adjustment phase of the P _R signals Is what you do. In this phase adjustment circuit, a phase difference of 50 ns corresponding to a cable length error of 10 m is defined as a maximum phase difference, and a phase difference of less than 50 ns is defined as an HD phase difference.
It is intended to adjust the phase so as to satisfy 3.5 ns which is the detection limit of delay error between TV component signals.

In this case, only the maximum phase difference between the component signals is given, and no signal to be used as a reference is given. Also, it is not known which component signal is leading or lagging. Therefore, for the sake of convenience, one of the plurality of component signals is processed as a main signal, and the remaining signals are processed as sub-signals. In this phase adjusting circuit, when a delay of 50 ns, which is the maximum phase difference, is given to the main signal by the delay line, the phase of the sub signal is utilized by utilizing that all other sub signals are ahead of the delayed main signal. Is adjusted to the phase of the main signal by switching the delay line. Since the main signal is only Dererain of 50ns enters one, Y, P _B, when the main signal frequency band widest Y signal in the case of P _R signals, the advantage of reducing the frequency characteristic deterioration of the Y signal There is. In the case of an RGB signal, a G signal is generally used as a main signal, but another signal may be used as a main signal.

The Y signal input from the input terminal 1 is delayed by 50 ns by the 50 ns delay line 4 and the output terminal 10 outputs a Y 'signal. Amplifiers 2 and 5 are inserted on the input and output sides of the delay line, respectively, to prevent the frequency characteristics from deteriorating.
The frequency characteristics of these amplifiers 2 and 5 can be adjusted by capacitors 3 and 6, respectively. The amplifier 7 is inserted to provide a delay corresponding to the delay in the third amplifier 20 inserted in the sub-signal phase adjusting circuit.

When the main signal Y is delayed by 50 ns on the delay line 4, if the sub-signal is initially 50 ns ahead of the main signal, the phase difference between the main signals becomes 100 ns.
Need to be able to adjust the range. In order to satisfy the detection limit of 3.5 ns, in this embodiment, it is about half that, 2 ns.
It is in phase with the accuracy of. The circuit operation will be explained as an example P _B signal. P _B signal input from the input terminal 11 via the amplifier 12 to improve the frequency characteristic, after 4ns approximately of the coarse phase is twice the first compensator accuracy, the fine-tuning phase of ± 2 ns . A capacitor 13 is connected to the amplifier 12 so that the frequency characteristic can be changed. The coarse tuning phase is a 2-digit quinary delay line 14, 1 in units of 4 ns.
8 to the electronic switch 1 by controlling the quinary counters 37 and 38
5 and 19 are switched to adjust the phase from 0 to 96 ns with an accuracy of 4 ns. The amplifiers 16 and 20 improve the frequency characteristic deterioration due to the delay lines 14 and 18. These amplifiers 16, 18
Will be connected in series with the two delay lines. In this phase adjustment circuit, 0 to 96n in units of 4ns
The range of s is adjusted, but when 2 ns is used as a unit, the range of 0 to 96 ns can be adjusted by using a 2-digit octal number, and the range of 0 to 126 ns can be adjusted by using a 2-digit octal number. Can be adjusted. In this case, if a 3-digit quaternary number is used, 0
Although the phase can be adjusted in the range of up to 106 ns, an increase in the number of digits increases the number of delay lines inserted into the circuit and the number of amplifiers for improving the frequency characteristics accordingly. Since the counter has a configuration that can easily take decimal numbers, it is preferable to reduce the number of digits, and usually two digits are sufficient. Thus, by selecting the number of digits of the delay line and the number within each digit, it is possible to set an arbitrary phase adjustment range and accuracy.

Electronic switches 15, 19 are used to switch between delay lines 14 and 18.
Is used, so that the frequency characteristics are not impaired as in the case where a manual mechanical switch is used. Since an IC for an electronic switch is commercially available that has ten or more switch elements, a circuit can be easily configured by using the IC.

Control signals for the quinary counters 37 and 38 are created as follows. And the Y 'signal given a delay, detects the timing of the horizontal synchronizing signal is supplied to the high-precision sync separator 9 and 22 to be described later to "tone-phase output P _B of 4ns precision, high-speed digital phase comparator of this in addition to 23, Y 'signal P _B "
, A positive pulse is generated when it is late, and a negative pulse is generated when it is advanced. The pulse width is proportional to the phase difference. The advance of Y '(up to 4 ns) occurs when the over-phase is performed.
At this time, the delay line is not controlled. The pulse width of the positive pulse due to the delay of Y 'becomes narrower when the phase difference becomes 4 ns or less immediately before the phase matching, but the pulse width is expanded so that adjacent pulses overlap and continue to make the logic circuit a high level. .

An example of the pulse processing circuit 25 having this function is shown in FIG. The input signal supplied to the input terminal 151 is applied to, for example, a monostable multivibrator 154 having a large time constant so that adjacent pulses overlap. In this example, since the pulse of 4 ns or less does not need to be phase-modulated, the input signal is directly applied to the AND gate 153 and the signal is applied through the 4 ns delay line 152 so that the pulse disappears. You don't have to.

The output given to the output terminal 156 of the pulse processing circuit 25 is input to the input terminal 29-2 of the start / stop circuit 28 as shown in FIG. This start / stop circuit 28 is connected to this external terminal
A starting circuit 30 connected to the ground by a non-locking key is connected to 29-1. When the starting circuit 30 is grounded, a reset signal is transmitted from an output terminal 29-4 to reset the quinary counters 37 and 38 to the initial state, The terminal 29-5 is set to high level to turn on the AND gate 31, and the clock pulse from the clock pulse generator 32 is applied to the quinary counter. As a result, the quinary counter operates, and the electronic switches 15 and 19 are controlled to switch the delay lines 14 and 18 one after another, thereby performing phase adjustment.
When the phase adjustment is completed and the output of the pulse processing circuit 25 goes low, the terminal 29-5 goes low and the transmission of the clock pulse stops, and the switching of the delay line also stops. After that, the terminal 29-
Even if 2 goes high or low, terminal 29-5 remains low. That is, the phase adjustment circuit is fixed at the phase adjustment completed state. At this time, the terminal 29-1 is again activated by the starting circuit 30.
Is grounded, phase adjustment can be performed in the same manner as described above.

FIG. 5 shows an embodiment of the start / stop circuit 28 having such a function. This circuit also incorporates a circuit for P _R to be described later. The input side of the NAND gate 163 is kept at a high level when the terminal 29-1 is not grounded by the non-lock key 31, but when it is grounded, it becomes a low level and a negative voltage is applied. Therefore, a positive voltage is applied to terminal 29-
4, the effect circuit is reset, and a negative voltage is applied to the set terminal S (or the reset terminal R) of the flip-flop 162 by the inverter 164.
As a result, the Q terminal (or Q terminal) becomes high level,
The phase is output from the terminal 29-5 and phase adjustment is performed. When the phase adjustment is completed and the terminal 29-2 becomes low level, the capacitor 161
Is charged, the reset terminal R (or set terminal S) becomes low level by the differential pulse, and the Q terminal (or Q terminal
) Is inverted to a low level, and the terminal 29-5 also becomes a low level. At this time, even if the terminal 29-2 goes high or low again for some reason, the potential of the flip-flop does not change, so that the terminal 29-5 remains low. The capacitor 165 and the flip-flop 166 are circuits for the _PR signal.

As shown in FIG. 5, the start / stop circuit 28 includes a means for sending a reset signal and a control signal to an effect circuit (phase adjusting circuit) by a start signal, and a control signal by a control completion signal from a signal control circuit. It has means for stopping the transmission and inhibiting the transmission of the control signal until the start signal is added again. Such a function can be obtained by another configuration without being limited to the above embodiment. For example, if the power supply of the above-described circuit is negative, the NAND gate 163 is an AND gate, the flip-flop 162 is a positive operation, and the inverter 164 is an amplifier, it is obvious that a similar operation can be obtained. The signal control circuit also includes a main circuit (delay lines 4, 14, 18, and electronic switches 15, 19 for performing direct phase adjustment), a detection circuit (high-precision synchronization separation circuits 9, 22, for detecting the state of phase adjustment, a phase comparator 23, Inverter 24, pulse processing circuit 25, 2
6, an LED or alarm circuit 27) and a signal control circuit including a control circuit (AND gate 31, clock generator 32, quinary counters 37 and 38).

Due to the above phase adjustment, the output P _B ″ of the amplifier 20 is 0 to 4 ns.
Is adjusted to the range. By passing this through a 2 ns delay line 35, its output P _B ″ is delayed in the range of 0 ± 2 ns, as shown in the waveform diagram in FIG.
While the coarse adjustment phase of 4 ns accuracy was obtained by the delay lines 14 and 18, passing through the delay line 35 was ±± with respect to Y ′.
It can be said that this is a fine tuning phase in which the accuracy is improved to 2 ns. As described above, the delay phases of the delay lines 14 and 18 are 2 ns.
It can also be achieved by setting the unit to two digits of octal or two digits of octal. It is easy to further improve the phase adjustment accuracy by a similar technique. On the other hand, the output of the phase comparator 23 is passed through the active filter 33 to be a DC value proportional to the phase difference, and this is added to the AVDL 34, so that fine phase adjustment can be performed in an analog manner. The characteristic of analog modulation is that a continuous modulation value can be obtained, but even with digital modulation, if the unit of the modulation is sufficiently small, a modulation value that does not cause discontinuity can be obtained. Can be. Of these methods, the above-described method is the simplest method since only a 2 ns delay line is inserted.

Another component signal input from terminal 39
P _R also, by passing the similar compensator circuit 40, Y '
A P _R 'signal phase-adjusted with an accuracy of ± 2 ns is output from a terminal 41.

If the phase difference exceeds the phase adjustment capability due to cable replacement or other causes, or if there is a fault in the phase adjustment circuit, the phase difference remains. In order to detect this state, an LED or an alarm circuit 27 is inserted on the output side of the pulse processing circuit 25 so that the LED is turned on when there is a phase difference or an alarm voltage can be sent to the outside. When Y 'is ahead of P _B or P _R signals, the output of the phase comparator 23 becomes negative, and positive by the inverter 24, and a high level by the pulse processing circuit 26 of the pulse processing circuit 25 and the same configuration, This is added to the LED or alarm circuit 27. When the LED or the alarm circuit 27 is operating properly within a predetermined range of the phase difference, the phase adjustment time is short, so that the LED or the alarm circuit 27 is only turned on for a moment or sends an alarm voltage to the outside. In the case of exceeding the threshold or in case of a fault, the lamp remains lit or the alarm voltage is sent to the outside, so that the occurrence of the fault can be known.

The high-precision sync separators 9 and 22 detect the timing of the horizontal synchronizing signal with high precision. In the case of a binary horizontal synchronizing signal such as a standard broadcast, the timing is the leading edge of the median value of the amplitude of the negative pulse. In the case of a ternary signal such as a high-definition television, the point is at the pedestal level at the center of the ternary signal, and any known circuit can be used.
An embodiment of a detection method for a ternary signal will be described with reference to FIG. The input signal supplied to the input terminal 131 is
After being amplified by 32, the minimum value is clamped to zero potential by capacitor 137 and diode 138 and applied to the positive terminal of comparator 139. This comparator 1
By applying + 0.15V, the median value of the lower pulse, to the negative terminal of 39, the timing of the H leading edge can be found. In this method, the operation of the simple sync separators 72 and 102 in FIG. This pulse is applied to the delay line or monostable multivibrator 140
And a pedestal level is detected by the clamp pulse generated by the clamp pulse generator 142. This output is connected to a transistor 13 whose emitter is grounded.
By adding to the base of 4, the lowest potential of the input signal is clamped to the pedestal level. Set the negative terminal to 0
When the potential is applied to the positive terminal of the converter 135, the output becomes a positive portion (a ternary signal and a video signal) above the petestal level. AND this output
Add to 136. On the other hand, a delay of DL2 is provided from the leading edge of the H by a delay line or a monostable multivibrator 141, and a gate pulse including a central portion of a ternary signal generated by a gate pulse generator 143 is added to the AND gate 136. The rising timing of the ternary signal at the required pedestal level, that is, the synchronization signal separated with high precision can be extracted from the output terminal 144.

FIG. 2 shows an embodiment of the automatic phase adjusting apparatus according to the present invention. In the present invention, unlike the method of giving a delay of the maximum phase difference to the main signal in advance, the coarse adjustment phase compares the output of the main signal with the input of the slowest sub signal as a first operation, and When the main signal is advanced, a delay is given to the position of the sub-signal, and when the main signal is delayed, the phase is maintained as it is. As a second operation, the phase control circuit shown in FIG. The phase of each sub-signal is adjusted with respect to the phase of the main signal in the same manner as described above. The method of fine phase adjustment is the same as that of the phase adjustment circuit shown in FIG. In the above-mentioned first operation, first, the slowest sub signal must be selected. However, the same result can be obtained by comparing the main signal and each sub signal separately and performing the same operation. Since this method directly adjusts the phase of the main signal and the sub-signal, there is a characteristic that the phase adjustment range is limited to the range of the maximum phase difference. Therefore,
Although the delay amount of the delay line, that is, the required number thereof, can be reduced, the main signal also requires a phase adjusting device. Therefore, it is inevitable that the characteristics of the main signal are slightly inferior to those of the phase adjustment circuit shown in FIG.

FIG. 2 shows that the maximum phase difference between the main signal and the sub signal is 50n.
5 shows an embodiment of the present invention in which the phase is adjusted with an accuracy of 4 ns and the fine adjustment phase with an accuracy of ± 2 ns. As a second operation, the Y 'signal in Soshi regulating the P _B and P _R signals with a precision of 4 ns, P _B ", P _R" is obtain, similar circuit operation and compensator circuit shown in Figure 1 It is. The fine tuning phase is also 2 ns by the delay lines 83 and 113 to P _B ″ and P _R ″ similarly to the phase adjusting circuit shown in FIG.
And adjust the phase to an accuracy of ± 2 ns.

The above-described series of circuit operations are performed by the start / stop circuit 67. In addition to the function of the start / stop circuit 28 of the phase adjustment circuit shown in FIG.
It includes a sequence circuit for sequentially adjusting the phase of the sub signal and the main signal and the phase of the main signal and each sub signal.

As shown in FIG. 2, the Y signal supplied to the input terminal 42 is supplied to a delay line 45 through an amplifier 43 connected with a capacitor 44 in order to improve the frequency characteristic, and this delay line is supplied to an electronic device controlled by a counter 55. Switch 46
, And is supplied to a delay line 49 through a second amplifier 47 whose frequency characteristic is adjusted by a capacitor 48, and is then delayed for a predetermined time by an electronic switch 50 controlled by a quaternary counter 56. To the third amplifier 51. This third amplifier 51 also has a capacitor 52
To improve the frequency characteristics. In order to detect the output phase of the Y signal, the output signal Y 'of the amplifier 51 is supplied to the high-precision synchronization separator 54 to extract the simple separation synchronization signal and the high-precision separation synchronization signal. And input to the input terminals of the phase comparators 86 and 116.

Simple synchronizing separating circuit from P _B signal supplied to the input terminal 71
The synchronizing signal separated by simple synchronizing separator circuit 102 from the P _R signals supplied to the synchronizing signal and the input terminal 101 separated by 72 is supplied to the phase comparator 62 detects a phase relationship between these signals. In other words, it generates a negative signal when a positive signal, which is delayed when is progressing P _B signal. The signal respectively supplied positive and negative input terminals to the negative and positive input terminals of the differential amplifier 65 and 66 connected to the reference potential, the polarity same time also delayed when progressed P _B signal Signal. The signal thus obtained is supplied to the other input terminal of the phase comparator 59. The phase comparator 59 has a positive polarity when the Y 'signal is advanced, has a negative polarity when the Y' signal is delayed, and outputs a signal whose width is proportional to the phase difference. This signal passes through an amplifier 60 to remove a negative component, and is supplied to a start / stop circuit 63 via a pulse processing circuit 61. First
Similarly to the phase adjustment circuit shown in the figure, an AND gate 57 and a clock pulse generator 58 are provided to control the counters 55 and 56 so that a desired delay time can be obtained.

The P _B signal input terminal 71, first and a capacitor 74 1
To a delay line 75 via a second amplifier 77 whose frequency characteristic is adjusted by a capacitor 78 after being delayed for a desired time by switching of an electronic switch 76 controlled by a quaternary counter 91. Electronic switch 80 supplied and controlled by a quaternary counter 90
, And is supplied to the third amplifier 81 after a predetermined time delay.
A capacitor 82 is also connected to the third amplifier 81 so that the frequency characteristics can be improved. The delayed signal P _B ″ obtained from the third amplifier 81 is supplied to an output terminal 84 via a delay line 83 of 2 ns. The synchronization signal is separated from P _B ″ by a high-precision synchronization separation circuit 85, and the other end of the phase comparator 86. Supply terminal. The output signal of the phase comparator 86 is supplied to the start / stop circuit 63 via the pulse processing circuit 87. A clock pulse generator 88 and an AND gate 89 are provided.An output of the clock pulse generator 88 is applied to one terminal of the AND gate 89, and a control signal of a start / stop circuit 87 is applied to the other terminal. The control to obtain the desired delay time is the same as described above for the Y signal. Thus, the output terminal
P _B signal delayed a predetermined time to 84 will be obtained.

Since also treated in the same way as P _B signal for P _R signals supplied to the input terminal 101, respectively capacitors 104, 108,
Amplifiers 103, 107, 111 with 112, delay lines 105, 10
9.Electronic switches 106 and 110, 2ns delay line 113, high-precision sync separation circuit 115, phase comparator 116, pulse processing circuit 117, clock pulse generator 118, and gate 11
Configuration, such as 9,4-ary counter 120, 121 is also similar to the configuration for the P _B signal, a detailed description thereof will be omitted. In this manner, so that the P _R signal delayed a predetermined time to the output terminal 114 is obtained.

As described above, the phase is aligned Y within the allowable range to an output terminal 53,84,114 'signal, P _B', it can be obtained P _R 'signal.

In the first and second embodiments, the phase adjustment within one channel has been described. However, it is easy to extend the phase adjustment to a plurality of channels. In this case, the phase of the component signal of each channel may be adjusted in accordance with the method shown in FIG. 2 with reference to the output phase signal of the Y signal of the standard channel or an arbitrary synchronization signal in the station. .

The embodiment of the present invention described above is a method of maintaining the phase after completion of the phase adjustment. However, when there is a possibility that a change such as a failure such as a large change in the frequency characteristic may occur, each scan line may be changed. The change can be dealt with by adjusting the phase. To do this, you need to use counters 37, 38, 55, 56,
The 90/91/120/121 may be of the up / down type, and the positive / negative pulses obtained by the phase comparators 23/59/86/116 may be separately extracted so that the up / down counter is constantly controlled. The connection is shown by a dotted line in FIG.

Although the embodiment described above is directed to the case of a wideband CAV such as an HDTV, the same can be applied to a standard broadcast CAV, a closed circuit CAV, and a VTR. Further, it is apparent that the sub-signals may be I and Q signals; (RY) and (BY) signals.

In the case of the CAV of the standard broadcast, it is sufficient to set the phase adjustment unit to 5 ns, so that fine adjustment is unnecessary.

Since the principle of the phase adjustment can be applied not only to television component signals but also to a plurality of signals, it can be applied to automatic detection of a phase difference between a plurality of signals irrespective of signals of the same type or different types. For example, when mixing, switching, and editing composite signals from a plurality of television cameras, it is necessary to match the phases of H and color subcarriers at the switching point, but this can be used for phase adjustment. . However, at this time, the signal of each camera first detects the V phase, matches the color sequence and the V phase, and then
A phase adjustment according to the invention has to be performed.

In a phase adjusting device having a low frequency band, for example, an H-phase shifting phase adjusting device, the delay means is not limited to the delay line, and it goes without saying that other delay means may be used.

(Effects of the Invention) According to the present invention, even in the case of a component signal without a reference signal, the phase between the component signals can be automatically adjusted. Since the tuning range and the tuning unit can be set arbitrarily, even if the cable length difference between each component is 10 m or more, HDTV that requires 3.5 ns tuning accuracy and higher tuning are required. Even when the phase accuracy is required, it can sufficiently cope with the situation, and the advantage is very large.

In addition, the component signals of a plurality of channels can be matched with reference to an arbitrary synchronization signal in the station or an output synchronization signal of a Y signal of a specific channel, thereby facilitating operations such as switching and mixing of each channel. There are advantages.

Furthermore, since the phase modulation in the present invention is to switch the delay line by an electronic switch, a transistor or
There is an advantage that the distortion entering the main line, particularly the distortion of the frequency characteristic and the rising characteristic of the rectangular wave, is smaller than that of the modulatable phase circuit using the IC. In addition, since the delay lines are configured to form two digits, at most three digits, of three to decimal numbers, only two or at most three delay lines are required to enter the signal main line. Accordingly, the number of frequency characteristic improving amplifiers inserted before and after the number of the amplifiers is minimized, the adjustment is easy, and the characteristic deterioration of the main line is small.

The Y signal and the main signal, in the case of a P _B, sub-signals P _R signals, etc., provides a delay of maximum phase difference Y signal, in the P _B, method Sosuru regulating the P _R signals thereto, most Since there is only one fixed delay line in the Y signal with a wide frequency range,
There is an advantage that characteristic deterioration is minimized.

Further, according to the present invention, after the completion of the phase adjustment, the phase can be fixed in this state, so that troubles due to pulse noise can be avoided and the circuit can be stably maintained.

The present invention provides broadband CAV broadcast, closed circuit television, V
It is most effective when used for phase changers in TRs, but because the operation is completely automatic, the standard CAV
Is also effective, and it can also be used as a phase adjustment device for the H phase of a plurality of composite television signals or the phase of color subcarriers. Further, it can be used as a phase adjusting device of various timings between different types of signals in various automatic devices and the like.

In addition, the present invention can be widely applied to a case where it is necessary to activate a circuit for giving some effect to a signal, such as giving a special effect, and to hold the control state after the control is completed.

[Brief description of the drawings]

FIG. 1 is a block diagram and a waveform diagram of a phase adjusting device developed by the present inventors in the process leading to the present invention, and FIG. 2 is a block diagram and a waveform diagram of an embodiment of the phase adjusting device according to the present invention. FIG. 3 is a block diagram and a waveform diagram of a high-precision sync separator for a ternary sync signal, FIG. 4 is a connection diagram of a pulse processing circuit, FIG. 5 is a connection diagram of a start / stop circuit, FIG. Is a known phase shift circuit using a transistor and having C and R on the output side, FIG. 6B is a known phase shift circuit that switches the delay line by a manual switch, FIG. 6C is a genlock type phase shift circuit of a synchronization signal, FIG. 7A is a known phase shift circuit using a differential amplifier, FIG. 7B is a known phase shift circuit using an operational amplifier, FIG. 7C is a known second-order all-pass filter using a single operational amplifier FIG. 8 shows a digital television set. Shows an example of a conventional compensator device component signal. 1 ...... Y signal input terminal, 4 ...... 50 ns Dererain 9 ...... Precision sync separator, 10 ...... Y 'signal output terminal 11 ...... P _B signal input terminal 14, 18 ...... 4 ns units 0～96Ns 5 2 digit hexadecimal delay line 15,18 ... Electronic switch, 22 ... High precision sync separator 23 ... High speed phase comparator, 24 ... Inverter 25,26 ... Pulse processing circuit, 28 ... Start / stop circuit 30 ... Non lock key, 31 ...... aND gate 32 ...... clock pulse generator, 35 ...... 2 ns Dererain 36 ...... Ps' signal output terminal, 37, 38 ...... quinary counter 39 ...... P _R signal input terminal, 40 ...... P _R signal phase adjustment circuit 41 ... P _R 'signal output terminal, 42 ... Y signal input terminal 45,49 ... 0 to 60ns 4ns unit quaternary 2-digit delay line 46,50 ... Electronic switch, 53 ... Y 'signal output terminal 54 High-precision synchronous separator, 55, 56 Quaternary counter 57 AND gate 58 Clock pulse generation Vessel 59 ...... fast phase comparator, 61 ...... pulse processing circuit 62 ...... fast phase comparator, 63-66 ...... minus level polarity inverter 67 ...... start-stop circuit, 68 ...... non-locking key 71 ...... P _B signal Input terminal, 72: Simple sync separator 75, 90: 4 ns, 4-digit 2-digit delay line from 0 to 60 ns 76, 80: Electronic switch, 83: 2 ns delay line

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Zenichiro Misawa 2-2-1 Jinnan, Shibuya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Center (56) References JP-A-2-13087 (JP, A) JP-A-Hei 2-232867 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 7/18 H04N 9/44 H03L 7/00

Claims (6)

(57) [Claims] 1. One of a plurality of signals is defined as a main signal, and the remaining signals are defined as sub-signals. The input phase of the main signal and each sub-signal is minimized to a maximum deviation phase by switching by an electronic switch of a delay line. Delay means for delaying the phase in units of phase, means for selecting a sub signal having the most delayed input phase, and comparing means for comparing the output phase of the main signal with the input phase of the sub signal having the most delayed input phase When the output phase of the main signal is ahead of the input phase of the sub-signal having the most delayed phase as a result of the comparison by the comparing means, the electronic switch is controlled to change the phase of the main signal to the phase of the sub-signal. Means for holding the main signal when the output phase of the main signal is behind the input phase of the sub-signal having the most phase delay, and controlling the electronic switch after the operation of the means to terminate the main signal. Automatic phase compensator device among multiple signals that do not depend on a special insertion reference signal, characterized in that it comprises a means for matching the output phase of each sub-signal to the force phase. Wherein the luminance signal of the main signal television, automatic phase adjustment phase device among multiple signals that do not depend on a special insertion reference signal according to claim 1, wherein the sub-signal was P _R signals and P _B signal. 3. The method of claim 1, wherein the main signal is any one of a red signal, a green signal and a blue signal of the television, and the sub signal is another color signal. Automatic phase adjuster. 4. The method according to claim 1, wherein the main signal is a horizontal synchronizing signal or a color subcarrier of any one of the plurality of composite television signals, and the sub signal is a horizontal synchronizing signal or a color subcarrier of another composite television signal. Item 1. An automatic phase adjusting apparatus for a plurality of signals which does not depend on a special insertion reference signal according to Item 1. 5. A means for transmitting a reset signal and a control signal in response to a start signal to an effect circuit for performing an operation for producing a predetermined effect in response to the reset signal and the control signal;
A start / stop circuit having means for stopping transmission of the control signal by a control completion signal from the effect circuit and prohibiting transmission of the control signal until a start signal is added again. 6. A start control voltage is applied to a set or reset terminal of a flip-flop in response to a start signal, a control completion voltage from an effect circuit is applied to a reset or set terminal, and a normal output terminal or an inverted output terminal of the flip-flop is applied. 6. The start / stop circuit according to claim 5, wherein a control voltage of the effect circuit is taken out.