1274474 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種彩色電視系統，且特別是有關於 一種色副載波之產生裝置與方法。 【先前技術】 近年來，不同電視系統的接收器隨著電視機的普及被 廣泛地使用，而且具有越來越好的性能表現。舉例來說， 如被廣泛應用於NTSC以及PAL系統中的數位顏色再產生 電路（digital color signal reproducing circuit)等。第 1 圖係 繪示一種習知數位鎖相迴路之示意圖，可應用於 NTSC/PAL/SECAM電視系統中。此數位鎖相迴路1〇〇的功 用係根據所輸入的繫色（color burst)訊號產生副載波 (sub_carrier)訊號，以供之後的顏色解調器使用。 如第1圖所示’頻率相位偵測器（phase detector; PD)102 係用以比較繫色訊號以及副載波訊號的相位，並據此產生 一相位差訊號。此相位差訊號接著被一迴路濾波器（l〇op filter) 104濾波，而後已濾波之相位差訊號再被輸入至一數 位控制振盡器（digital control oscillator ; DCO)106。 數位控制振盪器106根據此已濾波之相位差訊號產生 副載波訊號，並將所產生之副載波訊號再回授至頻率相位 偵測器102。藉由上述回授過程，此數位鎖相迴路1〇〇可產 生振盪頻率與繫色訊號相同的次載波訊號，並鎖定繫色訊 號與次載波訊號的相位，使兩訊號間不存在任何相位差。 然而，此種習知的數位鎖相迴路100,當繫色訊號與副 1274474 載波訊號的相位差超過90度時，其頻率相位偵測器102卻 可能將兩者的相位差錯誤地鎖相在180度，而無法正確地 鎖定在〇度。第2圖係繪示繫色訊號與副載波訊號被鎖定 在反相位的示意圖。如第2圖所示，上述情況將導致繫色 訊號202(實線）與副載波訊號204(虛線）二者在穩態時卻被 鎖定在反相位，因而使得後面之顏色解調器將無法解調出 正確的顏色。 因此，習知技術提出數種不同的方法或裝置來解決此 相位錯誤鎖定問題。舉例來說，中攀民國專利第373,389 號「一種可與電腦相連接之視訊輸入裝置及方法」，其揭示 使用查表法來解決相位錯誤鎖定的裝置及方法：或是，例 如美國專利第 6,741，289 號「Technique to stabilize the chrominance subcarrier generation in a line-locked digital video system」以及第 6,310,653 號「Phase comparison and phase adjustment for synchronization to a reference signal that is asynchronous with respect to a digital sampling clock」，均運用非常複雜的電路架構來解決前述問題。 其他習知技術如美國專利第6,538,702號「Digital color signal reproducing circuit」以及第 6,034,735 號「Clock generator for digital video signal processing apparatus」貝1J 是 使用相位補償的方法解決前述問題，但是均需要大型電路 而且難以快速完成相位的鎖定。 【發明内容】 因此本發明一方面就是在提供一種數位鎖相迴路，其 1274474 電路結構簡單，且可快速鎖定數位輸人訊號以及數位輸出 訊7虎的相位。 本發明另-方面是在提供一種用於電視訊號解碼器中 的數位鎖相迴路，以解決習知數位鎖相迴路之相位錯誤 定的問題。 根據本發明之一較佳實施例，此數位鎖相迴路包含一 頻率相位偵測器、一迴路濾波器、一數位控制振盪器、一 數值偵測器以及一相位延遲比較器。頻率相位偵測器係用 以比較數位輸入訊號以及數位輸出訊號之相位，並依此產 生相位差訊號。迴路濾波器係對相位差訊號進行數位濾 波，數位控制振盪器則根據已濾波之相位差訊號產生數位 輸出訊號。 數值j貞測器係用以偵測數位輸出訊號，並輸出數位輸 出訊號之波峰值或波谷值。相位延遲比較器則接收數位輸 出訊號之波峰值或波谷值以及數位輸入訊號，並判斷波峰 值或波谷值的最高位元與同時輸入相位延遲比較器之數位 輸入訊號的最高位元是否相同。當波峰值或波谷值的最高 位元與同時輸入之數位輸入訊號的最高位元不相同時，相 位延遲比較器會改變被輸入至頻率相位偵測器之數位輸入 訊號的相位。 本發明又一方面是在提供一種電視訊號相位鎖定的方 法’用以解決習知繫色訊號以及副載波訊號在穩態時被鎖 定在相反相位的問題。 根據本發明之另一較佳實施例，此電視訊號相位鎖定 的方法係用以鎖定一數位輸入訊號以及一數位輸出訊號之 1274474 相位。數位輸人訊號係為_數位弦波，且數位輸出訊號係 根據數位輸人訊號而被重複產生。首先，制數位輸出訊 號之波峰值或波谷值。當偵測到波峰值或波谷值時，判斷 波峰值或波谷值的最高位元與同時輸人之數位輸人訊號的 最高位元是否相同。當波峰值或波谷值的最高位元與同時 輸入之數位輸人訊號的最高位元不相同時，改變此數位輸 入δίΐ 3虎之相位。 此數位鎖相迴路與方法之電路結構簡單，且適用於 NTSC/PAL/SECΑΜ電視系統中，可快速同步數位輸入訊號 以及數位輸出遽’使兩者具有相同的相位，以便後端的 顏色調解器解調出正確的顏色。 【實施方式】 第3圖係綠示本發明之一較佳實施例之電路功能方塊 圖。此數位鎖相迴路300包含一頻率相位债測器3〇2、一迴 路濾波器304、一數位控制振盪器3〇6、_數值偵測器· =及-相位延遲比較器312。頻率相位_器搬係用以比 較數位輸人訊號以及數位輸出訊號的相位，並依此產生一 相位差《。料錢^ 3G4係對此相位差⑽進行數位 慮波’數㈣龍纽3〇6職據已缝之料差訊號產 生，位輸出訊號，並將此數位輸出訊號發送至頻率相位摘 測器302以及數值偵測器308。 數值偵測器308係用'以债測數位輸出訊號，並輸出此 數位輸出訊號之波蜂值或波谷值。相位延遲比較器312則 接收由數值偵測器谓傳送來的數位輪出訊號之波峰值或 1274474 波谷值以及數位輸入訊號，並判斷波峰值或波谷值的最汽 位元（most significant bit; MSB)與同時輸入相位延遲比較 器312之數位輸入訊號的最高位元是否相同。當波峰值或 波谷值的最高位元與同時輸入之數位輸入訊號的最高位元 不相同時，相位延遲比較器312會改變被輸入至頻率相位 债測器302之數位輸入訊號的相位。 第4A圖係繪示此較佳實施例之頻率相位偵測器3〇2 的運作原理示意圖。如第4A圖所示，此頻率相位偵測器 302係依照下列等式（1)得出數位輸入訊號以及數位輸出訊 號之間的相位差：〜 〇e a =f [sin(^ + θ0 )cos(^ + θ,)]} sign^ [cos(d〇/ + θ0 )cos(c〇i + Θί)]} (1) =± sin 9e · sign(± cos 6e) 在4式（i)中，θ,·係表示數位輸入訊號之相位，0。係表示 數位輸出訊號之相位，而&則表示數位輸入訊號以及數位輸 出訊號兩者間的相位差。經過等式（1)之運算所得出的相位 差。K唬，其貫際上僅為一近似值。而數位控制振盪器3⑽ 即根據此相位差訊號修正並產生與數位輸入訊號沒有相位 差的數位輸出訊號。 然而，由於在上述之等式（1)中實際上存在正負號，這 會發生正乘正為正，而負乘負也為正的情況。如此導致頻 率相位债測器302在穩態時可能無法正確判斷數位輸入訊 1274474 號以及數位輸出訊號為同相位或是反相位。 因此，此較佳實施例係先偵測數位輸入訊號以及數位 輸出訊號兩者是否反相位。若此兩訊號為反相位，則使用 延遲數位輸入訊號的方式，來達成數位輸入訊號以及數位 輸出訊號的同步，使此兩訊號變得具有相同的相位。 第4B圖係繪示此較佳實施例之相位延遲比較器3 之1274474 IX. Description of the Invention: [Technical Field] The present invention relates to a color television system, and more particularly to a device and method for generating a color subcarrier. [Prior Art] In recent years, receivers of different television systems have been widely used with the popularity of televisions, and have been getting better and better performance. For example, it is widely used in NTSC and digital color signal reproducing circuits in PAL systems. Figure 1 shows a schematic diagram of a conventional digital phase-locked loop that can be applied to NTSC/PAL/SECAM television systems. The function of the digital phase locked loop 1 产生 generates a subcarrier (sub_carrier) signal according to the input color burst signal for use by a subsequent color demodulator. As shown in Fig. 1, a phase detector (PD) 102 is used to compare the phase of the color signal and the subcarrier signal, and accordingly generate a phase difference signal. The phase difference signal is then filtered by a first loop filter 104, and the filtered phase difference signal is then input to a digital control oscillator (DCO) 106. The digitally controlled oscillator 106 generates a subcarrier signal based on the filtered phase difference signal and returns the generated subcarrier signal to the frequency phase detector 102. Through the above feedback process, the digital phase-locked loop 1 产生 can generate a sub-carrier signal with the same oscillation frequency and color signal, and lock the phase of the color signal and the sub-carrier signal, so that there is no phase difference between the two signals. . However, in the conventional digital phase-locked loop 100, when the phase difference between the color signal and the sub-1274744 carrier signal exceeds 90 degrees, the frequency phase detector 102 may incorrectly lock the phase difference between the two. 180 degrees, and can't lock correctly in the twist. Figure 2 is a schematic diagram showing the phase signal and the subcarrier signal being locked in opposite phases. As shown in Fig. 2, the above situation will cause both the color signal 202 (solid line) and the subcarrier signal 204 (dashed line) to be locked in the opposite phase at steady state, thus causing the latter color demodulator to Unable to demodulate the correct color. Therefore, the prior art proposes several different methods or devices to solve this phase error locking problem. For example, the Chinese Patent No. 373,389, "A Video Input Device and Method Connectable to a Computer," discloses a device and method for solving phase error locking using a look-up table method: or, for example, U.S. Patent No. 6,741 , "No. 289 "Technique to stabilize the chrominance subcarrier generation in a line-locked digital video system" and No. 6,310,653 "Phase comparison and phase adjustment for synchronization to a reference signal that is asynchronous with respect to a digital sampling clock" Very complex circuit architecture to solve the aforementioned problems. Other conventional techniques, such as "Digital color signal reproducing circuit" in U.S. Patent No. 6,538,702 and "Clock generator for digital video signal processing apparatus" No. 6,034,735, solve the aforementioned problems by using a phase compensation method, but both require a large circuit and are difficult. Quickly complete the phase lock. SUMMARY OF THE INVENTION Therefore, in one aspect of the present invention, a digital phase-locked loop is provided, wherein the 1274474 circuit has a simple structure, and can quickly lock the phase of the digital input signal and the digital output signal. Another aspect of the present invention is to provide a digital phase locked loop for use in a television signal decoder to solve the problem of phase error of a conventional digital phase locked loop. According to a preferred embodiment of the present invention, the digital phase locked loop includes a frequency phase detector, a loop filter, a digitally controlled oscillator, a numerical detector, and a phase delay comparator. The frequency phase detector is used to compare the phase of the digital input signal and the digital output signal, and thereby generate a phase difference signal. The loop filter performs digital filtering on the phase difference signal, and the digitally controlled oscillator generates a digital output signal based on the filtered phase difference signal. The value detector is used to detect the digital output signal and output the peak value or valley value of the digital output signal. The phase delay comparator receives the peak value or valley value of the digital output signal and the digital input signal, and determines whether the highest bit of the peak value or the trough value is the same as the highest bit of the digital input signal of the simultaneous input phase delay comparator. The phase delay comparator changes the phase of the digital input signal that is input to the frequency phase detector when the highest bit of the peak or valley value is different from the highest bit of the digital input signal that is simultaneously input. Yet another aspect of the present invention is to provide a method of phase locking of television signals to solve the problem that conventional color signals and subcarrier signals are locked in opposite phases at steady state. According to another preferred embodiment of the present invention, the method of phase locking the television signal is used to lock a digital input signal and a 1274474 phase of a digital output signal. The digital input signal is a _ digital sine wave, and the digital output signal is repeatedly generated according to the digital input signal. First, the peak value or valley value of the digital output signal is made. When a peak value or a trough value is detected, it is determined whether the highest bit of the peak value or the trough value is the same as the highest bit of the digital input signal simultaneously input. When the highest bit of the peak value or the trough value is different from the highest bit of the digital input signal input at the same time, the phase of the digital input δίΐ 3 is changed. The digital phase-locked loop and method have a simple circuit structure and are suitable for use in an NTSC/PAL/SEC/TV system. The digital input signal and the digital output can be quickly synchronized to make the two phases have the same phase, so that the color mediator of the back end can be solved. Bring up the correct color. [Embodiment] Fig. 3 is a block diagram showing the circuit function of a preferred embodiment of the present invention. The digital phase locked loop 300 includes a frequency phase debt detector 3〇2, a loop filter 304, a digitally controlled oscillator 3〇6, a _value detector·= and a phase delay comparator 312. The frequency phase is used to compare the phase of the digital input signal and the digital output signal, and thereby generate a phase difference. The money ^ 3G4 is the digital phase difference (10) for the digital wave 'number (four) Long New 3 〇 6 job data has been generated by the gap signal, the bit output signal, and the digital output signal is sent to the frequency phase sifter 302 And a value detector 308. The value detector 308 outputs the signal by the 'bit measurement number and outputs the wave bee value or trough value of the digital output signal. The phase delay comparator 312 receives the peak value or the 1274474 wave trough value and the digital input signal transmitted by the value detector, and determines the most significant bit (MSB) of the peak value or the trough value. Whether or not the highest bit of the digital input signal of the phase delay comparator 312 is simultaneously input. The phase delay comparator 312 changes the phase of the digital input signal input to the frequency phase detector 302 when the highest bit of the peak or valley value is not the same as the highest bit of the digital input signal that is simultaneously input. FIG. 4A is a schematic diagram showing the operation principle of the frequency phase detector 3〇2 of the preferred embodiment. As shown in FIG. 4A, the frequency phase detector 302 derives the phase difference between the digital input signal and the digital output signal according to the following equation (1): ~ 〇ea =f [sin(^ + θ0 )cos (^ + θ,)]} sign^ [cos(d〇/ + θ0 )cos(c〇i + Θί)]} (1) =± sin 9e · sign(± cos 6e) In Equation 4 (i) , θ, · indicates the phase of the digital input signal, 0. It represents the phase of the digital output signal, and & represents the phase difference between the digital input signal and the digital output signal. The phase difference obtained by the operation of equation (1). K唬, which is only an approximation. The digitally controlled oscillator 3 (10) corrects and generates a digital output signal having no phase difference from the digital input signal based on the phase difference signal. However, since there is actually a sign in the above equation (1), this occurs when the positive multiplication is positive and the negative multiplication is positive. As a result, the frequency phase detector 302 may not correctly determine whether the digital input signal 1274474 and the digital output signal are in phase or opposite phase. Therefore, in the preferred embodiment, it is first detected whether the digital input signal and the digital output signal are opposite to each other. If the two signals are in anti-phase, the digital input signal is delayed to synchronize the digital input signal and the digital output signal so that the two signals have the same phase. FIG. 4B is a diagram showing the phase delay comparator 3 of the preferred embodiment.
電路功能方塊圖。一般來說，數位訊號的正負號可由其符 號位元（sign bit)來表示，而此符號位元通常即為其最高位 元（most significant bit ; MSB)。亦即，由比較兩數位訊號 之最高位元是否相同即可得知此兩數位訊號之正負號是否 相同，如此即可得知此兩數位訊號為同相位或反相位。 如第4B圖所示，此相位延遲比較器312兼具比較訊號 相位以及延遲訊號相位的功能，其包含一最高位元比較器 4〇2、一延遲裝置404以及一多工器4〇6。最高位元比較器 402係用以判斷數位輸出訊號之波峰值或波谷值的最高位 元與同時輸入相位延遲比較n 312之數位輸入訊號的最高 位否相同。值得注意的是，在實際應用上，相位延遲 比較器312僅需判斷波峰值以及波谷值其中之一者即可， 並不須同時具備可同時判斷兩者的能力。 當最高位元比較器402的輸出值為，，〇,,時，則表示數位 輸入訊號以及數位輸出訊號互為反相位。此輸出值，，〇·，接著 會被傳送至多工ϋ偏，使得被延遲I置4G4延遲的數位輸 入訊號通過多工器偏被傳送至頻率相位_器3G2,達成 相位延遲的效果。而且，最高位元比㈣402在___ 次判斷之後會將其輸出值則—直Μ在”『，直到下一個書 1274474 面做重新判斷。 田取回位元比較器4〇2 則表示數位輸入訊號以及 =出值為1時， 輸出汛唬互為同相位。此輕 . 夕工斋406,使得數位輸入訊號 直接破傳迗至頻率相位偵 402在“赞 制斋3〇2。而且，最高位元比較器 在、、、工過第一次判斷之後合 更曰將其輸出值則一直固定在 ，直到下一個畫面做重新判斷。Circuit function block diagram. In general, the sign of a digital signal can be represented by its sign bit, which is usually the most significant bit (MSB). That is, whether the sign of the two-digit signal is the same by comparing whether the highest bit of the two-digit signal is the same is the same, so that the two-digit signal is in phase or opposite phase. As shown in FIG. 4B, the phase delay comparator 312 has a function of comparing the signal phase and delaying the signal phase, and includes a highest bit comparator 4〇2, a delay device 404, and a multiplexer 4〇6. The highest bit comparator 402 is configured to determine whether the highest bit of the peak value or the trough value of the digital output signal is the same as the highest bit of the digital input signal of the simultaneous input phase delay comparison n 312. It is worth noting that, in practical applications, the phase delay comparator 312 only needs to determine one of the peak value and the valley value, and does not need to have the ability to simultaneously judge both. When the output value of the highest bit comparator 402 is ,, 〇, , , the digital input signal and the digital output signal are opposite to each other. This output value, 〇·, is then transmitted to the multiplexed offset so that the digital input signal delayed by I4G4 is transmitted to the frequency phase_3G2 through the multiplexer bias to achieve the phase delay effect. Moreover, the highest bit ratio (four) 402 will be its output value after ___ judgments, and it will be judged again until the next book 1274474. The field retrieves the bit comparator 4〇2 to indicate the digital input. When the signal and the = value are 1, the output 汛唬 are in phase with each other. This light. Xigong Zhai 406, so that the digital input signal is directly transmitted to the frequency phase detection 402 in "Zanzhan 3〇2. Moreover, the highest bit comparator is fixed after the first judgment, and the output value is fixed until the next screen is re-judged.
—述之L遲#置404較佳地可由複數個緩衝H(BUF) 電性串接而組成’其作用係用以延遲數位輸人訊號的相 位。而且，根據本發明之其他較佳實施例，若數位輸入訊 號或數位輸人訊號並不是以其最高位元代表其正負號時， 則可使用符號位元比較器來取代上述之最高位元比較器 '02。更具體地說，相位延遲比較器此時係根據符號位元比 較數位輸出訊號之波峰值或波谷值與同時輸人相位延遲比 較器之數位輸入訊號兩者的相位是否相同。The L-station 404 is preferably composed of a plurality of buffers H (BUF) electrically connected in sequence to 'delay the phase of the digital input signal. Moreover, according to other preferred embodiments of the present invention, if the digital input signal or the digital input signal does not represent its sign with its highest bit, a sign bit comparator can be used instead of the highest bit comparison described above. '02. More specifically, the phase delay comparator is now based on whether the phase of the sign or the peak value or valley of the digital output signal is the same as the phase of the digital input signal of the phase input comparator.
根據本發明之一較佳實施例，上述之數位鎖相迴路300 係用於一電視訊號解碼器中，此時數位輸入訊號為一繫色 訊號，且數位輸出訊號則為一副載波訊號。繫色訊號以及 田1J載波汛號具有相同的振盪週期，且每一個振盪週期具有 N個取樣點。而且，此取樣點的個數n係由繫色訊號之振 盪頻率以及一取樣頻率所決定。當副載波訊號之波峰值或 波谷值的最高位元與同時輸入之繫色訊號的最高位元不相 同時’該相位延遲比較器312會將該繫色訊號延遲[N/2]或 [N/2] + l個取樣點。此處的符號[]係表示階梯函數（fi〇〇r function)或南斯函數（Guass function)，其值為小於或等於符 12 1274474 號口中數值的最大整數值’例如[3.4]的值為3，而[4.6]的值 為4 〇 舉例來說’當繫色訊號之振盪頻率為3·58ΜΗζ，且其 取樣頻率為54MHz時，此繫色訊號之每一個振盪週期係由 15個取樣點所構成，且每一個取樣點代表24度。當副載波 訊號之波峰值或波谷值與繫色訊號之相位不同時，亦即副 載波訊號以及繫色訊號被鎖定在相反相位時，該相位延遲 比較器312會將繫色訊號延遲7或8個取樣點。如此相當 於將繫色訊號延遲168度（7個取樣點）或192度（8個取樣 點），使得延遲後之繫色訊號與副載波訊號之相位相差僅12 度，進而使兩者具有相同的相位。 第5圖係繪示本發明之一較佳實施例之方法流程圖。 如第5圖所示，此電視訊號相位鎖定的方法係用以鎖定一 數位輸入訊號以及一數位輸出訊號之相位。此數位輸入訊 號係為一數位弦波，且數位輸出訊號係根據數位輸入訊號 而被重複產生（reproduced)。 首先，偵測數位輸出訊號以及數位輸入訊號的相位 差，並依此產生一相位差訊號（步驟5〇2)。然後對此相位差 訊號進行數位濾波，以去除不必要雜訊的干擾（步驟5〇4)。 再根據此已濾波之相位差訊號，產生數位輸出訊號（步驟 506) 〇 接著，當數位輸出訊號以及數位輸入訊號達到穩態 時，偵測此數位輸出訊號之波峰值或波谷值（步驟5〇8)。當 偵測到波峰值或波谷值時，判斷波峰值或波谷值的最高位 疋與同時輸入之數位輸入訊號的最高位元是否相同（步驟 13 1274474 512)。當波峰值或波谷值的最高位元與同時輸入之數位輸 入訊號的最高位元不相同時，改變此數位輸入訊號之相位 (步驟514);當波峰值或波谷值的最高位元與同時輸入之數 位輸入訊號的最高位元相同時，則不改變此數位輸入訊號 之相位（步驟516)。 根據本發明之一較佳實施例，此方法係應用於一電視 訊號解碼器中，此時數位輸入訊號為一繫色訊號，且數位 輸出訊號則為一副載波訊號。繫色訊號以及副載波訊號具 有相同的振盪週期，且每一個振盪週期具有N個取樣點。 而且，此取樣點的個數N係由繫色訊號之振盪頻率以及一 取樣頻率所決定。當副載波訊號之波峰值或波谷值的最高 位元與同時輸入之繫色訊號的最南位元不相同時，將該繫 色訊號延遲[N/2]或[N/2] + l個取樣點。此處的符號[]係表示 階梯函數（floor function)或高斯函數（Guass functi〇n)，其值 為小於或等於符號□中數值的最大整數值。 以NTSC電視系統為例，其取樣頻率為27 mhz，而繫 色訊號為一數位弦波’其振盪頻率約為3·58 MHz，所以繫 色號的母一個振盪週期是由7或8個取樣點所組成。若 以8個取樣點來表示，則每一個取樣點代表48度。當繫色 訊號以及副載波號的相位相反時，即兩者相差18 〇度時， 則將繫色訊號延遲四個點（相當於192度），如此使得繫色訊 號以及副載波讯號相差12度’進而再利用此回授過程將繫 色訊號以及副載波訊號之相位差鎖定在〇度。 第6圖係繪示此較佳實施例之繫色訊號與副載波訊號 被鎖定在同相位的示意圖。如第6圖所示，此較佳實施例 1274474 可將原本如第2圖所示鎖定在相反相位之繫色訊號202(實 線）與副載波訊號204(虛線）經由相位延遲而被鎖定成同相 位的繫色訊號602(實線）以及副載波訊號604(虛線），以供 後面之顏色解調器解調出正確的顏色。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之詳細說明如下： 第1圖係繪示一種習知數位鎖相迴路之示意圖；According to a preferred embodiment of the present invention, the digital phase-locked loop 300 is used in a television signal decoder. In this case, the digital input signal is a color signal, and the digital output signal is a sub-carrier signal. The system color signal and the field 1J carrier apostrophe have the same oscillation period, and each sampling period has N sampling points. Moreover, the number n of the sampling points is determined by the oscillation frequency of the color signal and a sampling frequency. When the peak of the peak value or the trough value of the subcarrier signal is different from the highest bit of the simultaneously input moiré signal, the phase delay comparator 312 delays the color signal by [N/2] or [N /2] + 1 sampling point. The symbol [] here represents a step function (fi〇〇r function) or a Guass function, and its value is less than or equal to the maximum integer value of the value in the mouth of the number 12 1274474 'for example, [3.4] 3, and the value of [4.6] is 4 〇 For example, when the oscillation frequency of the color signal is 3.58 ΜΗζ and the sampling frequency is 54 MHz, each oscillation period of the color signal is 15 sampling points. Constructed, and each sampling point represents 24 degrees. When the peak value or the trough value of the subcarrier signal is different from the phase of the color signal, that is, when the subcarrier signal and the color signal are locked in opposite phases, the phase delay comparator 312 delays the color signal by 7 or 8. Sample points. This is equivalent to delaying the color signal by 168 degrees (7 sampling points) or 192 degrees (8 sampling points), so that the phase of the delayed color signal and the subcarrier signal are only 12 degrees apart, so that the two have the same The phase. Figure 5 is a flow chart showing a method of a preferred embodiment of the present invention. As shown in Fig. 5, the phase locking method of the television signal is used to lock the phase of a digital input signal and a digital output signal. The digital input signal is a digital sine wave, and the digital output signal is repeatedly generated based on the digital input signal. First, the phase difference between the digital output signal and the digital input signal is detected, and a phase difference signal is generated accordingly (step 5〇2). This phase difference signal is then digitally filtered to remove unwanted noise (step 5〇4). Then, according to the filtered phase difference signal, a digital output signal is generated (step 506). Then, when the digital output signal and the digital input signal reach a steady state, the peak value or the trough value of the digital output signal is detected (step 5〇). 8). When a peak value or a trough value is detected, it is judged whether the highest level of the peak value or the trough value is the same as the highest bit of the digital input signal input at the same time (step 13 1274474 512). When the highest bit of the peak value or the trough value is different from the highest bit of the digital input signal input at the same time, the phase of the digital input signal is changed (step 514); when the highest bit of the peak value or the trough value is simultaneously input When the highest bit of the digital input signal is the same, the phase of the digital input signal is not changed (step 516). According to a preferred embodiment of the present invention, the method is applied to a television signal decoder. In this case, the digital input signal is a color signal, and the digital output signal is a subcarrier signal. The color signal and the subcarrier signal have the same oscillation period, and each sampling period has N sampling points. Moreover, the number N of the sampling points is determined by the oscillation frequency of the color signal and a sampling frequency. When the highest bit of the peak value or the trough value of the subcarrier signal is different from the southernmost bit of the simultaneously input moiré signal, the color signal is delayed by [N/2] or [N/2] + l Sampling point. The symbol [] here represents a floor function or a Gaussian function (Guass functi〇n) whose value is the largest integer value less than or equal to the value in the symbol □. Taking the NTSC TV system as an example, the sampling frequency is 27 mhz, and the color signal is a digital sine wave whose oscillation frequency is about 3.58 MHz, so the mother's one oscillation period is 7 or 8 samples. The composition of points. If represented by 8 sampling points, each sampling point represents 48 degrees. When the phase of the color signal and the subcarrier number are opposite, that is, when the two are different by 18 degrees, the color signal is delayed by four points (equivalent to 192 degrees), so that the color signal and the subcarrier signal are different by 12 Then, the feedback process is used to lock the phase difference between the color signal and the subcarrier signal in the degree of twist. Figure 6 is a schematic diagram showing that the color signal and the subcarrier signal of the preferred embodiment are locked in phase. As shown in FIG. 6, the preferred embodiment 1274474 can lock the color signal 202 (solid line) and the subcarrier signal 204 (dashed line), which are locked in opposite phases as shown in FIG. 2, by phase delay. The in-phase color signal 602 (solid line) and subcarrier signal 604 (dashed line) are used by the subsequent color demodulator to demodulate the correct color. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; Schematic diagram
第2圖係繪示習知繫色訊號與副載波訊號被鎖定在反 相位的示意圖； 圖； 第3圖係繪示本發明之一較佳實施例 之電路功能方塊 作2 2圖騎不此較佳實施例之頻率相位㈣器的運 作原理不意圖； 遲比較器之電 第4B圖係繪示此較佳實施例之相位延 路功能方塊圖； 第5圖係緣示本蘇 以及 衫月之㈣實_之方法流程圖； 15 1274474 第6圖係繪示此較佳實 被鎖定在同相位的示意圖。 施例之繫色訊號與副載波訊號2 is a schematic diagram showing the conventional color signal and the subcarrier signal locked in the opposite phase; FIG. 3 is a schematic diagram showing the circuit function block of a preferred embodiment of the present invention. The operation principle of the frequency phase (four) device of the preferred embodiment is not intended; the fourth embodiment of the power of the late comparator is shown in the block diagram of the phase extension function of the preferred embodiment; the fifth figure shows the system and the shirt. Flow chart of the method of the month (4) _ _ 15 1274474 Figure 6 is a schematic diagram showing that the better is locked in the same phase. Color signal and subcarrier signal of the example
【主要元件符號說明】 100 ·數位鎖相迴路 104 ··迴路濾波器 202 :繫色訊號 300 :數位鎖相迴路 304 :迴路濾波器 308 :數值偵測器 402 ·最南位元比較器 406 :多工器 502 、 504 、 506 、 508 、 6〇2 ·•繫色訊號 102 ··頻率相位偵測器 106 :數位控制振盪器 204 :副載波訊號 302 :頻率相位偵測器 306 :數位控制振盪器 312 :相位延遲比較器 404 :延遲裝置 512、514、516 :步驟 604 :副載波訊號[Description of main component symbols] 100 · Digital phase-locked loop 104 · · Loop filter 202 : Color signal 300 : Digital phase-locked loop 304 : Loop filter 308 : Numerical detector 402 · Southernmost comparator 406 : Multiplexers 502, 504, 506, 508, 6〇2 • Color signal 102 • Frequency phase detector 106: Digitally controlled oscillator 204: Subcarrier signal 302: Frequency phase detector 306: Digitally controlled oscillation 312: phase delay comparator 404: delay means 512, 514, 516: step 604: subcarrier signal
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