JPH05219407A - Agc circuit for video signal - Google Patents

Abstract

PURPOSE:To attain no adjustment of the video signal AGC circuit, to make the operation stable and to improve the transient response characteristic. CONSTITUTION:An input analog video signal is given to an analog gain control amplifier 2, in which the level of the signal is adjusted by an analog output signal F1 outputted from a microcomputer 7. An output of the analog gain control amplifier 2 is given to an A/D converter circuit 4, in which the signal is converted into a digital video signal. A video synchronizing signal detection circuit 6 detects a SYNC tip level and a pedestal level of the digital video signal to transfer the result to the microcomputer 7. The microcomputer 7 calculates a synchronization level to generate the analog output F1 used to control the gain of the analog gain control amplifier 2 and a digital data F2 outputted to a multiplier circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AGC circuit for a video signal (hereinafter referred to as a video AGC circuit) in a magnetic recording / reproducing apparatus, etc. It is about.

[0002]

2. Description of the Related Art Conventionally, as a video AGC circuit, for example, an analog video AGC circuit disclosed in Japanese Patent Laid-Open No. 63-1265 and a digital video AGC circuit disclosed in Japanese Patent Laid-Open No. 60-75112. It has been known. FIG. 3 is a block diagram showing the configuration of a conventional analog video AGC circuit, and FIG. 4 is a conventional digital video AGC circuit.
Block diagram showing the configuration of the GC circuit, FIG. 5 is a video AGC
It is a video signal waveform diagram input into a circuit.

In FIGS. 3 and 5, the analog gain control amplifier 11 is controlled by the output of the control voltage generation circuit 14, and the sync tip level a of the output video signal is controlled.
The gain is adjusted so that the synchronization level L, which is the difference between the pedestal level b and the pedestal level b, becomes a predetermined level (eg, 0.5 V).
The sync level detection circuit 12 detects the sync level L of the video signal output by the analog gain control amplifier 11. This circuit is configured by, for example, a circuit that samples and holds a sync chip level a and a pedestal level b of a video signal to obtain the difference between them. The reference level adjusting circuit 13 creates a reference voltage for setting the synchronization level L of the output video signal to a predetermined level (for example, 0.5V),
The control voltage generation circuit 14 outputs the difference voltage between the synchronization level L of the output video signal detected by the synchronization level detection circuit 12 and the reference voltage output by the reference level adjustment circuit 13, and outputs the gain adjustment voltage to the analog gain control amplifier 11. To do.

Analog video A constructed as described above
In the GC circuit, feedback control is performed so that the sync level L of the output video signal detected by the sync level detection circuit 12 becomes equal to the output of the reference level adjustment circuit 13, so that the sync level L of the output video signal is a predetermined level ( (Eg, 0.5 V). Next, in FIG.
The analog gain control amplifier 21 is controlled by the output of the control voltage generation circuit 26, and adjusts the gain so that the synchronization level L of the output video signal becomes a predetermined level (for example, 0.5V). The A / D conversion circuit 22 converts the output of the analog gain control amplifier 11 into, for example, a 10-bit parallel digital video signal. The sync signal detection circuit 23 detects the sync signal of the digital video signal, and the pedestal detection circuit 24 detects the pedestal data corresponding to the pedestal level b of the digital video signal based on the output of the sync signal detection circuit 23, and the sync chip The detection circuit 25 detects sync chip data corresponding to the sync chip level a of the digital video signal based on the output of the sync signal detection circuit 23. Control voltage generation circuit 26
Is a difference between the pedestal data detected by the pedestal level detection circuit 24 and the sync chip data detected by the sync chip detection circuit 25, and the sync level L of the output digital video signal is a predetermined level (eg, 0.5 V).
A gain adjustment voltage for generating the output is generated and output to the analog gain control amplifier 21.

Also in the digital video AGC circuit configured as described above, the synchronization level of the output digital video signal is controlled to a predetermined level (for example, 0.5 V) in the same manner as in FIG.

[0006]

However, the conventional analog video AGC circuit described above has a problem that a reference level adjusting circuit is required and no adjustment can be performed. Further, in order to perform gain adjustment with high accuracy, a high resolution gain control amplifier is required, which causes a problem that the circuit becomes unstable in operation.

Further, the above conventional analog video AGC
Since the circuit and the digital video AGC circuit are feedback-controlled, there is a problem that oscillation occurs when the response speed is increased. That is, the transient response characteristic was not good. The present invention solves the above problems,
It is an object of the present invention to provide a video AGC circuit that can be adjusted, can perform stable operation, and has excellent transient response characteristics.

[0008]

In order to solve the above problems, the present invention relates to a video AGC circuit, in which an analog gain control amplifier for adjusting the level of an input analog video signal and an output of the analog gain control amplifier are digital. A / D conversion circuit for converting into a video signal, a sync level detection circuit for detecting a sync level of a digital video signal output from the A / D conversion circuit, and A / D
Digital gain control amplifier that adjusts the level of the digital video signal that is the output of the D conversion circuit, and first control that creates a first control signal that adjusts the gain of the analog gain control amplifier based on the output of the synchronization level detection circuit A signal generation circuit and a second control signal generation circuit for generating a second control signal for adjusting the gain of the digital gain control amplifier based on the output of the synchronization level detection circuit are provided.

[0009]

According to the present invention, since the video AGC circuit is constructed as described above, the input analog video signal is controlled by the first control signal in the analog gain control amplifier, adjusted to a predetermined level, and then the A It is converted into a digital video signal by the / D conversion circuit. Then, the digital video signal is controlled by the second control signal in the digital gain control amplifier, and is adjusted to a predetermined level again.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a video AGC circuit according to an embodiment of the present invention. A clamp circuit 1 clamps a sync chip of an input analog video signal to a predetermined level. In the case of the analog video signal of 2.0V _PP shown in FIG. 5, it is clamped at 0.0V. The analog gain control amplifier 2 is controlled by the analog output signal F1 of the microcomputer 7 and adjusts the output level of the clamp circuit 1 so that the synchronization level L of the output video signal becomes a predetermined level (for example, 0.5V). Adjust the gain to. The sample and hold circuit 3 samples and holds the output video signal of the analog gain control amplifier 2 at, for example, a frequency four times as high as the color subcarrier. The A / D conversion circuit 4 converts the output of the sample and hold circuit 3 into a 10-bit digital video signal. The low-pass filter 5 removes noise components, color components, etc. in the digital video signal. The video sync detection circuit 6 detects the sync chip level and the pedestal level of the digital video signal output from the low pass filter 5. The video sync detection circuit 6 is a sync signal detection circuit 23 in a conventional digital video AGC circuit,
Pedestal detection circuit 24 and sync tip detection circuit 25
Equivalent to. Then, the microcomputer 7 outputs an analog output signal for adjusting the gain of the analog gain control amplifier 2 based on the sync chip level and the pedestal level output from the video sync detection circuit 6 and digital data (coefficient value) output to the multiplication circuit 8. Create F2. The multiplication circuit 8 multiplies the digital video signal output from the A / D conversion circuit 4 by the digital data from the microcomputer 7 so that the synchronization level of the digital video signal becomes a predetermined level (for example, 0.5 V). It is a multiplication circuit and functions as a digital gain control amplifier.

FIG. 2 is an operation flowchart of the microcomputer in the embodiment of the present invention. First, in step S1, sync chip level data D0 and pedestal level data D1 are fetched from the video sync detection circuit 6. Next, in step S2, the difference between D1 and D0 is calculated,
The data D2 corresponding to the synchronization level L is obtained. Next, in step S3, the reference synchronization level R stored in the ROM
The difference between 1 (e.g., 0.5 V) and D2 is calculated to obtain error data E1. Then, adaptive processing is performed in step S4 to obtain an analog output signal F1 for controlling the analog gain control amplifier 2 and a digital data F2 output to the multiplication circuit 8 as a function of the error data E.

Since the sync chip level and the pedestal level detected by the video sync detection circuit 6 are 10 bits each, they are transmitted to the microcomputer 7 in the form of serial signals or parallel signals. Further, the following processing is performed in the adaptive processing in step S4. (1) For example, the 8-bit error data E1 is converted into 4-bit rough error data, and this is D / A converted to obtain the analog output signal F1. As a result, the analog gain control amplifier 2 roughly adjusts the synchronization level. (2) The 8-bit error data E1 is fully utilized to obtain the digital data F2. As a result, the multiplication circuit 8
The synchronization level is finely adjusted with. (3) The analog output F1 is supplied to the analog gain control amplifier 2 at a rate of 1 field to once every several seconds,
The time constants of the analog amplifier and the digital amplifier are changed by supplying the digital data F2 to the multiplication circuit 8 once per horizontal scanning period to one field. As a result, the analog gain control amplifier absorbs a gradual change, and the digital gain control amplifier absorbs a sudden change that cannot be absorbed there. (4) If the error data E1 sharply changes for a short time, the error data before that is used. Thereby, the influence of noise can be avoided.

The AG of the video signal configured as described above
In the C circuit, the sync chip of the input analog video signal in the clamp circuit 1 has a predetermined level (for example, 0.0).
The analog gain control amplifier 2 is clamped to V) and the gain is adjusted by the analog output signal F1 output from the microcomputer 7 so that the synchronization level L becomes a predetermined level (for example, 0.5 V).

The output of the analog gain control amplifier 2 is sampled and held by the sample and hold circuit 3, converted into a 10-bit parallel digital video signal by the A / D conversion circuit, and unnecessary components such as noise are generated in the low pass filter 5. To be removed. Then, the sync chip data D0 and the pedestal data D1 detected by the video sync detection circuit 5 are transferred to the microcomputer 7.

The analog output signal F1 created by the microcomputer 7 based on the sync tip data D0 and the pedestal data D1 is transferred to the analog gain control amplifier 2 to adjust its gain. As a result, an analog video signal whose sync level L is adjusted to a predetermined level (for example, 0.5 V) is obtained at the output of the analog gain control amplifier 2.

Similarly, the gain control data F2 created by the microcomputer 7 based on the sync tip data D0 and the pedestal data D1 is transferred to the multiplication circuit 8 where it is multiplied by the digital video signal. As a result, a digital video signal whose sync level is adjusted to a predetermined level (for example, 0.5 V) is obtained at the output of the multiplication circuit 8.

In this embodiment, the video signal P-P (P
By providing a circuit for detecting the eak To Peak value, an AGC circuit (peak AGC circuit) for adjusting the PP value to a predetermined level or an AGC circuit combining a sink AGC circuit and a peak AGC circuit can be configured. .

[0018]

As described above in detail, the present invention has the following effects. (1) Since the gain control is performed based on the digital data in the analog gain control amplifier and the digital gain control amplifier, no adjustment is necessary. (2) After adjusting the gain of the video signal with the analog gain control amplifier, the gain is again adjusted with a digital gain control amplifier such as a multiplication circuit to an accurate value. Therefore, the resolution (sensitivity) of the analog gain control amplifier is increased so much. There is no need, and the circuit becomes stable. (3) If the time constant of the analog gain control amplifier and the time constant of the digital gain control amplifier are appropriately determined, a video AGC amplifier having higher performance than the conventional one can be realized. For example, if the analog gain control amplifier is subjected to feedback control with a large time constant and the digital gain control amplifier is subjected to feedforward control with a small time constant, the transient response characteristic can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video AGC circuit according to an embodiment of the present invention.

FIG. 2 is an operation flowchart of the microcomputer according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional analog video AGC circuit.

FIG. 4 is a block diagram showing a configuration of a conventional digital video AGC circuit.

FIG. 5 is a waveform diagram of a video signal input to the video AGC circuit.

[Explanation of symbols]

 1 Clamp circuit 2 Analog gain control amplifier 3 Sample and hold circuit 4 A / D conversion circuit 5 Low pass filter 6 Video sync detection circuit 7 Microcomputer 8 Multiplication circuit

Claims (1)

[Claims] 1. An analog gain control amplifier for adjusting the level of an input analog video signal, (b) an A / D conversion circuit for converting the output of the analog gain control amplifier into a digital video signal, and (c). A sync level detection circuit for detecting the sync level of the digital video signal output from the A / D conversion circuit; and (d) a digital gain control amplifier for adjusting the level of the digital video signal output from the A / D conversion circuit. And (e) first adjusting the gain of the analog gain control amplifier based on the output of the synchronization level detection circuit
A first control signal generating circuit for generating the control signal of (1), and (f) a second control signal generating for generating a second control signal for adjusting the gain of the digital gain control amplifier based on the output of the synchronization level detecting circuit. And an AGC circuit for video signals.