JP2553794B2 - Velocity error detector - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to VTR digital video signal processing, and is directed to a circuit for detecting a phase error in one line remaining in a reproduced video signal.

[0002]

2. Description of the Related Art In recent years, with the progress of semiconductor process technology, various digital technologies have been introduced for video signal processing of consumer VTRs.

For example, a TB for correcting the time base of a reproduced signal
C (time base collector) and the like have also been adopted as intermediate class machines due to the widespread use of large-capacity memory.

The TBC detects a phase error signal called a time base error and a velocity error from a reproduction synchronizing signal or a burst signal, and corrects the time axis based on the signal.

FIG. 6 is a waveform diagram showing the relationship between the time base error and the velocity error. Now, it is assumed that the residual phase error as shown in FIG. 6A has occurred in the reproduced signal. This phase error is detected at the beginning of each line of the video signal, and the signal held for 1H (H: horizontal synchronization period) is the time base error, which has the waveform shown in FIG. 6B.

Further, the velocity error is obtained by taking the difference of the time base error for each H, and has a waveform as shown in FIG. 6 (c).

If it is attempted to correct the residual phase error only by the time base error shown in FIG. 6B, the correction is effective at the beginning of each H of the video signal, but the correction is more effective toward the end. It will disappear and cause color unevenness on the right side of the screen. Therefore, it is necessary to detect the velocity error shown in FIG. 6C, and the residual phase error in the line can be almost completely corrected by combining it with the time base error.

Further, regarding color signals, an example using feedforward APC for correction of residual phase error in addition to conventional feedback APC (automatic phase control) is also reported, and similar to TBC as a residual phase error detection method. Any thing can be used.

As a method of detecting the above-mentioned velocity error, a circuit configuration as shown in FIG. 7 is conventionally used.

The differential signal .DELTA..theta. Given to the input terminal 7a represents the velocity error between each H and is a function of the first-order approximation shown in FIG. 6 (c). Therefore, N within 1H of the video signal
If there are sampling points, the slope of the linear function is represented by Δθ / N.
It is realized by using 1.

The counter 72 starts counting up by a 1-bit SP (start pulse) signal given to the input terminal 7c. Since the SP signal is input every N clocks, the count value changes from 0 to N-1.

Therefore, the velocity error in one line can be obtained by multiplying the outputs of the ROM table 71 and the counter 72 by the multiplier 63.

Finally, by adding the time base error θ _n-1 before 1H given to the input terminal 7b to the output of the multiplier 73 by using the adder 74, a velocity error detection signal is output to the output terminal 7d. Obtainable.

[0014]

However, the above-mentioned conventional configuration requires a ROM and a multiplier, and
If there is a possibility that the velocity error in the line is in the relation of Δθ ≧ N, the ROM table needs to output both the quotient and the remainder data. Therefore, in order to maintain the remainder data accuracy, the ROM table output Therefore, it is necessary to increase the number of bits input to the multiplier, and there is a problem that the circuit scale becomes large in order to realize an LSI.

[0015]

In order to achieve this object, a velocity error detecting device of the present invention is provided with an n-type video signal.
The absolute value circuit that takes the absolute value of the difference input signal, which is the difference between the phase error of the line n-1 and the phase error of the line n-1, and the output of the absolute value circuit and the 1-bit start pulse are input, and the result of the division A division circuit that outputs a quotient and a remainder, a delay circuit that delays the start pulse for a predetermined period, an output of the remainder of the division circuit and an output of the delay circuit are input, and a quotient correction signal is output in 1 bit. A correction signal generating circuit, a correction data generating circuit which outputs the correction signal generating circuit and the sign bit of the difference input signal and outputs correction data of a quotient, an output of the correction data generating circuit and a division circuit. An adder for adding the output of the quotient, and an integrating circuit for receiving the output of the adder, the phase error of the (n-1) th line and the output of the delay circuit, and outputting a detection signal of the velocity error. It has a configuration consisting of.

[0016]

According to the present invention, the amplitude of the velocity error is first obtained by the absolute value circuit with the above-mentioned configuration. The division circuit divides the constant "N" from the obtained amplitude value. The result of division is 1
It represents the slope of the next function, and the integer part is output as the quotient and the decimal part is output as the remainder.

The correction signal generation circuit cumulatively adds the remainders and generates a correction signal for the quotient each time a carry to the integer part is detected.

Based on this correction signal, the correction data generation circuit generates "1" at the time of correction and "0" at the time of non-correction, and further, -1 times in the case of a monotone decrease according to the sign of the differential input signal. Is output.

The new correction data added with the quotient by the adder is cumulatively added by the integrating circuit, and is added with the time base error of 1H before so that even if the slope of the linear function is 1 or more, an accurate one line is obtained. Velocity error in can be detected.

[0020]

EXAMPLES Examples of the present invention will be described below with reference to FIGS.
Will be described with reference to.

FIG. 1 is a block diagram showing the structure of a velocity error detecting device in an embodiment of the present invention.

The Δθ given to the input terminal 1a represents the velocity error between the respective Hs as described above, and the polarity thereof can be positive or negative as shown in FIG. Then, the absolute value of the velocity error amplitude is calculated, and the division circuit 15 shown in FIG.
Is inputted as an ABS signal to the input terminal 5b.

In the division circuit 15, the up-counter 55 is cleared using the SP signal of the input terminal 5c as a reference signal, and at the same time, the ABS signal is fetched by the switch 53.

The D flip-flop 54 holds the output of the switch 53 for one clock and feeds it back to the subtractor 51. The subtractor 51 subtracts the constant "N" set in the input terminal 5a from the fed-back data, the up counter 55 counts up only when the result is positive, and the switch 52 selects the output of the subtractor 51. .

Then, as a result of performing the above calculation until the output of the subtractor 51 becomes negative, the output of the up counter 55 is output as the quotient, and the output of the D flip-flop 54 is output as the remainder to the output terminals 5d and 5e, respectively. .

The correction signal generation circuit 12 having the configuration shown in FIG.
Is a circuit for cumulatively adding the remainders obtained by the division circuit 15 to detect a carry to the integer part and generating a correction signal thereof.

The switch 23 selects the constant "0" based on the SP signal at the input terminal 2b, and the D flip-flop 24 is cleared at the next clock.

The div1 signal which is the output of the quotient of the division circuit 15 given to the input terminal 2a is cumulatively added by the adder 21 with the feedback signal from the D flip-flop 24.

Then, the subtractor 22 subtracts the constant "N" from the output of the adder 21, and the switch 23 selects the output of the subtractor 22 if the result is positive and the output of the adder 21 if the result is negative. To do.

The sign bit of the subtractor 22 controls the switch 23 and, at the same time, is output as an SNG2 signal from the output terminal 2c.

This circuit is basically an integrator circuit that receives the div1 signal as an input. However, it does not overflow with a power of 2 and overflows when it exceeds a constant "N". This is cumulative addition of the remainder, that is, the value after the decimal point,
It means that overflow occurs when carry to the integer part occurs. Therefore, the sign bit of the subtractor 22 can be used as a correction signal for the quotient.

The correction data generation circuit 13 outputs the SNG1 signal which is the sign bit of Δθ and the S signal from the correction signal generation circuit 12.
This is a circuit for generating quotient correction data based on the NG2 signal.

FIG. 3 shows the configuration. For the sake of explanation, it is assumed that all calculations are performed in 2's complement.

As can be seen from the waveform diagram of FIG. 6 (c),
The velocity error is either monotonically increasing or monotonically decreasing, and either one can be known by the polarity of the SNG1 signal. That is, when positive, the input terminal 3a
Is "0", the output of the XOR gate 31 is all "0", and the output of the XOR gate 31 is all "1" when it is negative. The signal with "1" added as a new LSB of this signal is AND
It is input to the gate 32. This operation means that the complement of 2 is set to "1" when the velocity error is monotonically increasing, and "-1" is set when the velocity error is monotonically decreasing.

The SNG2 signal given to the input terminal 3b is a signal for judging whether or not the quotient needs to be corrected.
That is, when this signal is "0", the NOT gate 3
The AND gate 32 is activated by 3 and the correction data is output to the output terminal 3c.
The D gate 32 is masked and the correction data is not output.

Therefore, by adding the output of the correction data generation circuit 13 and the output of the quotient of the division circuit 15 by the adder 16, even if the velocity error is Δθ ≧ N, the velocity error within one line The correction data can be accurately generated.

The integrating circuit 14 is a circuit for cumulatively adding the output of the adder 16, and its configuration is shown in FIG.

Based on the SP signal from the input terminal 4c, the switch 43 causes the phase error θ of 1H before applied to the input terminal 4b.
Select _n-1 . The D flip-flop 42 feeds back this θ _n-1 to the adder 41 at the next clock, and the adder 1 continues for N clocks until the next SP signal is input.
The correction data which is the output of No. 6 will continue to be cumulatively added.

As a result, at the output terminal 4d, the velocity error θ (I) within one line from the phase error θ _{n - 1} 1H before the time base error to the current phase error θ _n ,
(I = 0 to N-1) will be detected and output.

[0040]

As described above, in the present invention, a circuit mainly composed of an adder, a subtractor, a switch and a D flip-flop is used as a means for detecting the velocity error in one line, and the ROM and the multiplier are No need at all.

Further, even if the velocity error gradient is "1" or more, a simple division circuit is provided to divide into a quotient and a remainder, so that the detection accuracy can be maintained without increasing the number of bits of the operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a velocity error detection device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a correction signal generation circuit 12 in FIG.

3 is a block diagram showing a specific configuration of a correction data generation circuit 13 in FIG.

4 is a block diagram showing a specific configuration of an integrating circuit 14 in FIG.

5 is a block diagram showing a specific configuration of a division circuit 15 in FIG.

FIG. 6 is a waveform diagram showing a time base error and a velocity error.

FIG. 7 is a block diagram showing a specific configuration of a conventional velocity error detection device.

[Explanation of symbols]

 11 Absolute value circuit 12 Correction signal generation circuit 13 Correction data generation circuit 14 Integration circuit 15 Division circuit 17 Delay circuit 16, 21, 41, 74 Adder 22, 51 Subtractor 23, 43, 52, 53 Switch 24, 42, 54 D flip-flop 55 up counter 31 XOR gate 32 AND gate 33 NOT gate

Claims (3)

(57) [Claims] 1. A signal generated between two lines of a reproduced video signal.
Of the reproduced video signal in order to detect the locality error.
Input that is the difference between the phase error on the nth line and the n-1th line.
The absolute value circuit that takes the absolute value of the force signal, and the absolute value circuit that is taken in based on the 1-bit start pulse.
The output of the logarithm circuit is the sample for one line of the reproduced video signal.
Divide by the constant "N" that represents the number of pulling, and as a result
The quotient which is the interpolation value for each sample and the decimal part of the interpolation value
A division circuit for outputting a certain remainder, a delay circuit for delaying the start pulse for a predetermined period, and the delay circuit as a signal for correcting the value of the quotient.
For each sample, the remainder obtained based on the output of
Cumulative, and the polarity changes depending on whether there is a carry to the integer part.
A correction signal generating circuit that outputs a 1-bit signal that is
Data "0", and when it is "1", the sign bit of the input signal is
Correction data “1” if the polarity of the
Correction data generation circuit that outputs correction data "-1"
And an addition for adding the quotient to the output of the correction data generation circuit
And the playback video captured based on the output of the delay circuit
The phase error of the n-1th line of the signal and the output of the adder are
As input, velocity error detection apparatus having an integrating circuit for outputting a detection signal of the velocity error, the. 2. The correction signal generating circuit cumulatively adds the output of the dividing circuit taken in based on the output signal of the delay circuit by using an adder, and when the addition result becomes a constant “N” or more, Take the configuration to feed back the difference value to the adder,
The velocity error detection device according to claim 1, wherein the velocity error detection device is a circuit that outputs a sign bit as a result of subtracting a constant "N" from the addition result as a quotient correction signal. 3. The velocity error detecting device according to claim 1, wherein the integrating circuit is a circuit for cumulatively adding the correction data of the velocity error to the time base error.