JP2968730B2 - Skew correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a skew correction circuit, and more particularly to a skew correction circuit for obtaining a skew correction value for converting quantized and quantized data into another sampling frequency data.

[0002]

2. Description of the Related Art In the processing of quantized data, when analog quantized data is sampled using a PLL to generate accurate digital quantized data, the sampled digital data is further converted to data having a desired sampling frequency (hereinafter referred to as data). When converting to a (quantized data) value, a skew correction circuit for correcting a phase (time) shift between the horizontal synchronization signal and the sampling clock to be converted and a difference from an expected value due to the phase shift, that is, a skew is required. And

The data value of the quantized data does not always match the expected data value, and the sampling timing does not match. It is necessary to perform interpolation for increasing the data value and thinning-out for reducing the data value by skew correction for that purpose.

The skew correction method will be described with reference to FIGS. 4A and 4B showing examples of data thinning and data interpolation. FIG. 4 shows actual sampling data A and expected data B. Are expressed as time on the horizontal axis and as data values on the vertical axis.

When the skew correction value is k, a certain time T
The expected data Mn at n and the actual sampling data have the following relationship. Sampling data at time Tn
Assuming that n is the data after one sampling, Sn + 1, and the data after one sampling is Sn-1, the following equation is satisfied in the case of thinning.

Mn = Sn + k · (Sn + 1−Sn) (1) Similarly, in the case of interpolation, the following equation holds.

Mn = Sn−k · (Sn−Sn−1) (2) Assuming that the period of the horizontal synchronization signal, that is, the horizontal synchronization period is 1H, the skew correction value k is Ask as follows. From FIG. 4, since k = b / a, the time of 1H is set to Th, 1
Assuming that the number of samples of H is Hcnt and the expected value is Href, the skew correction value k in the case of thinning is represented by the following equation. k = (Mn−Sn) / (Sn + 1−Sn) (3) = b / a = [{(Th / Href) · n} − ｛(Th / Hcnt ) · N｝] / (Th / Hcnt) = (Hcnt−Href / Href) · n (4) Similarly, in the case of interpolation, the following equation holds. k = (Mn−Sn) / (Sn−Sn−1) (5) = b / a = [{(Th / Hcnt) · n} − ｛(Th / Href) · n｝] / (Th / Hcnt) = (Href−Hcnt / Href) · n (6) Since k> 0 at this time, (Hcnt−Href) If> 0, thinning is performed, and if (Hcnt−Href) <0, interpolation is performed.

From equations (4) and (6), the skew correction value k
Calculates the actual sampling number Hcnt of 1H by a counter, divides the difference from the expected value Href by the expected value Href,
It will be determined by integration.

FIG. 5 is a block diagram showing a conventional skew correction circuit for performing the skew processing. Referring to FIG. 5, the conventional skew correction circuit corrects the quantized data VD of the input quantized data using a skew correction value k. A correction unit 1, a synchronization separation circuit 2 for extracting a horizontal synchronization signal H from the quantized data VD, and a digital PLL unit which synchronizes with the signal H and outputs a PLL clock CP in response to the supply of the horizontal synchronization signal H 3 and a skew measuring unit 5 that receives a supply of a PLL clock CP and calculates a skew correction value k.
And

Next, the operation of the conventional skew correction circuit will be described with reference to FIG. 5. Quantized data VD sampled at an arbitrary frequency is supplied to the sync separation circuit 2 and the skew correction unit 1. . The synchronization separation circuit 2 extracts the horizontal synchronization signal H and supplies it to the PLL circuit 3. PLL
The VCO 32 of the circuit 3 locks in response to the phase of the horizontal synchronization signal H. The skew measurement unit 5 calculates the skew correction value k by counting the number of clocks CP in one cycle of the VCO 32, that is, in the cycle of 1H. The skew correction unit 1 performs skew correction on the quantized data VD using the skew correction value k supplied from the skew measurement unit 5, and generates a corrected quantized data signal DC.

The PLL section 3 includes a phase detection circuit 31 and a VC
O32 and a PLL filter 33 are provided.

Next, referring to FIG. 6, which shows a block diagram of the skew correction unit 1 for realizing the equations (1) and (2), the skew correction unit 1 delays the quantized data VD by a delay circuit (not shown). The flip-flop (FF) 11 which receives the delayed data VDD generated by the clock CP and delays it by one clock to output the data F1, and the data F1
FF12 receiving the supply of the data F2 and outputting the data F2, an adder 13 for subtracting the delayed data TDD and the data F1 to generate a subtraction signal A1, an adder 14 for subtracting the data F1 and F2 and generating the subtraction data A2, A switch 15 for selecting either one of the subtraction data A1 and A2 and outputting the selection subtraction data AS in response to the control of the interpolation thinning signal, and multiplying the skew correction value k by the selection subtraction data AS and multiplying data M
k, a multiplier 16 for outputting the multiplication data Mk and a signal F1.
And an adder 17 that outputs the quantized data DC that has been subjected to the skew correction by adding.

Next, the operation of the skew correction unit 1 will be described with reference to FIG. 6. First, in order to secure the time required for the interpolation processing, as described above, the input quantized data V
Since it is necessary to generate the delay data VDD by delaying D, a delay circuit is actually provided before the circuit of FIG. The delay data VDD is supplied to the FF 11 for each clock CP,
The FF 11 supplies the output data F1 to the FF 12 in response to the supply of the delay data VDD. Data F1 is at time T
n, the adder 13 calculates the difference between the data F1 at time Tn and the data VDD after one clock,
The adder 14 calculates the difference between the data F1 at Tn and the data F2 one clock before.

The switch 15 switches between data thinning and interpolation, and is controlled by an interpolation thinning signal IP. The output data A1 of the adder 14 is used for thinning, and the output data A1 of the adder 13 is used for interpolation. A2 is input to the multiplier 16 respectively. The adder 17 receives the output data Mk of the multiplier 16 and the data F1 and receives the expression (1),
The calculation of (2) is realized.

Next, referring to FIG. 7, which shows the skew measuring section 5 as a block, the skew measuring section 5 counts clocks CP supplied from the PLL section 3 and counts data H.
counter 51 that outputs cnt, and count data Hcnt
And a calculation circuit 52 that receives the supply of the frequency reference data Href and calculates a skew correction value k.

The arithmetic circuit 52 receives the supply of the count data Hcnt and the reference data Href, and calculates the expression (Hcnt-Hre
f) A computing unit 521 for calculating / Href and an integrator 52
2 is provided.

The counter 51 counts the count data Hcnt of the sampling data during 1H of the quantized data VD.
The calculator 521 calculates the formula (Hcnt−Href) / Href, and the integrator 522 integrates the calculation result to obtain a correction value k.

[0018]

In the conventional skew correction circuit, the number of samplings of actual data during 1H is counted, and the skew correction value k is obtained from the relationship between the actual data value and the expected data value. Since the actual data sampling number during the period is determined by the sampling clock frequency, there is a disadvantage that when the sampling clock is asynchronous, an accuracy higher than the pulse width of the sampling clock cannot be obtained.

In order to improve the accuracy, it is necessary to calculate an average of a plurality of H actual data values and expected data values. This requires hardware such as a counter and a large-capacity ROM. There was a disadvantage that the scale was increased.

An object of the present invention is to provide a skew correction circuit with a smaller circuit scale than the sampling clock pulse width.

[0021]

According to the present invention, there is provided a circuit for obtaining a skew correction value k using an increment value of a VCO of a digital horizontal PLL circuit. .

[0022]

A skew correction circuit according to the present invention comprises: a sync separation means for extracting a horizontal synchronization signal from quantized video data obtained by digitizing a video signal; and a VCO of a VCO in response to the supply of the horizontal synchronization signal. A digital PLL means for synchronizing with the horizontal synchronizing signal by changing an increment value, and comparing the increment value with a predetermined expected expected value every time a clock signal is supplied, and A skew measuring unit for measuring a skew which is a difference between an expected value of the quantized video data due to a phase difference between the sampling clock and the horizontal synchronization signal and calculating a skew correction value; and Skew correction means for skew correction of the quantized video data.

[0023]

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which constituent elements common to those in FIG. The skew correction circuit according to the present embodiment shown in this figure includes a skew correction unit 1, a synchronization separation circuit 2, and a PLL unit 3 which are common to those of the related art, and an increment of the PLL unit 3 instead of the skew measurement unit 5. The skew measurement unit 4 receives the supply of the value Hinc and calculates a skew correction value k from the increment value Hinc.

Referring to FIG. 2, which shows a block diagram of the skew measurement block 4, an adder 41 for calculating a difference D1 between an increment value Hinc and an expected value Hwant every clock, a difference D1 and a data F3 every clock. Adder 4 that adds (ie, integrates) and outputs difference D2
2, the difference D between the increment value Hinc and the difference D2
3 and carry CO when D3 is positive.
, An FF 44 that outputs data F3 in response to the supply of data S1, a switch 45 that switches between the differences D2 and D3 in response to the supply of data CO,
A switch 46 for outputting a VCO offset value OF, data S1, and switching data S2 for each H, and a divider 47 for dividing the difference D2 by an increment value Hinc and outputting a skew correction value k.

Next, the operation of this embodiment will be described with reference to FIG. 1. First, the quantized data VD is supplied to the skew correction unit 1 and the synchronization separation circuit 2 as in the conventional case, and Quantized data V sampled at frequency
D is supplied to the sync separation circuit 2 and the skew correction unit 1. The synchronization separation circuit 2 extracts the horizontal synchronization signal H,
Supply to circuit 3. The phase detection circuit 31 of the PLL circuit 3 detects a phase difference between the supplied horizontal synchronization signal H and the clock CP output from the VCO 32, and outputs a phase error signal PD. The PLL filter 33 outputs the VCO control signal CV in response to the supply of the phase error signal PD. VCO3
2 synchronizes (locks) with the horizontal synchronization signal H by changing the oscillation (clock CP) frequency in response to the control of the VCO control signal CV so that the error value of the phase error signal PD becomes zero. The increment (decrease) of the clock CP frequency by the VCO control signal CV at this time is the increment value Hinc.

The skew measuring section 4 calculates the increment value H
The skew correction value k is calculated for each clock by comparing inc with the expected value Hwant. The skew correction unit 1 performs skew correction on the quantized data VD using the skew correction value k supplied from the skew measurement unit 4, and generates a corrected quantized data signal DC.

The skew correction value k is obtained based on the horizontal synchronization signal H from the positional relationship between the actual sampling point and the desired sampling point. Therefore, the correction value k can be obtained by using the increment value of the VCO in the PLL circuit locked to the horizontal synchronization signal H.

Next, a skew correction method will be described with reference to FIGS. 3A and 3B showing examples of data thinning and data interpolation according to the present embodiment. The relationship between the sampling data A and the expected data B is represented by the number of samples S on the horizontal axis and the count value N of the clock CP on the vertical axis.

The actual increment value of the VCO in one clock is Hinc, and the expected value Hwan obtained from the desired number of data is Hinc.
Assuming that t, the skew correction value k at the time of thinning is obtained as follows from Expression (3). k = (Mn−Sn) / (Sn + 1−Sn) = (n · Hwant−n · Hinc) / {(n + 1) Hinc−n · Hinc} = n · (Hwant−Hinc) / (Hinc) (7) Similarly, in the case of interpolation, the following equation holds from equation (5). k = (Mn−Sn) / (Sn−Sn−1) = (n · Hinc−n · Hwant) / {n · Hinc− (n−1) Hinc} = n · (Hinc−Hwant) / (Hinc) (8) From equations (7) and (8), the skew correction value k is obtained by integrating the difference between the increment value Hinc and the expected value Hwant for each clock, and dividing the result by Hinc. It can be seen that the value obtained is as follows.

When (Hwant-Hinc)> 0, the data is decimated, and when (Hwant-Hinc) <0, the data is interpolated. The relationship between the subsequent data and k at the time of interpolation is the relationship between the current data and the data one clock before. The integrated value for each clock is Hinc
Is exceeded, k is obtained using the remainder obtained by subtracting Hinc from the integrated value. In the case of thinning, k becomes the relationship between the data after one clock and the data after two clocks from the current data. The relationship between the data one clock before and the data two clocks before is obtained. Thereafter, each time the integrated value exceeds Hinc, the position of the data is advanced by one clock in thinning and delayed by one clock in interpolation.

In the case of asynchronous sampling, an offset occurs due to time mismatch between the leading edge of the horizontal synchronization signal and the sampling (VCO) clock CP. Therefore,
It is necessary to add or subtract an offset to the integral part of (Hwant-Hinc).

FIG. 3C shows the relationship between the offset and the data.
It is shown in (D). Assuming that the time when the value of the VCO clock CP exceeds 0 is the leading edge of the horizontal synchronization signal, the value of the clock CP at this time corresponds to the offset. From FIG. 2C, it is necessary to add (Hinc-CP count value N) at the time of data thinning and to add the VCO value at the time of data interpolation. However, it must be noted that in the case of thinning, data is delayed by one clock.

Since the parameter increment value Hinc used for obtaining the skew correction value k in the present invention is an existing value, the circuit scale can be reduced. Further, if the VCO bit width is set so that the accuracy of the PLL is equal to or higher than the sampling clock, the accuracy of the skew correction can be improved to the same level as that of the PLL.

Referring again to FIG. 2, the operation of the skew measuring section 4 for executing the above-described operation will be described.
1 calculates the difference D1 between the increment value Hinc and the expected value Hwant = (Hinc−Hwant) for each clock, and supplies the difference to the adder. The adder 42 normally adds the data D3 corresponding to the difference D2 of the previous clock and the difference D1, that is, adds the difference D2, which is an integrated value for each clock, to the divider 4
7, the adder 43 and the switch 45. Divider 4
7 calculates and outputs the skew correction value k by dividing the difference D2 by the increment value Hinc. The adder 43 calculates a difference D3 between the difference D2 and the increment value Hinc and supplies the difference D3 to the switch 45. Here, the adder 43 outputs the carry CO when D3 is positive, that is, when the difference D2 (= D1) exceeds the increment value Hinc, and the switch 45
Is switched to the difference D3 side and supplied to the switch 46 as selection data S1. The switch 45 selects this selection data S1
(= Difference D3) is supplied to the FF 44 as selection data S2. The FF 44 supplies the adder 42 with the data F3 delayed by one clock in response to the supply of the selection data 4D.
As a result, the difference D1, that is, (Hinc−Hwan)
When the added value of t) exceeds the increment value Hinc, the remainder circulates, and the required bit width can be reduced. The switch 46 normally selects the selection signal S1 as the selection signal S2, and selects the offset value OF supplied from the VCO every 1H as the selection signal S2.

[0035]

As described above, the skew correction circuit of the present invention measures the skew of quantized video data by comparing the increment value and the expected increment value each time the clock signal is supplied, and calculates the skew correction value. Since the skew correction value k is obtained by using a known value of the increment of the VCO, the counter required in the past can be reduced, and the skew correction accuracy can be reduced to the same level as the VCO control accuracy. Can be improved, and an increase in circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a skew correction circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a skew measuring unit in FIG. 1;

FIG. 3 is an explanatory diagram for explaining a correction method of each of data thinning and data interpolation in the skew correction circuit of the present embodiment.

FIG. 4 is an explanatory diagram for explaining each correction method of data thinning and data interpolation in a conventional skew correction circuit.

FIG. 5 is a block diagram illustrating an example of a conventional skew correction circuit.

FIG. 6 is a block diagram illustrating a configuration of a skew correction unit in FIG. 5;

FIG. 7 is a block diagram illustrating a configuration of a skew measuring unit in FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 skew correction unit 2 synchronization separation circuit 3 PLL unit 4, 5 skew measurement unit 11, 12, 44 flip-flop (FF) 13, 14, 17, 41, 42, 43 adder 15, 45, 46 switch 16 multiplier 47 Divider 51 Counter 52 Arithmetic circuit 521 Arithmetic unit 522 Integrator

────────────────────────────────────────────────── ─── of the front page continued (72) inventor Inagawa TsuyoshiRyo Kanagawa Prefecture, Nakahara-ku, Kawasaki, Kosugi-cho, chome 403 No. 53 NEC IC microcomputer system within Co., Ltd. (58) investigated the field (Int.Cl. ^6, (DB name) H04N 5/91-5/956

Claims (3)

(57) [Claims] 1. A synchronization separating means for extracting a horizontal synchronizing signal from quantized video data obtained by digitizing a video signal, and changing the increment value of a VCO in response to the supply of the horizontal synchronizing signal to thereby generate a horizontal synchronizing signal. Digital PLL means for synchronizing, and comparing the increment value with a predetermined expected expected value every time a clock signal is supplied, to obtain a phase difference between a sampling clock at the time of quantization of the quantized video data and the horizontal synchronization signal. A skew measuring unit for measuring a skew which is a difference from the expected value of the quantized video data and calculating a skew correction value; and a skew correction unit for performing a skew correction of the quantized video data using the skew correction value. And a skew correction circuit. A second adder for calculating a first difference that is a difference between the increment value and the expected increment value each time a clock signal is supplied; a skew measuring unit; A second adder that adds the difference every clock and outputs an integrated value; and a second adder that is a difference between the integrated value and the increment value.
And a third adder for calculating a difference between the second difference and the carry signal when the second difference is positive; and a third adder for calculating the difference between the integral value and the second difference in response to the supply of the carry signal. A first switch for selecting one of the signals and outputting the selected signal as a first selection signal; and normally outputting the first selection signal as a second selection signal and outputting the VCO offset every one cycle of the horizontal synchronization signal. A second switch for outputting the value as the second selection signal
, A flip-flop circuit that delays the second selection signal by one clock and outputs the delay signal, and a divider that divides the integral value by the increment value to calculate the skew value. The skew correction circuit according to claim 1, wherein: 3. The skew correction circuit according to claim 1, wherein said expected increment value is programmable.