JP2532608B2 - Time axis correction device - Google Patents

Description

TECHNICAL FIELD The present invention is to extract the periodic signal from an input signal including the periodic signal, such as the periodic signal in a television signal, and measure the period. The present invention relates to a time axis correction device that corrects the periodicity of an input signal to perfect the periodicity.

2. Description of the Related Art Generally, in a magnetic recording / reproducing apparatus for audio signals or video signals, an output signal recorded / reproduced due to a change in running speed of a tape or the like has a time axis of the signal fluctuated and jitter occurs. In order to correct the jitter, a time axis correction device as shown in FIG. 4 is used.

In FIG. 4, the horizontal synchronizing signal is separated from the reproduced video signal input from the input terminal 1 by the horizontal synchronizing separating circuit 4. In the periodicity detection circuit 5, the separated horizontal synchronizing signal is phase-compared with the horizontal synchronizing signal delayed by one period, for example, to detect a periodical variation, and the detected periodical variation is output as a voltage variation. The voltage fluctuation is converted into a phase fluctuation component integrated by the integrating circuit 6. The phase fluctuation component is applied as a control voltage for the voltage controlled oscillator 7.

In the semiconductor element delay circuit 3, by receiving the reproduced video signal as an input from the input terminal 1 and by receiving the oscillation output of the voltage controlled oscillator 7 as a clock, the delay time generated in the semiconductor element delay circuit 3 is controlled. Jitter is corrected.

However, with the above configuration, it is difficult to instantaneously perform the integration in the integrating circuit 6 in synchronization with the horizontal synchronizing signal and to completely hold the output value integrated over the period of the horizontal synchronizing signal. Is. The present invention is a means capable of instantaneously executing integration and holding an integration result for a required period (means for realizing an instantaneous perfect integration circuit).
By providing the jitter frequency range that satisfies the Nyquist sampling theorem as a correction range, and providing a time axis correction circuit that enables a large jitter correction amount by accumulating error signals. is there.

Means for Solving the Problems A time axis correction device of the present invention receives a periodic signal separation circuit that extracts a periodic signal from an input signal and an output from the periodic signal separation circuit, and receives each period of the periodic signal. A counter that counts the number of clock signals existing in the period, and an error detection circuit that outputs an error signal of a digital value corresponding to the difference between the count value of the counter and a reference value,
A digital cyclic filter that receives the error signal as an input and that operates using the output from the periodic signal separation circuit as a clock, and a D / A that converts the cumulative value of the error signal output from the digital cyclic filter into an analog value. It comprises a converter, a frequency controlled oscillator that receives the output of the D / A converter as a control signal, and a semiconductor element delay circuit that receives the input signal as an input and receives the output of the frequency controlled oscillator as a clock.

Operation According to the above configuration, the period of the periodic signal is detected as a digital value by the counter, and the error detection circuit uses the digital addition circuit (full adder) to obtain the difference from the reference value and output the error component as a digital value. I am letting you. Further, as the integrating circuit, a cyclic digital filter that receives the periodic signal generated by the periodic signal separation circuit as a clock pulse and that receives the error component as an input is used to synchronize with the period of the periodic signal. The cumulative integration of error components is instantaneously executed, and the integrated value can be held completely for a required period.

Embodiment FIG. 1 is a block diagram of a time axis correction device according to an embodiment of the present invention.

In FIG. 1, the reproduced video signal input from the input terminal 1 is separated into a horizontal synchronizing signal by a horizontal synchronizing signal separating circuit 4, one of which is output to a counter 8 to detect its cycle, and the other of which is an integrating circuit 10. Is output as a clock pulse.

The counter 8 receives a counter clock of about 50 to 100 MHz, counts the number of clocks for the counter from the rising edge of the horizontal synchronizing signal to the rising edge (or the falling edge of the horizontal synchronizing signal), and outputs the horizontal synchronizing signal. The count result is output in synchronization with the rising (or falling) of the signal. When the counter clock of 100 MHz is used, the counter 8 outputs a digital signal of 13 BIT, the count result is output, and the jitter can be corrected with a resolution of 10 nsec.

The error detection circuit 9 is a general digital operation circuit, and by calculating the count result from the counter 8 and the reference value, the difference between the reference value and the count result is taken as an error component to the integration circuit 10 for the horizontal synchronization signal. Output in synchronization with the rising edge (or falling edge) of.

An internal configuration diagram of the integrating circuit 10 is shown in FIG. The integrating circuit 10 is a general recursive filter that receives a horizontal synchronizing signal as a clock. In FIG. 2, the latch circuit
Reference numeral 14 latches the output of the adder circuit 13 in synchronization with the rising (or falling) of the horizontal synchronizing signal and holds it for one horizontal synchronizing period, thereby delaying the output of the adder circuit 13 by one horizontal synchronizing period. The adder circuit 13 receives the error component sent in synchronization with the horizontal synchronizing signal and the adder circuit 13
The data output by the latch circuit 14 and delayed by one horizontal synchronizing period are added. This means that all the error component data from the past are instantaneously added (integrated) in synchronization with the horizontal synchronization signal, and the horizontal synchronization period is held.

The integration result output by the integrating circuit 10 in synchronization with the horizontal synchronizing signal is converted into an analog voltage value by the D / A converter 11.

The voltage controlled oscillator 7 receives the analog voltage value as a control voltage and oscillates a clock to the semiconductor element delay circuit 3 (a charge-coupled element which is a clock-driven analog variable delay line and is abbreviated as CCD hereinafter). .

The frequency of the clock to the CCD3 is frequency-modulated by the integration result output in synchronization with the horizontal synchronizing signal, and the reproduced video signal input from the input terminal 1 is CC
The delay time delayed by D3 will change.
Due to the change in the delay time, the jitter of the reproduced video signal is corrected.

The operation of the time axis correction apparatus of the above embodiment will be described in detail with reference to FIG. It is assumed that the counter 8 and the integrating circuit 10 in FIG. 1 are operating in synchronization with the falling edge of the horizontal synchronizing signal.

In FIGS. 1 and 3, the counter 8 counts the counter clock during the period from the rising edge to the falling edge of the period A _n horizontal synchronizing signal, and outputs the count result at time t _n . Based on the output count result, the error detection circuit 9 instantaneously calculates the difference from the reference value, and similarly outputs the error component n _n at time t _n . Integrating circuit 10 adds all of the error components up to time t _n, in total, in synchronization with the timing of time t _n outputs the integration result m _n, holds up to time t _n +1.

In a third diagram, it is assumed jitter was not until time t _0, + n ₁ in the period A _1, there is jitter -n ₃ in the period A _3, periods A
_It is assumed that there is no jitter at ₂ and A ₄ . In this case, the error component until time t ₀ is 0, and the integration result m ₀ in the period A ₁ is also 0. At time t ₁ , an error component of + n ₁ is detected, so the integration result m ₁ of the period A ₂ is m ₁ = 0 + n ₁ = n ₁ . Times of Day
At t ₂ , no jitter is detected and n ₂ = 0. At this time, the integration result m ₂ of the period A ₃ is m ₂ = n ₁ + 0 = n ₁ and is the same as the period A ₂ . At time t ₃ , an error component of −n ₃ is detected,
The integration result m ₃ of the period A ₄ is m ₃ = n ₁ −n ₃ . At time t _4, a n ₄ = 0, the period A ₅ in _{m 4 = n 1 -n 3 +} 0 = n 1 -
n ₃ is the same as period A ₄ .

Next, the integration result m _n is D / A converted to the analog voltage value v _n
Is converted to.

v _n = K ₁ × m _n (1) where K ₁ is the D / A conversion coefficient The voltage controlled oscillator 7 in FIG.
It receives v _n as a control voltage, oscillates according to the second equation at the frequency, and outputs it as the clock of CCD3.

= _{0 0} + K ₂ × v _n …… Second formula where ₀ is the oscillation frequency when v _n = 0 (free-run frequency) K ₂ is the control constant from the 1st and 2nd formulas = ₀ + K ₁ × K ₂ × m _n ...... 3rd formula = ₀ + K + m _n = ₀ + Δ ₀ where Δ ₀ = K × m _n , K = K ₁ × K ₂ Here, the delay time when the CCD3 receives a clock of frequency ₀ T _D is set to approximately match the horizontal synchronization period T _H. Here, CC with a clock frequency of ₀
The input signal input to D3 is ₀ + during the next horizontal synchronization period.
When output at a clock frequency of Δ _0, it is roughly estimated that ΔT≈−T _k × Δ ₀ Fifth expression, where T _K is the proportional constant, and compression and expansion on the time axis shown in the fifth equation occur.

In the period A _1, an input signal input in the period A _{0 0} becomes the clock frequency is output at ₀ becomes the clock frequency, the input signal of the period A ₀ is not subject to change in the time axis in CCD 3. In the period A _2, an input signal input in the period A _{1 0} comprising clock frequency is output at _{0 +} K × m ₁ becomes the clock frequency, the _{CCD3, ΔT 1 = -T K ×} k × m 1 = - _TK × K × n ₁ ... The input signal of the period A ₁ is output due to the compression of the time axis of the sixth equation. In a period A _{3, 0 +} K × input signal input to CCD3 the period A ₂ in n ₁ becomes the clock frequency, and outputs at the same clock frequency _{0 +} K × n _1, the time of the input signal of the period A ₂ No axis changes occur. In period A ₄ ,
_{0 +} to K × CCD 3 at n ₁ becomes the clock frequency of the input signal which is input in the period A _3, and outputs at _{0 + K × n 1 -K ×} n 3 becomes the clock frequency, the CCD3, ΔT ₃ = T _K × In response to the expansion of the time axis of K × n _3, the input signal of the period A ₃ is output. In the period A ₅ , the input signal input to the CCD ₃ in the period A ₄ at the clock frequency of ₀ + K × n ₁ −K × n ₃ is
The same clock frequency of ₀ + K × n ₁ −K × n ₃ is output, and the time axis of the input signal in the period A ₄ does not change. That is, when the time axis correction circuit is configured with one CCD delay line, if the horizontal period of the same length different from the regular length continues, if the integration method is the cumulative type, the horizontal period is shortened. Stretch is obtained.

The above results show that the compression and expansion of the time axis occur in an inversely proportional relationship in response to the counting result of counting the period, that is, by appropriately setting the constants T _K , K,
Jitter can be corrected.

As described above, according to the present invention, the horizontal synchronizing period is counted by the counter using the counter clock and the error component of the horizontal synchronizing period which is the jitter component is detected by the digital value. By inputting the error component as an input to the digital recursive filter and using the horizontal sync signal as the clock, the cumulative integration is instantaneously executed in synchronization with the horizontal sync signal, and the integrated value is perfectly measured over the horizontal sync period. Hold on. With the instantaneous perfect integration circuit shown above,
A highly accurate time axis correction device can be easily realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a time axis correction device in an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of an integrating circuit in FIG. 1, and FIG. 3 is an operation in an embodiment of the present invention. The timing diagram shown in FIG. 4 is a block diagram of a conventional time axis correction device. 1 ... Input terminal, 2 ... Output terminal, 3 ... Semiconductor element delay circuit (CCD), 4 ... Horizontal sync separation circuit, 5 ... Periodicity detection circuit, 6 ... Integration circuit, 7 ... Voltage control Oscillator,
8 ... Counter, 9 ... Error detection circuit, 10 ... Integration circuit (digital cyclic filter), 11 ... D / A converter, 13
…… Adder circuit, 14 …… Latch circuit.

Claims (1)

(57) [Claims] 1. A periodic signal separation circuit for extracting a periodic signal from an input signal, and an output from the periodic signal separation circuit to count the number of clock signals existing in each period of one period of the periodic signal. A counter, an error detection circuit that outputs an error signal of a digital value corresponding to the difference between the count value of the counter and a reference value, the error signal as an input, and the output from the periodic signal separation circuit as a clock. A digital recursive filter operating as, a D / A converter for converting the error signal, which is the output from the digital recursive filter, of the accumulated error signal into an analog value, and the D / A converter A frequency controlled oscillator that receives an output as a control signal, and a CCD that receives the input signal as an input and receives the output of the frequency controlled oscillator as a clock Become more time base corrector the extending line circuit.